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https://github.com/Dr-Noob/cpufetch.git
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1 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
|
d134f68ffe |
25
Makefile
25
Makefile
@@ -70,27 +70,12 @@ $(error Aborting compilation)
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OUTPUT=cpufetch
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else
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arch := $(shell cc -dumpmachine)
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arch := $(firstword $(subst -, ,$(arch)))
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ifeq ($(arch), $(filter $(arch), x86_64 amd64 i386 i486 i586 i686))
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SRC_DIR=src/x86/
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SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
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HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h
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CFLAGS += -DARCH_X86 -std=c99
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else ifeq ($(arch), $(filter $(arch), arm aarch64_be aarch64 arm64 armv8b armv8l armv7l armv6l))
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SRC_DIR=src/arm/
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SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_COMMON)pci.c $(SRC_DIR)udev.c sve.o
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HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_COMMON)pci.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
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CFLAGS += -DARCH_ARM -std=c99
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else
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# Error lines should not be tabulated because Makefile complains about it
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$(warning Unsupported arch detected: $(arch). See https://github.com/Dr-Noob/cpufetch#1-support)
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$(warning If your architecture is supported but the compilation fails, please open an issue in https://github.com/Dr-Noob/cpufetch/issues)
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$(error Aborting compilation)
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endif
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# Assume x86_64
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GIT_VERSION := ""
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SRC_DIR=src/x86/
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SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
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HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h
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CFLAGS += -DARCH_X86 -std=c99
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SANITY_FLAGS += -Wno-pedantic-ms-format
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OUTPUT=cpufetch.exe
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endif
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@@ -63,7 +63,7 @@ cpufetch is a command-line tool written in C that displays the CPU information i
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| OS | x86_64 / x86 | ARM | RISC-V | PowerPC |
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|:-----------:|:------------------:|:------------------:|:------------------:|:------------------:|
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| GNU / Linux | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
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| Windows | :heavy_check_mark: | :heavy_check_mark: | :x: | :x: |
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| Windows | :heavy_check_mark: | :x: | :x: | :x: |
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| Android | :heavy_check_mark: | :heavy_check_mark: | :x: | :x: |
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| macOS | :heavy_check_mark: | :heavy_check_mark: | :x: | :heavy_check_mark: |
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| FreeBSD | :heavy_check_mark: | :x: | :x: | :x: |
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162
src/arm/midr.c
162
src/arm/midr.c
@@ -11,10 +11,6 @@
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#include "../common/freq.h"
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#elif defined __APPLE__ || __MACH__
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#include "../common/sysctl.h"
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#elif defined _WIN32
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#define WIN32_LEAN_AND_MEAN
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#define NOMINMAX
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#include <windows.h>
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#endif
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#include "../common/global.h"
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@@ -25,60 +21,6 @@
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#include "uarch.h"
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#include "sve.h"
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#if defined _WIN32
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// Windows stores processor information in registery at:
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// "HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor"
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// Within this directory, each core will get its own folder with
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// registery entries named `CP ####` that map to ARM system registers.
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// Ex. the MIDR register for core 0 is the `REG_QWORD` at:
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// "HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor\0\CP 4000"
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// The name of these `CP ####`-registers follow their register ID encoding in hexadecimal
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// (op0&1):op1:crn:crm:op2.
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// More registers can be found here:
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// https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers
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// Some important ones:
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// CP 4000: MIDR_EL1
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// CP 4020: ID_AA64PFR0_EL1
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// CP 4021: ID_AA64PFR1_EL1
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// CP 4028: ID_AA64DFR0_EL1
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// CP 4029: ID_AA64DFR1_EL1
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// CP 402C: ID_AA64AFR0_EL1
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// CP 402D: ID_AA64AFR1_EL1
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// CP 4030: ID_AA64ISAR0_EL1
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// CP 4031: ID_AA64ISAR1_EL1
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// CP 4038: ID_AA64MMFR0_EL1
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// CP 4039: ID_AA64MMFR1_EL1
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// CP 403A: ID_AA64MMFR2_EL1
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bool read_registry_hklm_int(char* path, char* name, void* value, bool is64) {
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DWORD value_len;
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int reg_type;
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if (is64) {
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value_len = sizeof(int64_t);
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reg_type = RRF_RT_REG_QWORD;
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}
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else {
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value_len = sizeof(int32_t);
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reg_type = RRF_RT_REG_DWORD;
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}
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if(RegGetValueA(HKEY_LOCAL_MACHINE, path, name, reg_type, NULL, value, &value_len) != ERROR_SUCCESS) {
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printBug("Error reading registry entry \"%s\\%s\"", path, name);
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return false;
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}
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return true;
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}
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bool get_win32_core_info_int(uint32_t core_index, char* name, void* value, bool is64) {
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// path + digits
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uint32_t max_path_size = 45+3+1;
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char* path = ecalloc(sizeof(char) * max_path_size, sizeof(char));
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snprintf(path, max_path_size, "HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\%u", core_index);
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return read_registry_hklm_int(path, name, value, is64);
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}
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#endif
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bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
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return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
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}
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@@ -266,46 +208,6 @@ struct features* get_features_info(void) {
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feat->NEON = true;
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feat->SVE = false;
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feat->SVE2 = false;
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#elif defined _WIN32
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// CP 4020 maps to the ID_AA64PFR0_EL1 register on Windows
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// https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers/ID-AA64PFR0-EL1--AArch64-Processor-Feature-Register-0
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int64_t pfr0 = 0;
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if(!get_win32_core_info_int(0, "CP 4020", &pfr0, true)) {
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printWarn("Unable to retrieve PFR0 via registry");
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}
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else {
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// AdvSimd[23:20]
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// -1: Not available
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// 0: AdvSimd support
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// 1: AdvSimd support + FP16
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int8_t adv_simd = ((int64_t)(pfr0 << (60 - 20)) >> 60);
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feat->NEON = (adv_simd >= 0);
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// SVE[35:32]
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feat->SVE = (pfr0 >> 32) & 0xF ? true : false;
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}
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// Windoes does not expose a registry entry for the ID_AA64ZFR0_EL1 register
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// this would have mapped to "CP 4024".
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feat->SVE2 = false;
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// CP 4030 maps to the ID_AA64ISAR0_EL1 register on Windows
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// https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers/ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0
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int64_t isar0 = 0;
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if(!get_win32_core_info_int(0, "CP 4030", &isar0, true)) {
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printWarn("Unable to retrieve ISAR0 via registry");
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}
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else {
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// AES[7:4]
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feat->AES = (isar0 >> 4) & 0xF ? true : false;
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// SHA1[11:8]
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feat->SHA1 = (isar0 >> 8) & 0xF ? true : false;
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// SHA2[15:12]
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feat->SHA2 = (isar0 >> 12) & 0xF ? true : false;
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// CRC32[19:16]
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feat->CRC32 = (isar0 >> 16) & 0xF ? true : false;
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}
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#endif // ifdef __linux__
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if (feat->SVE || feat->SVE2) {
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@@ -526,68 +428,6 @@ struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
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return cpu;
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}
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#elif defined _WIN32
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struct cpuInfo* get_cpu_info_windows(struct cpuInfo* cpu) {
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init_cpu_info(cpu);
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SYSTEM_INFO sys_info;
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GetSystemInfo(&sys_info);
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int ncores = sys_info.dwNumberOfProcessors;
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uint32_t* midr_array = emalloc(sizeof(uint32_t) * ncores);
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int32_t* freq_array = emalloc(sizeof(uint32_t) * ncores);
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uint32_t* ids_array = emalloc(sizeof(uint32_t) * ncores);
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for(int i=0; i < ncores; i++) {
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// Cast from 64 to 32 bit to be able to re-use the pre-existing
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// functions such as fill_ids_from_midr and cores_are_equal
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int64_t midr_64;
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if(!get_win32_core_info_int(i, "CP 4000", &midr_64, true)) {
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return NULL;
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}
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midr_array[i] = midr_64;
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if(!get_win32_core_info_int(i, "~MHz", &freq_array[i], false)) {
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return NULL;
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}
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}
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uint32_t sockets = fill_ids_from_midr(midr_array, freq_array, ids_array, ncores);
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struct cpuInfo* ptr = cpu;
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int midr_idx = 0;
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int tmp_midr_idx = 0;
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for(uint32_t i=0; i < sockets; i++) {
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if(i > 0) {
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ptr->next_cpu = emalloc(sizeof(struct cpuInfo));
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ptr = ptr->next_cpu;
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init_cpu_info(ptr);
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tmp_midr_idx = midr_idx;
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while(cores_are_equal(midr_idx, tmp_midr_idx, midr_array, freq_array)) tmp_midr_idx++;
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midr_idx = tmp_midr_idx;
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}
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ptr->midr = midr_array[midr_idx];
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ptr->arch = get_uarch_from_midr(ptr->midr, ptr);
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ptr->feat = get_features_info();
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ptr->freq = emalloc(sizeof(struct frequency));
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ptr->freq->measured = false;
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ptr->freq->base = freq_array[midr_idx];
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ptr->freq->max = UNKNOWN_DATA;
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ptr->cach = get_cache_info(ptr);
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ptr->topo = get_topology_info(ptr, ptr->cach, midr_array, freq_array, i, ncores);
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}
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cpu->num_cpus = sockets;
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cpu->hv = emalloc(sizeof(struct hypervisor));
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cpu->hv->present = false;
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cpu->soc = get_soc(cpu);
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cpu->peak_performance = get_peak_performance(cpu);
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return cpu;
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}
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#endif
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struct cpuInfo* get_cpu_info(void) {
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@@ -598,8 +438,6 @@ struct cpuInfo* get_cpu_info(void) {
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return get_cpu_info_linux(cpu);
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#elif defined __APPLE__ || __MACH__
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return get_cpu_info_mach(cpu);
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#elif defined _WIN32
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return get_cpu_info_windows(cpu);
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#endif
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}
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118
src/arm/soc.c
118
src/arm/soc.c
@@ -14,28 +14,6 @@
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#include "../common/sysctl.h"
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#endif
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#if defined(_WIN32)
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#define WIN32_LEAN_AND_MEAN
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#define NOMINMAX
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#include <windows.h>
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// Gets a RRF_RT_REG_SZ-entry from the Windows registry, returning a newly allocated
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// string and its length
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bool read_registry_hklm_sz(char* path, char* value, char** string, LPDWORD length) {
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// First call to RegGetValueA gets the length of the string and determines how much
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// memory should be allocated for the new string
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if(RegGetValueA(HKEY_LOCAL_MACHINE, path, value, RRF_RT_REG_SZ, NULL, NULL, length) != ERROR_SUCCESS) {
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return false;
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}
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*string = ecalloc(*length, sizeof(char));
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// Second call actually writes the string data
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if(RegGetValueA(HKEY_LOCAL_MACHINE, path, value, RRF_RT_REG_SZ, NULL, *string, length) != ERROR_SUCCESS) {
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return false;
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}
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return true;
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}
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#endif
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#define NA -1
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#define min(a,b) (((a)<(b))?(a):(b))
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#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
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@@ -306,21 +284,7 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
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soc->vendor = SOC_VENDOR_MEDIATEK;
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SOC_START
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// TODO
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// Dimensity 6000 Series //
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// Dimensity 7000 Series //
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// Dimensity 8000 Series //
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// END TODO
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// Dimensity 9000 Series //
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SOC_EQ(tmp, "MT6983Z", "Dimensity 9000", SOC_MTK_MT6983Z, soc, 4)
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SOC_EQ(tmp, "MT8798Z/C","Dimensity 9000", SOC_MTK_MT8798ZC, soc, 4)
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SOC_EQ(tmp, "MT6983W", "Dimensity 9000+", SOC_MTK_MT6983W, soc, 4)
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SOC_EQ(tmp, "MT8798Z/T","Dimensity 9000+", SOC_MTK_MT8798ZT, soc, 4)
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SOC_EQ(tmp, "MT6985W", "Dimensity 9200+", SOC_MTK_MT6985W, soc, 4)
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SOC_EQ(tmp, "MT6985", "Dimensity 9200", SOC_MTK_MT6985, soc, 4)
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SOC_EQ(tmp, "MT6989", "Dimensity 9300", SOC_MTK_MT6989, soc, 4)
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SOC_EQ(tmp, "MT8796", "Dimensity 9300", SOC_MTK_MT8796, soc, 4)
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// Dimensity 1000 //
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// Dimensity //
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SOC_EQ(tmp, "MT6893Z", "Dimensity 1300", SOC_MTK_MT6893Z, soc, 6)
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SOC_EQ(tmp, "MT6893", "Dimensity 1200", SOC_MTK_MT6893, soc, 6)
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SOC_EQ(tmp, "MT6891", "Dimensity 1100", SOC_MTK_MT6891, soc, 6)
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@@ -330,21 +294,12 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
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SOC_EQ(tmp, "MT6885Z", "Dimensity 1000L", SOC_MTK_MT6885Z, soc, 7)
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SOC_EQ(tmp, "MT6889Z", "Dimensity 1000+", SOC_MTK_MT6889Z, soc, 7)
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SOC_EQ(tmp, "MT6883Z", "Dimensity 1000C", SOC_MTK_MT6883Z, soc, 7)
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// Dimensity 900
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SOC_EQ(tmp, "MT6877V/Z","Dimensity 900", SOC_MTK_MT6877VZ, soc, 6)
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SOC_EQ(tmp, "MT6877T" ,"Dimensity 920", SOC_MTK_MT6877T, soc, 6)
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SOC_EQ(tmp, "MT6855" ,"Dimensity 930", SOC_MTK_MT6855, soc, 6)
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// Dimensity 800
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SOC_EQ(tmp, "MT6873", "Dimensity 800", SOC_MTK_MT6873, soc, 7)
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SOC_EQ(tmp, "MT6853V/T","Dimensity 800U", SOC_MTK_MT6853VT, soc, 7)
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SOC_EQ(tmp, "MT6853T", "Dimensity 800U", SOC_MTK_MT6853T, soc, 7)
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SOC_EQ(tmp, "MT6833P", "Dimensity 810", SOC_MTK_MT6833P, soc, 6)
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SOC_EQ(tmp, "MT6833GP", "Dimensity 810", SOC_MTK_MT6833GP, soc, 6)
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SOC_EQ(tmp, "MT6833V", "Dimensity 810", SOC_MTK_MT6833V, soc, 6)
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SOC_EQ(tmp, "MT6875", "Dimensity 820", SOC_MTK_MT6875, soc, 7)
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// Dimensity 700
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SOC_EQ(tmp, "MT6833", "Dimensity 700", SOC_MTK_MT6833, soc, 7)
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SOC_EQ(tmp, "MT6853V", "Dimensity 720", SOC_MTK_MT6853, soc, 7)
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SOC_EQ(tmp, "MT6853", "Dimensity 720", SOC_MTK_MT6853, soc, 7)
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SOC_EQ(tmp, "MT6873", "Dimensity 800", SOC_MTK_MT6873, soc, 7)
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SOC_EQ(tmp, "MT6853V", "Dimensity 800U", SOC_MTK_MT6853V, soc, 7)
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SOC_EQ(tmp, "MT6833", "Dimensity 810", SOC_MTK_MT6833, soc, 6)
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SOC_EQ(tmp, "MT6875", "Dimensity 820", SOC_MTK_MT6875, soc, 7)
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// Helio //
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SOC_EQ(tmp, "MT6761D", "Helio A20", SOC_MTK_MT6761D, soc, 12)
|
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SOC_EQ(tmp, "MT6761", "Helio A22", SOC_MTK_MT6761, soc, 12)
|
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@@ -1016,18 +971,6 @@ struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
|
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DT_EQ(dt, len, soc, "apple,t6030", "M3 Pro", SOC_APPLE_M3_PRO, 3)
|
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DT_EQ(dt, len, soc, "apple,t6031", "M3 Max", SOC_APPLE_M3_MAX, 3)
|
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DT_EQ(dt, len, soc, "apple,t6034", "M3 Max", SOC_APPLE_M3_MAX, 3)
|
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// NVIDIA
|
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// https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/nvidia
|
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// https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm/boot/dts/nvidia
|
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DT_EQ(dt, len, soc, "nvidia,tegra20", "Tegra 2", SOC_TEGRA_2, 40) // https://en.wikipedia.org/wiki/Tegra#Tegra_2
|
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DT_EQ(dt, len, soc, "nvidia,tegra30", "Tegra 3", SOC_TEGRA_3, 40) // https://en.wikipedia.org/wiki/Tegra#Tegra_3
|
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DT_EQ(dt, len, soc, "nvidia,tegra114", "Tegra 4", SOC_TEGRA_4, 28) // https://en.wikipedia.org/wiki/Tegra#Tegra_4
|
||||
DT_EQ(dt, len, soc, "nvidia,tegra124", "Tegra K1", SOC_TEGRA_K1, 28) // https://en.wikipedia.org/wiki/Tegra#Tegra_K1
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DT_EQ(dt, len, soc, "nvidia,tegra132", "Tegra K1", SOC_TEGRA_K1, 28) // https://en.wikipedia.org/wiki/Tegra#Tegra_K1
|
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DT_EQ(dt, len, soc, "nvidia,tegra210", "Tegra X1", SOC_TEGRA_X1, 20) // https://en.wikipedia.org/wiki/Tegra#Tegra_X1
|
||||
DT_EQ(dt, len, soc, "nvidia,tegra186", "Tegra X2", SOC_TEGRA_X2, 16) // https://en.wikipedia.org/wiki/Tegra#Tegra_X2
|
||||
DT_EQ(dt, len, soc, "nvidia,tegra194", "Tegra Xavier", SOC_TEGRA_XAVIER, 12) // https://en.wikipedia.org/wiki/Tegra#Xavier
|
||||
DT_EQ(dt, len, soc, "nvidia,tegra234", "Tegra Orin", SOC_TEGRA_ORIN, 8) // https://www.phoronix.com/news/NVIDIA-Orin-Tegra234-Audio, https://github.com/Dr-Noob/cpufetch/issues/275, https://en.wikipedia.org/wiki/Tegra#Orin
|
||||
// Qualcomm now also in devtree...
|
||||
// TODO: Integrate this with SOC_EQ
|
||||
DT_EQ(dt, len, soc, "qcom,sc8280", "8cx Gen 3", SOC_SNAPD_SC8280XP, 5)
|
||||
@@ -1041,29 +984,11 @@ struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
|
||||
DT_EQ(dt, len, soc, "fsl,imx8dxp", "i.MX 8DualXPlus", SOC_NXP_IMX8DXP, NA)
|
||||
DT_EQ(dt, len, soc, "fsl,imx8qxp", "i.MX 8QuadXPlus", SOC_NXP_IMX8QXP, NA)
|
||||
DT_EQ(dt, len, soc, "fsl,imx93", "i.MX 93", SOC_NXP_IMX93, NA)
|
||||
// [1] https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/amlogic
|
||||
// [2] https://github.com/Dr-Noob/cpufetch/issues/268
|
||||
// [3] https://www.amlogic.com/#Products/393/index.html
|
||||
// [4] https://wikimovel.com
|
||||
// [5] https://wiki.postmarketos.org/wiki/Amlogic_S905W/S905D/S905X/S905L/S805X/S805Y/S905Z
|
||||
DT_EQ(dt, len, soc, "amlogic,a311d", "A311D", SOC_AMLOGIC_A311D, 12) // [1,2,3,4]
|
||||
DT_EQ(dt, len, soc, "amlogic,a311d2", "A311D2", SOC_AMLOGIC_A311D2, 12) // [1,4]
|
||||
DT_EQ(dt, len, soc, "amlogic,s905w", "S905W", SOC_AMLOGIC_S905W, 28) // [1,5]
|
||||
DT_EQ(dt, len, soc, "amlogic,s905d", "S905D", SOC_AMLOGIC_S905D, 28) // [1,5]
|
||||
DT_EQ(dt, len, soc, "amlogic,s905x", "S905X", SOC_AMLOGIC_S905X, 28) // [1,4,5]
|
||||
DT_EQ(dt, len, soc, "amlogic,s805x", "S805X", SOC_AMLOGIC_S805X, 28) // [1,5]
|
||||
// Marvell
|
||||
// https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/marvell
|
||||
DT_EQ(dt, len, soc, "marvell,armada3700", "Armada 3700", SOC_MARVELL_A3700, 28) // http://wiki.espressobin.net/tiki-index.php?page=Armada+3700 (pdf), https://github.com/Dr-Noob/cpufetch/issues/279
|
||||
DT_EQ(dt, len, soc, "marvell,armada3710", "Armada 3710", SOC_MARVELL_A3710, 28) // https://gzhls.at/blob/ldb/2/7/4/2/6eacf9661c5a2d20c4d7cd3328ffba47bfd6.pdf
|
||||
DT_EQ(dt, len, soc, "marvell,armada3720", "Armada 3720", SOC_MARVELL_A3720, 28) // https://gzhls.at/blob/ldb/2/7/4/2/6eacf9661c5a2d20c4d7cd3328ffba47bfd6.pdf
|
||||
DT_EQ(dt, len, soc, "marvell,armada7200", "Armada 7200", SOC_MARVELL_A7200, 28) // Assuming same manufacturing process as 7400
|
||||
DT_EQ(dt, len, soc, "marvell,armada7400", "Armada 7400", SOC_MARVELL_A7400, 28) // https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-embedded-processors-armada-7040-product-brief-2017-12.pdf
|
||||
DT_EQ(dt, len, soc, "marvell,armada8020", "Armada 8020", SOC_MARVELL_A8020, 28) // https://datasheet.datasheetarchive.com/originals/crawler/marvell.com/da7b6a997e49e9e93fa4b1f4cfbed71b.pdf
|
||||
DT_EQ(dt, len, soc, "marvell,armada8040", "Armada 8040", SOC_MARVELL_A8040, 28) // https://www.verical.com/datasheet/marvell-technology-group-application-processors-and-soc-88f8040-a2-bvp4i160-6331367.pdf
|
||||
DT_EQ(dt, len, soc, "marvell,cn9130", "CN9130", SOC_MARVELL_CN9130, NA) // https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-infrastructure-processors-octeon-tx2-cn913x-product-brief.pdf
|
||||
DT_EQ(dt, len, soc, "marvell,cn9131", "CN9131", SOC_MARVELL_CN9131, NA) // https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-infrastructure-processors-octeon-tx2-cn913x-product-brief.pdf
|
||||
DT_EQ(dt, len, soc, "marvell,cn9132", "CN9132", SOC_MARVELL_CN9132, NA) // https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-infrastructure-processors-octeon-tx2-cn913x-product-brief.pdf
|
||||
// TODO: Add more Amlogic SoCs: https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/amlogic
|
||||
// https://github.com/Dr-Noob/cpufetch/issues/268
|
||||
// https://www.amlogic.com/#Products/393/index.html
|
||||
// https://wikimovel.com/index.php/Amlogic_A311D
|
||||
DT_EQ(dt, len, soc, "amlogic,a311d", "A311D", SOC_AMLOGIC_A311D, 12)
|
||||
DT_END(dt, len)
|
||||
}
|
||||
|
||||
@@ -1302,24 +1227,7 @@ struct system_on_chip* get_soc(struct cpuInfo* cpu) {
|
||||
else {
|
||||
return soc;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined _WIN32
|
||||
// Use the first core to determine the SoC
|
||||
char* processor_name_string = NULL;
|
||||
unsigned long processor_name_string_len = 0;
|
||||
if(!read_registry_hklm_sz("HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0", "ProcessorNameString", &processor_name_string, &processor_name_string_len)) {
|
||||
printWarn("Failed to aquire SoC name from registery");
|
||||
return soc;
|
||||
}
|
||||
|
||||
soc->name = processor_name_string;
|
||||
soc->raw_name = processor_name_string;
|
||||
soc->vendor = try_match_soc_vendor_name(processor_name_string);
|
||||
soc->model = SOC_MODEL_UNKNOWN;
|
||||
soc->process = UNKNOWN;
|
||||
|
||||
#else
|
||||
#endif // ifdef __linux__
|
||||
|
||||
if(soc->model == SOC_MODEL_UNKNOWN) {
|
||||
// raw_name might not be NULL, but if we were unable to find
|
||||
@@ -1328,7 +1236,5 @@ struct system_on_chip* get_soc(struct cpuInfo* cpu) {
|
||||
snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
return soc;
|
||||
}
|
||||
|
||||
@@ -192,22 +192,6 @@ enum {
|
||||
SOC_MTK_MT9950,
|
||||
SOC_MTK_MT9972,
|
||||
SOC_MTK_MT9982,
|
||||
SOC_MTK_MT6983Z,
|
||||
SOC_MTK_MT8798ZC,
|
||||
SOC_MTK_MT6983W,
|
||||
SOC_MTK_MT8798ZT,
|
||||
SOC_MTK_MT6985W,
|
||||
SOC_MTK_MT6985,
|
||||
SOC_MTK_MT6989,
|
||||
SOC_MTK_MT8796,
|
||||
SOC_MTK_MT6877VZ,
|
||||
SOC_MTK_MT6877T,
|
||||
SOC_MTK_MT6855,
|
||||
SOC_MTK_MT6853VT,
|
||||
SOC_MTK_MT6853T,
|
||||
SOC_MTK_MT6833P,
|
||||
SOC_MTK_MT6833GP,
|
||||
SOC_MTK_MT6833V,
|
||||
// Snapdragon //
|
||||
SOC_SNAPD_QSD8650,
|
||||
SOC_SNAPD_QSD8250,
|
||||
@@ -396,15 +380,7 @@ enum {
|
||||
SOC_GOOGLE_TENSOR_G2,
|
||||
SOC_GOOGLE_TENSOR_G3,
|
||||
// NVIDIA,
|
||||
SOC_TEGRA_2,
|
||||
SOC_TEGRA_3,
|
||||
SOC_TEGRA_4,
|
||||
SOC_TEGRA_K1,
|
||||
SOC_TEGRA_K2,
|
||||
SOC_TEGRA_X1,
|
||||
SOC_TEGRA_X2,
|
||||
SOC_TEGRA_XAVIER,
|
||||
SOC_TEGRA_ORIN,
|
||||
// ALTRA
|
||||
SOC_AMPERE_ALTRA,
|
||||
// NXP
|
||||
@@ -418,22 +394,6 @@ enum {
|
||||
SOC_NXP_IMX93,
|
||||
// AMLOGIC
|
||||
SOC_AMLOGIC_A311D,
|
||||
SOC_AMLOGIC_A311D2,
|
||||
SOC_AMLOGIC_S905W,
|
||||
SOC_AMLOGIC_S905D,
|
||||
SOC_AMLOGIC_S905X,
|
||||
SOC_AMLOGIC_S805X,
|
||||
// MARVELL
|
||||
SOC_MARVELL_A3700,
|
||||
SOC_MARVELL_A3710,
|
||||
SOC_MARVELL_A3720,
|
||||
SOC_MARVELL_A7200,
|
||||
SOC_MARVELL_A7400,
|
||||
SOC_MARVELL_A8020,
|
||||
SOC_MARVELL_A8040,
|
||||
SOC_MARVELL_CN9130,
|
||||
SOC_MARVELL_CN9131,
|
||||
SOC_MARVELL_CN9132,
|
||||
// UNKNOWN
|
||||
SOC_MODEL_UNKNOWN
|
||||
};
|
||||
@@ -443,17 +403,16 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
|
||||
else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_9000S) return SOC_VENDOR_KIRIN;
|
||||
else if(soc >= SOC_KUNPENG_920 && soc <= SOC_KUNPENG_930) return SOC_VENDOR_KUNPENG;
|
||||
else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
|
||||
else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8796) return SOC_VENDOR_MEDIATEK;
|
||||
else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
|
||||
else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SC8280XP) return SOC_VENDOR_SNAPDRAGON;
|
||||
else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE;
|
||||
else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
|
||||
else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP;
|
||||
else if(soc >= SOC_GOOGLE_TENSOR && soc <= SOC_GOOGLE_TENSOR_G3) return SOC_VENDOR_GOOGLE;
|
||||
else if(soc >= SOC_TEGRA_2 && soc <= SOC_TEGRA_ORIN) return SOC_VENDOR_NVIDIA;
|
||||
else if(soc >= SOC_TEGRA_X1 && soc <= SOC_TEGRA_X1) return SOC_VENDOR_NVIDIA;
|
||||
else if(soc >= SOC_AMPERE_ALTRA && soc <= SOC_AMPERE_ALTRA) return SOC_VENDOR_AMPERE;
|
||||
else if(soc >= SOC_NXP_IMX8QM && soc <= SOC_NXP_IMX93) return SOC_VENDOR_NXP;
|
||||
else if(soc >= SOC_AMLOGIC_A311D && soc <= SOC_AMLOGIC_S805X) return SOC_VENDOR_AMLOGIC;
|
||||
else if(soc >= SOC_MARVELL_A3700 && soc <= SOC_MARVELL_CN9132) return SOC_VENDOR_MARVELL;
|
||||
else if(soc >= SOC_AMLOGIC_A311D && soc <= SOC_AMLOGIC_A311D) return SOC_VENDOR_AMLOGIC;
|
||||
return SOC_VENDOR_UNKNOWN;
|
||||
}
|
||||
|
||||
|
||||
@@ -433,18 +433,6 @@ $C1#########.### ## ## ## ## ### ###### ## ### \
|
||||
$C1 ### \
|
||||
$C1 ### "
|
||||
|
||||
#define ASCII_MARVELL \
|
||||
"$C1 ........... ........... \
|
||||
$C1 .### . .## . \
|
||||
$C1 .##### . #### . \
|
||||
$C1 ####### . ####### . \
|
||||
$C1 .#########__________. #########__________. \
|
||||
$C1 .###########|__________|#########|__________| \
|
||||
$C1 ############ ______############ __________ \
|
||||
$C1 .######### |__________|###### |__________| \
|
||||
$C1 ########### ___########### __________ \
|
||||
$C1.########## |__________| |__________| "
|
||||
|
||||
// --------------------- LONG LOGOS ------------------------- //
|
||||
#define ASCII_AMD_L \
|
||||
"$C1 \
|
||||
@@ -623,7 +611,6 @@ asciiL logo_nvidia = { ASCII_NVIDIA, 45, 19, false, {C_FG_GREEN, C_FG_
|
||||
asciiL logo_ampere = { ASCII_AMPERE, 50, 17, false, {C_FG_RED}, {C_FG_WHITE, C_FG_RED} };
|
||||
asciiL logo_nxp = { ASCII_NXP, 55, 8, false, {C_FG_YELLOW, C_FG_CYAN, C_FG_GREEN}, {C_FG_CYAN, C_FG_WHITE} };
|
||||
asciiL logo_amlogic = { ASCII_AMLOGIC, 58, 8, false, {C_FG_BLUE}, {C_FG_BLUE, C_FG_B_WHITE} };
|
||||
asciiL logo_marvell = { ASCII_MARVELL, 56, 10, false, {C_FG_B_BLACK}, {C_FG_B_BLACK, C_FG_B_WHITE} };
|
||||
|
||||
// Long variants | ----------------------------------------------------------------------------------------------------------------|
|
||||
asciiL logo_amd_l = { ASCII_AMD_L, 62, 19, true, {C_BG_WHITE, C_BG_GREEN}, {C_FG_WHITE, C_FG_GREEN} };
|
||||
|
||||
@@ -34,12 +34,6 @@ int64_t get_freq(struct frequency* freq) {
|
||||
return freq->max;
|
||||
}
|
||||
|
||||
#ifdef ARCH_X86
|
||||
int64_t get_freq_pp(struct frequency* freq) {
|
||||
return freq->max_pp;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(ARCH_X86) || defined(ARCH_PPC)
|
||||
char* get_str_cpu_name(struct cpuInfo* cpu, bool fcpuname) {
|
||||
#ifdef ARCH_X86
|
||||
|
||||
@@ -60,11 +60,6 @@ struct frequency {
|
||||
int32_t max;
|
||||
// Indicates if max frequency was measured
|
||||
bool measured;
|
||||
#ifdef ARCH_X86
|
||||
// Max frequency when running vectorized code.
|
||||
// Used only for peak performance computation.
|
||||
int32_t max_pp;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct hypervisor {
|
||||
@@ -193,8 +188,6 @@ struct cpuInfo {
|
||||
#ifdef ARCH_X86
|
||||
// The index of the first core in the module
|
||||
uint32_t first_core_id;
|
||||
// The index of this module
|
||||
uint32_t module_id;
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
@@ -207,9 +200,6 @@ uint32_t get_nsockets(struct topology* topo);
|
||||
|
||||
VENDOR get_cpu_vendor(struct cpuInfo* cpu);
|
||||
int64_t get_freq(struct frequency* freq);
|
||||
#ifdef ARCH_X86
|
||||
int64_t get_freq_pp(struct frequency* freq);
|
||||
#endif
|
||||
|
||||
char* get_str_aes(struct cpuInfo* cpu);
|
||||
char* get_str_sha(struct cpuInfo* cpu);
|
||||
|
||||
@@ -395,8 +395,6 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
|
||||
art->art = &logo_nxp;
|
||||
else if(art->vendor == SOC_VENDOR_AMLOGIC)
|
||||
art->art = &logo_amlogic;
|
||||
else if(art->vendor == SOC_VENDOR_MARVELL)
|
||||
art->art = &logo_marvell;
|
||||
else if(art->vendor == SOC_VENDOR_NVIDIA)
|
||||
art->art = choose_ascii_art_aux(&logo_nvidia_l, &logo_nvidia, term, lf);
|
||||
else {
|
||||
@@ -887,13 +885,7 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
|
||||
char* soc_name = get_soc_name(cpu->soc);
|
||||
char* features = get_str_features(cpu);
|
||||
setAttribute(art, ATTRIBUTE_SOC, soc_name);
|
||||
|
||||
// Currently no reliable way to identify the specific SoC on Windows
|
||||
// https://github.com/Dr-Noob/cpufetch/pull/273
|
||||
// Hide manufacturing process
|
||||
#if !defined(_WIN32)
|
||||
setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
|
||||
#endif
|
||||
|
||||
if(cpu->num_cpus == 1) {
|
||||
char* uarch = get_str_uarch(cpu);
|
||||
|
||||
@@ -24,7 +24,6 @@ static char* soc_trademark_string[] = {
|
||||
[SOC_VENDOR_AMPERE] = "Ampere ",
|
||||
[SOC_VENDOR_NXP] = "NXP ",
|
||||
[SOC_VENDOR_AMLOGIC] = "Amlogic ",
|
||||
[SOC_VENDOR_MARVELL] = "Marvell",
|
||||
// RISC-V
|
||||
[SOC_VENDOR_SIFIVE] = "SiFive ",
|
||||
[SOC_VENDOR_STARFIVE] = "StarFive ",
|
||||
@@ -79,18 +78,6 @@ void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef _WIN32
|
||||
VENDOR try_match_soc_vendor_name(char* vendor_name)
|
||||
{
|
||||
for(size_t i=1; i < sizeof(soc_trademark_string)/sizeof(soc_trademark_string[0]); i++) {
|
||||
if(strstr(vendor_name, soc_trademark_string[i]) != NULL) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return SOC_VENDOR_UNKNOWN;
|
||||
}
|
||||
#endif
|
||||
|
||||
bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
|
||||
int len1 = strlen(raw_name);
|
||||
int len2 = strlen(expected_name);
|
||||
|
||||
@@ -28,7 +28,6 @@ enum {
|
||||
SOC_VENDOR_AMPERE,
|
||||
SOC_VENDOR_NXP,
|
||||
SOC_VENDOR_AMLOGIC,
|
||||
SOC_VENDOR_MARVELL,
|
||||
// RISC-V
|
||||
SOC_VENDOR_SIFIVE,
|
||||
SOC_VENDOR_STARFIVE,
|
||||
@@ -51,9 +50,6 @@ VENDOR get_soc_vendor(struct system_on_chip* soc);
|
||||
bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process);
|
||||
char* get_str_process(struct system_on_chip* soc);
|
||||
void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process);
|
||||
#ifdef _WIN32
|
||||
VENDOR try_match_soc_vendor_name(char* vendor_name);
|
||||
#endif
|
||||
|
||||
#define SOC_START if (false) {}
|
||||
#define SOC_EQ(raw_name, expected_name, soc_name, soc_model, soc, process) \
|
||||
|
||||
@@ -62,7 +62,6 @@ int parse_multi_letter_extension(struct extensions* ext, char* e) {
|
||||
SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM)
|
||||
SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE)
|
||||
SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT)
|
||||
SET_ISA_EXT_MAP("zicbop", RISCV_ISA_EXT_ZICBOP)
|
||||
SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ)
|
||||
SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA)
|
||||
SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA)
|
||||
|
||||
@@ -23,7 +23,6 @@ enum riscv_isa_ext_id {
|
||||
RISCV_ISA_EXT_ZICBOM,
|
||||
RISCV_ISA_EXT_ZIHINTPAUSE,
|
||||
RISCV_ISA_EXT_SVNAPOT,
|
||||
RISCV_ISA_EXT_ZICBOP,
|
||||
RISCV_ISA_EXT_ZICBOZ,
|
||||
RISCV_ISA_EXT_SMAIA,
|
||||
RISCV_ISA_EXT_SSAIA,
|
||||
@@ -38,7 +37,6 @@ enum riscv_isa_ext_id {
|
||||
|
||||
// https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface
|
||||
// https://en.wikichip.org/wiki/risc-v/standard_extensions
|
||||
// (Zicbop) https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicbop.adoc
|
||||
// Included all except for G
|
||||
static const struct extension extension_list[] = {
|
||||
{ 'i' - 'a', "(I) Integer Instruction Set" },
|
||||
@@ -66,7 +64,6 @@ static const struct extension extension_list[] = {
|
||||
{ RISCV_ISA_EXT_ZIHINTPAUSE, "(Zihintpause) Pause Hint" },
|
||||
{ RISCV_ISA_EXT_SVNAPOT, "(Svnapot) Naturally Aligned Power of Two Pages" },
|
||||
{ RISCV_ISA_EXT_ZICBOZ, "(Zicboz) Cache Block Zero Operations" },
|
||||
{ RISCV_ISA_EXT_ZICBOP, "(Zicbop) Cache Block Prefetch Operations" },
|
||||
{ RISCV_ISA_EXT_SMAIA, "(Smaia) Advanced Interrupt Architecture" },
|
||||
{ RISCV_ISA_EXT_SSAIA, "(Ssaia) Advanced Interrupt Architecture" },
|
||||
{ RISCV_ISA_EXT_ZBA, "(Zba) Address Generation" },
|
||||
|
||||
@@ -210,14 +210,18 @@ int64_t get_peak_performance(struct cpuInfo* cpu, bool accurate_pp) {
|
||||
|
||||
for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
|
||||
struct topology* topo = ptr->topo;
|
||||
int64_t freq = get_freq(ptr->freq);
|
||||
int64_t max_freq = get_freq(ptr->freq);
|
||||
|
||||
int64_t freq;
|
||||
#ifdef __linux__
|
||||
if(accurate_pp)
|
||||
freq = get_freq_pp(ptr->freq);
|
||||
freq = measure_frequency(ptr);
|
||||
else
|
||||
freq = max_freq;
|
||||
#else
|
||||
// Silence compiler warning
|
||||
(void)(accurate_pp);
|
||||
freq = max_freq;
|
||||
#endif
|
||||
|
||||
//First, check we have consistent data
|
||||
@@ -446,23 +450,6 @@ int32_t get_core_type(void) {
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __linux__
|
||||
// Gets the max frequency for estimating the peak performance,
|
||||
// filling in the passed cpuInfo parameter with this information.
|
||||
void fill_frequency_info_pp(struct cpuInfo* cpu) {
|
||||
int32_t unused;
|
||||
int32_t *max_freq_pp_vec = malloc(sizeof(int32_t) * cpu->num_cpus);
|
||||
struct cpuInfo* ptr = cpu;
|
||||
|
||||
for (uint32_t i=0; i < cpu->num_cpus; i++) {
|
||||
set_cpu_module(i, cpu->num_cpus, &unused);
|
||||
|
||||
ptr->freq->max_pp = measure_frequency(ptr, max_freq_pp_vec);
|
||||
ptr = ptr->next_cpu;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
struct cpuInfo* get_cpu_info(void) {
|
||||
struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
|
||||
cpu->peak_performance = -1;
|
||||
@@ -559,7 +546,6 @@ struct cpuInfo* get_cpu_info(void) {
|
||||
ptr->core_type = get_core_type();
|
||||
}
|
||||
ptr->first_core_id = first_core;
|
||||
ptr->module_id = i;
|
||||
ptr->feat = get_features_info(ptr);
|
||||
|
||||
ptr->arch = get_cpu_uarch(ptr);
|
||||
@@ -584,13 +570,6 @@ struct cpuInfo* get_cpu_info(void) {
|
||||
if(ptr->topo == NULL) return cpu;
|
||||
}
|
||||
|
||||
#ifdef __linux__
|
||||
// If accurate_pp is requested, we need to get the max frequency
|
||||
// after fetching the topology for all CPU modules, since the topology
|
||||
// is required by fill_frequency_info_pp
|
||||
if (accurate_pp()) fill_frequency_info_pp(cpu);
|
||||
#endif
|
||||
|
||||
cpu->peak_performance = get_peak_performance(cpu, accurate_pp());
|
||||
|
||||
return cpu;
|
||||
@@ -1026,7 +1005,6 @@ struct frequency* get_frequency_info(struct cpuInfo* cpu) {
|
||||
}
|
||||
#endif
|
||||
|
||||
freq->max_pp = UNKNOWN_DATA;
|
||||
return freq;
|
||||
}
|
||||
|
||||
|
||||
@@ -21,12 +21,9 @@
|
||||
#define FREQ_VECTOR_SIZE 1<<16
|
||||
|
||||
struct freq_thread {
|
||||
// Inputs
|
||||
struct cpuInfo* cpu;
|
||||
bool end;
|
||||
bool measure;
|
||||
// Output
|
||||
int32_t *max_pp;
|
||||
double freq;
|
||||
};
|
||||
|
||||
double vector_average_harmonic(double* v, int len) {
|
||||
@@ -51,7 +48,6 @@ void* measure_freq(void *freq_ptr) {
|
||||
char* line = NULL;
|
||||
size_t len = 0;
|
||||
ssize_t read;
|
||||
struct cpuInfo* cpu = freq->cpu;
|
||||
|
||||
int v = 0;
|
||||
double* freq_vector = malloc(sizeof(double) * FREQ_VECTOR_SIZE);
|
||||
@@ -80,43 +76,18 @@ void* measure_freq(void *freq_ptr) {
|
||||
sleep_ms(500);
|
||||
}
|
||||
|
||||
if (cpu->hybrid_flag) {
|
||||
// We have an heterogeneous architecture. After measuring the
|
||||
// frequency for all cores, we now need to compute the average
|
||||
// independently for each CPU module.
|
||||
struct cpuInfo* ptr = cpu;
|
||||
double* freq_vector_ptr = freq_vector;
|
||||
|
||||
for (int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
|
||||
freq->max_pp[i] = vector_average_harmonic(freq_vector_ptr, ptr->topo->total_cores_module);
|
||||
printWarn("AVX2 measured freq=%d (module %d)", freq->max_pp[i], i);
|
||||
|
||||
freq_vector_ptr = freq_vector_ptr + ptr->topo->total_cores_module;
|
||||
}
|
||||
}
|
||||
else {
|
||||
freq->max_pp[0] = vector_average_harmonic(freq_vector, v);
|
||||
printWarn("AVX2 measured freq=%d\n", freq->max_pp[0]);
|
||||
}
|
||||
freq->freq = vector_average_harmonic(freq_vector, v);
|
||||
printWarn("AVX2 measured freq=%f\n", freq->freq);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int32_t measure_frequency(struct cpuInfo* cpu, int32_t *max_freq_pp_vec) {
|
||||
if (cpu->hybrid_flag && cpu->module_id > 0) {
|
||||
// We have a hybrid architecture and we have already
|
||||
// measured the frequency for this module in a previous
|
||||
// call to this function, so now just return it.
|
||||
return max_freq_pp_vec[cpu->module_id];
|
||||
}
|
||||
|
||||
int64_t measure_frequency(struct cpuInfo* cpu) {
|
||||
int ret;
|
||||
int num_spaces;
|
||||
struct freq_thread* freq_struct = malloc(sizeof(struct freq_thread));
|
||||
freq_struct->end = false;
|
||||
freq_struct->measure = false;
|
||||
freq_struct->cpu = cpu;
|
||||
freq_struct->max_pp = max_freq_pp_vec;
|
||||
|
||||
void* (*compute_function)(void*);
|
||||
|
||||
@@ -188,5 +159,5 @@ int32_t measure_frequency(struct cpuInfo* cpu, int32_t *max_freq_pp_vec) {
|
||||
}
|
||||
|
||||
printf("\r%*c", num_spaces, ' ');
|
||||
return max_freq_pp_vec[0];
|
||||
return freq_struct->freq;
|
||||
}
|
||||
|
||||
@@ -8,6 +8,6 @@
|
||||
#define MEASURE_TIME_SECONDS 5
|
||||
#define LOOP_ITERS 100000000
|
||||
|
||||
int32_t measure_frequency(struct cpuInfo* cpu, int32_t *max_freq_pp_vec);
|
||||
int64_t measure_frequency(struct cpuInfo* cpu);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -93,7 +93,6 @@ enum {
|
||||
UARCH_CEDAR_MILL,
|
||||
UARCH_ITANIUM2,
|
||||
UARCH_ICE_LAKE,
|
||||
UARCH_SAPPHIRE_RAPIDS,
|
||||
UARCH_TIGER_LAKE,
|
||||
UARCH_ALDER_LAKE,
|
||||
UARCH_RAPTOR_LAKE,
|
||||
@@ -120,9 +119,7 @@ enum {
|
||||
UARCH_ZEN3,
|
||||
UARCH_ZEN3_PLUS,
|
||||
UARCH_ZEN4,
|
||||
UARCH_ZEN4C,
|
||||
UARCH_ZEN5,
|
||||
UARCH_ZEN5C,
|
||||
UARCH_ZEN4C
|
||||
};
|
||||
|
||||
struct uarch {
|
||||
@@ -256,7 +253,6 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
|
||||
// CHECK_UARCH(arch, 0, 6, 8, 14, 10, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake R or Coffee Lake U)
|
||||
CHECK_UARCH(arch, 0, 6, 8, 14, 11, "Whiskey Lake", UARCH_WHISKEY_LAKE, 14) // wikichip
|
||||
CHECK_UARCH(arch, 0, 6, 8, 14, 12, "Comet Lake", UARCH_COMET_LAKE, 14) // wikichip
|
||||
CHECK_UARCH(arch, 0, 6, 8, 15, 8, "Sapphire Rapids", UARCH_SAPPHIRE_RAPIDS, 7) // wikichip
|
||||
CHECK_UARCH(arch, 0, 6, 9, 6, NA, "Tremont", UARCH_TREMONT, 10) // LX*
|
||||
CHECK_UARCH(arch, 0, 6, 9, 7, NA, "Alder Lake", UARCH_ALDER_LAKE, 10) // instlatx64 (Alder Lake-S)
|
||||
CHECK_UARCH(arch, 0, 6, 9, 10, NA, "Alder Lake", UARCH_ALDER_LAKE, 10) // instlatx64 (Alder Lake-P)
|
||||
@@ -414,12 +410,6 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
|
||||
CHECK_UARCH(arch, 10, 15, 8, NA, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64 (AMD MI300C)
|
||||
CHECK_UARCH(arch, 10, 15, 9, NA, NA, "Zen 4", UARCH_ZEN4, 5) // instlatx64 (AMD MI300A)
|
||||
CHECK_UARCH(arch, 10, 15, 10, NA, NA, "Zen 4c", UARCH_ZEN4C, 5) // instlatx64
|
||||
CHECK_UARCH(arch, 11, 15, 0, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Turin/EPYC (instlatx64)
|
||||
CHECK_UARCH(arch, 11, 15, 1, NA, NA, "Zen 5c", UARCH_ZEN5C, 3) // Zen5c EPYC (instlatx64, https://en.wikipedia.org/wiki/Zen_5#cite_note-10)
|
||||
CHECK_UARCH(arch, 11, 15, 2, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Strix Point (instlatx64)
|
||||
CHECK_UARCH(arch, 11, 15, 4, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Granite Ridge (instlatx64)
|
||||
CHECK_UARCH(arch, 11, 15, 6, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Krackan Point (instlatx64)
|
||||
CHECK_UARCH(arch, 11, 15, 7, NA, NA, "Zen 5", UARCH_ZEN5, 4) // Strix Halo (instlatx64)
|
||||
UARCH_END
|
||||
|
||||
return arch;
|
||||
@@ -562,8 +552,6 @@ char* infer_cpu_name_from_uarch(struct uarch* arch) {
|
||||
}
|
||||
|
||||
bool vpus_are_AVX512(struct cpuInfo* cpu) {
|
||||
// Zen5 actually has 2 x AVX512 units
|
||||
// https://www.anandtech.com/show/21469/amd-details-ryzen-ai-300-series-for-mobile-strix-point-with-rdna-35-igpu-xdna-2-npu
|
||||
return cpu->arch->uarch != UARCH_ICE_LAKE &&
|
||||
cpu->arch->uarch != UARCH_TIGER_LAKE &&
|
||||
cpu->arch->uarch != UARCH_ZEN4 &&
|
||||
@@ -593,7 +581,6 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
|
||||
case UARCH_KNIGHTS_LANDING:
|
||||
case UARCH_KNIGHTS_MILL:
|
||||
|
||||
case UARCH_SAPPHIRE_RAPIDS:
|
||||
case UARCH_ICE_LAKE:
|
||||
case UARCH_TIGER_LAKE:
|
||||
case UARCH_ALDER_LAKE:
|
||||
@@ -605,8 +592,6 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
|
||||
case UARCH_ZEN3_PLUS:
|
||||
case UARCH_ZEN4:
|
||||
case UARCH_ZEN4C:
|
||||
case UARCH_ZEN5:
|
||||
case UARCH_ZEN5C:
|
||||
return 2;
|
||||
default:
|
||||
return 1;
|
||||
|
||||
Reference in New Issue
Block a user