[v1.04][X86] Fix incorrect free in AMD CPUs

src/arm/midr.c

@@ -289,7 +289,7 @@ void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint
   bli->feat = get_features_info();
   bli->topo = malloc(sizeof(struct topology));
   bli->topo->cach = bli->cach;
-  bli->topo->total_cores = ecores;
+  bli->topo->total_cores = pcores;
   bli->freq = malloc(sizeof(struct frequency));
   bli->freq->base = UNKNOWN_DATA;
   bli->freq->max = 2800;
@@ -305,7 +305,7 @@ void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint
   ava->feat = get_features_info();
   ava->topo = malloc(sizeof(struct topology));
   ava->topo->cach = ava->cach;
-  ava->topo->total_cores = pcores;
+  ava->topo->total_cores = ecores;
   ava->freq = malloc(sizeof(struct frequency));
   ava->freq->base = UNKNOWN_DATA;
   ava->freq->max = 3500;
@@ -314,78 +314,70 @@ void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint
   ava->next_cpu = NULL;
 }
 
-void fill_cpu_info_everest_sawtooth(struct cpuInfo* cpu, uint32_t pcores, uint32_t ecores) {
-  // 1. Fill SAWTOOTH
-  struct cpuInfo* saw = cpu;
-
-  saw->midr = MIDR_APPLE_M3_SAWTOOTH;
-  saw->arch = get_uarch_from_midr(saw->midr, saw);
-  saw->cach = get_cache_info(saw);
-  saw->feat = get_features_info();
-  saw->topo = malloc(sizeof(struct topology));
-  saw->topo->cach = saw->cach;
-  saw->topo->total_cores = ecores;
-  saw->freq = malloc(sizeof(struct frequency));
-  saw->freq->base = UNKNOWN_DATA;
-  saw->freq->max = 2750;
-  saw->hv = malloc(sizeof(struct hypervisor));
-  saw->hv->present = false;
-  saw->next_cpu = malloc(sizeof(struct cpuInfo));
-
-  // 2. Fill EVEREST
-  struct cpuInfo* eve = saw->next_cpu;
-  eve->midr = MIDR_APPLE_M3_EVEREST;
-  eve->arch = get_uarch_from_midr(eve->midr, eve);
-  eve->cach = get_cache_info(eve);
-  eve->feat = get_features_info();
-  eve->topo = malloc(sizeof(struct topology));
-  eve->topo->cach = eve->cach;
-  eve->topo->total_cores = pcores;
-  eve->freq = malloc(sizeof(struct frequency));
-  eve->freq->base = UNKNOWN_DATA;
-  eve->freq->max = 4050;
-  eve->hv = malloc(sizeof(struct hypervisor));
-  eve->hv->present = false;
-  eve->next_cpu = NULL;
-}
-
 struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
-  // https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_system_capabilities
-  uint32_t nperflevels = get_sys_info_by_name("hw.nperflevels");
-
-  if((cpu->num_cpus = nperflevels) != 2) {
-    printBug("Expected to find SoC with 2 perf levels, found: %d", cpu->num_cpus);
-    return NULL;
-  }
-
-  uint32_t pcores = get_sys_info_by_name("hw.perflevel0.physicalcpu");
-  uint32_t ecores = get_sys_info_by_name("hw.perflevel1.physicalcpu");
-  if(ecores <= 0) {
-    printBug("Expected to find a numer of ecores > 0, found: %d", ecores);
-    return NULL;
-  }
-  if(pcores <= 0) {
-    printBug("Expected to find a numer of pcores > 0, found: %d", pcores);
-    return NULL;
-  }
-
   uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
+
   // Manually fill the cpuInfo assuming that
-  // the CPU is an Apple SoC
+  // the CPU is an Apple M1/M2
   if(cpu_family == CPUFAMILY_ARM_FIRESTORM_ICESTORM) {
-    fill_cpu_info_firestorm_icestorm(cpu, pcores, ecores);
+    cpu->num_cpus = 2;
+    // Now detect the M1 version
+    uint32_t cpu_subfamily = get_sys_info_by_name("hw.cpusubfamily");
+    if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
+      // Apple M1
+      fill_cpu_info_firestorm_icestorm(cpu, 4, 4);
+    }
+    else if(cpu_subfamily == CPUSUBFAMILY_ARM_HS || cpu_subfamily == CPUSUBFAMILY_ARM_HC_HD) {
+      // Apple M1 Pro/Max/Ultra. Detect number of cores
+      uint32_t physicalcpu = get_sys_info_by_name("hw.physicalcpu");
+      if(physicalcpu == 20) {
+        // M1 Ultra
+        fill_cpu_info_firestorm_icestorm(cpu, 16, 4);
+      }
+      else if(physicalcpu == 8 || physicalcpu == 10) {
+        // M1 Pro/Max
+        fill_cpu_info_firestorm_icestorm(cpu, physicalcpu-2, 2);
+      }
+      else {
+        printBug("Found invalid physical cpu number: %d", physicalcpu);
+        return NULL;
+      }
+    }
+    else {
+      printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
+      return NULL;
+    }
     cpu->soc = get_soc();
     cpu->peak_performance = get_peak_performance(cpu);
   }
   else if(cpu_family == CPUFAMILY_ARM_AVALANCHE_BLIZZARD) {
-    fill_cpu_info_avalanche_blizzard(cpu, pcores, ecores);
+    cpu->num_cpus = 2;
-    cpu->soc = get_soc();
+    // Now detect the M2 version
-    cpu->peak_performance = get_peak_performance(cpu);
+    uint32_t cpu_subfamily = get_sys_info_by_name("hw.cpusubfamily");
-  }
+    if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
-  else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
+      // Apple M2
-          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
+      fill_cpu_info_avalanche_blizzard(cpu, 4, 4);
-          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
+    }
-    fill_cpu_info_everest_sawtooth(cpu, pcores, ecores);
+    else if(cpu_subfamily == CPUSUBFAMILY_ARM_HS) {
+      // Apple M2 Pro/Max/Ultra. Detect number of cores
+      uint32_t physicalcpu = get_sys_info_by_name("hw.physicalcpu");
+      if(physicalcpu == 24) {
+        // M2 Ultra
+        fill_cpu_info_avalanche_blizzard(cpu, 16, 8);
+      }
+      else if(physicalcpu == 10 || physicalcpu == 12) {
+        // M2 Pro/Max
+        fill_cpu_info_avalanche_blizzard(cpu, physicalcpu-4, 4);
+      }
+      else {
+        printBug("Found invalid physical cpu number: %d", physicalcpu);
+        return NULL;
+      }
+    }
+    else {
+      printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
+      return NULL;
+    }
     cpu->soc = get_soc();
     cpu->peak_performance = get_peak_performance(cpu);
   }
@@ -475,12 +467,6 @@ void print_debug(struct cpuInfo* cpu) {
       printf("%ld MHz\n", freq);
     }
   }
-
-  #if defined(__APPLE__) || defined(__MACH__)
-    printf("hw.cpufamily: 0x%.8X\n", get_sys_info_by_name("hw.cpufamily"));
-    printf("hw.cpusubfamily: 0x%.8X\n", get_sys_info_by_name("hw.cpusubfamily"));
-    printf("hw.physicalcpu: %d\n", get_sys_info_by_name("hw.physicalcpu"));
-  #endif
 }
 
 void free_topo_struct(struct topology* topo) {

src/arm/soc.c

@@ -734,7 +734,6 @@ bool get_rk_soc_from_efuse(struct system_on_chip* soc, char* efuse) {
   rkToSoC socFromRK[] = {
     // TODO: Add RK2XXX
     // RK3XXX
-    // Reverse order
     {0x2388, {SOC_ROCKCHIP_3288,  SOC_VENDOR_ROCKCHIP, 28, "RK3288",  NULL} },
     {0x2392, {SOC_ROCKCHIP_3229,  SOC_VENDOR_ROCKCHIP, 28, "RK3229",  NULL} }, // https://gadgetversus.com/processor/rockchip-rk3229-vs-rockchip-rk3128/
     {0x3380, {SOC_ROCKCHIP_3308,  SOC_VENDOR_ROCKCHIP, 28, "RK3308",  NULL} }, // https://en.t-firefly.com/product/rocrk3308cc?theme=pc
@@ -743,12 +742,10 @@ bool get_rk_soc_from_efuse(struct system_on_chip* soc, char* efuse) {
     {0x3382, {SOC_ROCKCHIP_3328,  SOC_VENDOR_ROCKCHIP, 28, "RK3328",  NULL} },
     {0x3386, {SOC_ROCKCHIP_3368,  SOC_VENDOR_ROCKCHIP, 28, "RK3368",  NULL} },
     {0x3399, {SOC_ROCKCHIP_3399,  SOC_VENDOR_ROCKCHIP, 28, "RK3399",  NULL} },
-    // Normal Order (https://github.com/Dr-Noob/cpufetch/issues/209)
+    {0x5366, {SOC_ROCKCHIP_3566,  SOC_VENDOR_ROCKCHIP, 22, "RK3566",  NULL} },
-    {0x3528, {SOC_ROCKCHIP_3528,  SOC_VENDOR_ROCKCHIP, 28, "RK3528",  NULL} },
+    {0x5386, {SOC_ROCKCHIP_3568,  SOC_VENDOR_ROCKCHIP, 22, "RK3568",  NULL} },
-    {0x3562, {SOC_ROCKCHIP_3562,  SOC_VENDOR_ROCKCHIP, 22, "RK3562",  NULL} },
+    {0x5388, {SOC_ROCKCHIP_3588,  SOC_VENDOR_ROCKCHIP,  8, "RK3588",  NULL} },
-    {0x3566, {SOC_ROCKCHIP_3566,  SOC_VENDOR_ROCKCHIP, 22, "RK3566",  NULL} },
+    {0x3588, {SOC_ROCKCHIP_3588S, SOC_VENDOR_ROCKCHIP,  8, "RK3588S", NULL} }, // https://github.com/Dr-Noob/cpufetch/issues/188
-    {0x3568, {SOC_ROCKCHIP_3568,  SOC_VENDOR_ROCKCHIP, 22, "RK3568",  NULL} },
-    {0x3588, {SOC_ROCKCHIP_3588,  SOC_VENDOR_ROCKCHIP,  8, "RK3588",  NULL} }, // No known way to distingish between S version: https://github.com/Dr-Noob/cpufetch/issues/188,209
     // Unknown
     {0x0000, {UNKNOWN,            SOC_VENDOR_UNKNOWN,   -1,       "", NULL} }
   };
@@ -889,24 +886,6 @@ struct system_on_chip* guess_soc_apple(struct system_on_chip* soc) {
       soc->soc_vendor = SOC_VENDOR_UNKNOWN;
     }
   }
-  else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
-          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
-          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
-    // Check M3 version
-    if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH) {
-      fill_soc(soc, "M3", SOC_APPLE_M3, 3);
-    }
-    else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO) {
-      fill_soc(soc, "M3 Pro", SOC_APPLE_M3_PRO, 3);
-    }
-    else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
-      fill_soc(soc, "M3 Max", SOC_APPLE_M3_MAX, 3);
-    }
-    else {
-      printBug("Found invalid cpu_family: 0x%.8X", cpu_family);
-      soc->soc_vendor = SOC_VENDOR_UNKNOWN;
-    }
-  }
   else {
     printBug("Found invalid cpu_family: 0x%.8X", cpu_family);
     soc->soc_vendor = SOC_VENDOR_UNKNOWN;

src/arm/socs.h

@@ -309,9 +309,6 @@ enum {
   SOC_APPLE_M2_PRO,
   SOC_APPLE_M2_MAX,
   SOC_APPLE_M2_ULTRA,
-  SOC_APPLE_M3,
-  SOC_APPLE_M3_PRO,
-  SOC_APPLE_M3_MAX,
   // ALLWINNER
   SOC_ALLWINNER_A10,
   SOC_ALLWINNER_A13,
@@ -349,11 +346,10 @@ enum {
   SOC_ROCKCHIP_3328,
   SOC_ROCKCHIP_3368,
   SOC_ROCKCHIP_3399,
-  SOC_ROCKCHIP_3528,
-  SOC_ROCKCHIP_3562,
   SOC_ROCKCHIP_3566,
   SOC_ROCKCHIP_3568,
   SOC_ROCKCHIP_3588,
+  SOC_ROCKCHIP_3588S,
   // GOOGLE
   SOC_GOOGLE_TENSOR,
   SOC_GOOGLE_TENSOR_G2,
@@ -368,9 +364,9 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
   else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
   else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
   else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8450) return SOC_VENDOR_SNAPDRAGON;
-  else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE;
+  else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M2_ULTRA) return SOC_VENDOR_APPLE;
   else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
-  else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP;
+  else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588S) return SOC_VENDOR_ROCKCHIP;
   else if(soc >= SOC_GOOGLE_TENSOR && soc <= SOC_GOOGLE_TENSOR_G3) return SOC_VENDOR_GOOGLE;
   return SOC_VENDOR_UNKNOWN;
 }

src/arm/sysctl.h

@@ -8,9 +8,6 @@
 // APPLE_CPU_PART_M2_BLIZZARD=0x30,M2_AVALANCHE=0x31
 #define MIDR_APPLE_M2_BLIZZARD  0x610F0300
 #define MIDR_APPLE_M2_AVALANCHE 0x610F0310
-// https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c
-#define MIDR_APPLE_M3_SAWTOOTH  0x610F0480
-#define MIDR_APPLE_M3_EVEREST   0x610F0490
 
 // M1 / A14
 #ifndef CPUFAMILY_ARM_FIRESTORM_ICESTORM
@@ -20,12 +17,6 @@
 #ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD
   #define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D
 #endif
-// M3 / A16 / A17
-// https://ratfactor.com/zig/stdlib-browseable2/c/darwin.zig.html
-// https://github.com/Dr-Noob/cpufetch/issues/210
-#define CPUFAMILY_ARM_EVEREST_SAWTOOTH     0x8765EDEA
-#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO 0x5F4DEA93
-#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX 0x72015832
 
 // For detecting different M1 types
 // NOTE: Could also be achieved detecting different

src/arm/uarch.c

@@ -105,8 +105,6 @@ enum {
   UARCH_FIRESTORM,  // Apple M1 processor (big cores).
   UARCH_BLIZZARD,   // Apple M2 processor (little cores).
   UARCH_AVALANCHE,  // Apple M2 processor (big cores).
-  UARCH_SAWTOOTH,   // Apple M3 processor (little cores).
-  UARCH_EVEREST,    // Apple M3 processor (big cores).
   // CAVIUM
   UARCH_THUNDERX,   // Cavium ThunderX
   UARCH_THUNDERX2,  // Cavium ThunderX2 (originally Broadcom Vulkan).
@@ -222,7 +220,6 @@ void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u,
  * Other sources:
  * - https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/asm/cputype.h
  * - https://elixir.bootlin.com/linux/latest/source/arch/arm/include/asm/cputype.h
- * - https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c
  */
 struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   struct uarch* arch = emalloc(sizeof(struct uarch));
@@ -330,8 +327,6 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   CHECK_UARCH(arch, cpu, 'a', 0x023, NA, NA, "Firestorm",             UARCH_FIRESTORM,    CPU_VENDOR_APPLE)
   CHECK_UARCH(arch, cpu, 'a', 0x030, NA, NA, "Blizzard",              UARCH_BLIZZARD,     CPU_VENDOR_APPLE)
   CHECK_UARCH(arch, cpu, 'a', 0x031, NA, NA, "Avalanche",             UARCH_AVALANCHE,    CPU_VENDOR_APPLE)
-  CHECK_UARCH(arch, cpu, 'a', 0x048, NA, NA, "Sawtooth",              UARCH_SAWTOOTH,     CPU_VENDOR_APPLE)
-  CHECK_UARCH(arch, cpu, 'a', 0x049, NA, NA, "Everest",               UARCH_EVEREST,      CPU_VENDOR_APPLE)
 
   CHECK_UARCH(arch, cpu, 'V', 0x581, NA, NA, "PJ4",                   UARCH_PJ4,          CPU_VENDOR_MARVELL)
   CHECK_UARCH(arch, cpu, 'V', 0x584, NA, NA, "PJ4B-MP",               UARCH_PJ4,          CPU_VENDOR_MARVELL)
@@ -392,7 +387,6 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
   MICROARCH ua = cpu->arch->uarch;
 
   switch(ua) {
-    case UARCH_EVEREST:     // Just a guess, needs confirmation.
     case UARCH_FIRESTORM:   // [https://dougallj.github.io/applecpu/firestorm-simd.html]
     case UARCH_AVALANCHE:   // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
     case UARCH_CORTEX_X1:   // [https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging/3]
@@ -400,7 +394,6 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
     case UARCH_CORTEX_X3:   // [https://www.hwcooling.net/en/cortex-x3-the-new-fastest-arm-core-architecture-analysis: "The FPU and SIMD unit of the core still has four pipelines"]
     case UARCH_NEOVERSE_V1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v1]
       return 4;
-    case UARCH_SAWTOOTH:    // Needs confirmation, rn this is the best we know: https://mastodon.social/@dougall/111118317031041336
     case UARCH_EXYNOS_M3:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
     case UARCH_EXYNOS_M4:   // [https://en.wikichip.org/wiki/samsung/microarchitectures/m4#Block_Diagram]
     case UARCH_EXYNOS_M5:   // [https://en.wikichip.org/wiki/samsung/microarchitectures/m5]

src/common/cpu.h

@@ -38,7 +38,6 @@ enum {
   HV_VENDOR_PARALLELS,
   HV_VENDOR_PHYP,
   HV_VENDOR_BHYVE,
-  HV_VENDOR_APPLEVZ,
   HV_VENDOR_INVALID
 };
 

src/ppc/ppc.c

@@ -20,7 +20,6 @@ static char *hv_vendors_name[] = {
   [HV_VENDOR_PARALLELS] = "Parallels",
   [HV_VENDOR_PHYP]      = "pHyp",
   [HV_VENDOR_BHYVE]     = "bhyve",
-  [HV_VENDOR_APPLEVZ]   = "Apple VZ",
   [HV_VENDOR_INVALID]   = STRING_UNKNOWN
 };
 

src/x86/cpuid.c

@@ -30,9 +30,8 @@ static const char *hv_vendors_string[] = {
   [HV_VENDOR_VMWARE]    = "VMwareVMware",
   [HV_VENDOR_XEN]       = "XenVMMXenVMM",
   [HV_VENDOR_PARALLELS] = "lrpepyh vr",
-  [HV_VENDOR_PHYP]      = NULL,
   [HV_VENDOR_BHYVE]     = "bhyve bhyve ",
-  [HV_VENDOR_APPLEVZ]   = "Apple VZ"
+  [HV_VENDOR_PHYP]      = NULL
 };
 
 static char *hv_vendors_name[] = {
@@ -44,7 +43,6 @@ static char *hv_vendors_name[] = {
   [HV_VENDOR_PARALLELS] = "Parallels",
   [HV_VENDOR_PHYP]      = "pHyp",
   [HV_VENDOR_BHYVE]     = "bhyve",
-  [HV_VENDOR_APPLEVZ]   = "Apple VZ",
   [HV_VENDOR_INVALID]   = STRING_UNKNOWN
 };
 
@@ -286,7 +284,7 @@ struct hypervisor* get_hp_info(bool hv_present) {
 
     if(!found) {
       hv->hv_vendor = HV_VENDOR_INVALID;
-      printBug("Unknown hypervisor vendor: '%s'", name);
+      printBug("Unknown hypervisor vendor: %s", name);
     }
   }
 
@@ -1172,8 +1170,10 @@ void print_raw(struct cpuInfo* cpu) {
 }
 
 void free_topo_struct(struct topology* topo) {
-  free(topo->apic->cache_select_mask);
+  if(topo->apic->cache_select_mask != NULL)
-  free(topo->apic->cache_id_apic);
+    free(topo->apic->cache_select_mask);
+  if(topo->apic->cache_id_apic != NULL)
+    free(topo->apic->cache_id_apic);
   free(topo->apic);
   free(topo);
 }