[v1.06][PPC] Small correction

README.md

@@ -174,6 +174,7 @@ Thanks to the fellow contributors and interested people in the project. Special
 - [bbonev](https://github.com/bbonev) and [stephan-cr](https://github.com/stephan-cr): Reviewed the source code.
 - [mdoksa76](https://github.com/mdoksa76) and [exkc](https://github.com/exkc): Excellent ideas and feedback for supporting Allwinner SoCs.
 - [Sakura286](https://github.com/Sakura286), [exkc](https://github.com/exkc) and [Patola](https://github.com/Patola): Helped with RISC-V port with ssh access, ideas, testing, etc.
+- [ThomasKaiser](https://github.com/ThomasKaiser): Very valuable feedback on improving ARM SoC detection (Apple, Allwinner, Rockchip).
 
 ## 8. cpufetch for GPUs (gpufetch)
 See [gpufetch](https://github.com/Dr-Noob/gpufetch) project!

src/arm/midr.c

@@ -237,7 +237,7 @@ struct cpuInfo* get_cpu_info_linux(struct cpuInfo* cpu) {
   cpu->num_cpus = sockets;
   cpu->hv = emalloc(sizeof(struct hypervisor));
   cpu->hv->present = false;
-  cpu->soc = get_soc();
+  cpu->soc = get_soc(cpu);
   cpu->peak_performance = get_peak_performance(cpu);
 
   return cpu;
@@ -374,23 +374,23 @@ struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
   // the CPU is an Apple SoC
   if(cpu_family == CPUFAMILY_ARM_FIRESTORM_ICESTORM) {
     fill_cpu_info_firestorm_icestorm(cpu, pcores, ecores);
-    cpu->soc = get_soc();
+    cpu->soc = get_soc(cpu);
     cpu->peak_performance = get_peak_performance(cpu);
   }
   else if(cpu_family == CPUFAMILY_ARM_AVALANCHE_BLIZZARD) {
     fill_cpu_info_avalanche_blizzard(cpu, pcores, ecores);
-    cpu->soc = get_soc();
+    cpu->soc = get_soc(cpu);
     cpu->peak_performance = get_peak_performance(cpu);
   }
   else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
           cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
           cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
     fill_cpu_info_everest_sawtooth(cpu, pcores, ecores);
-    cpu->soc = get_soc();
+    cpu->soc = get_soc(cpu);
     cpu->peak_performance = get_peak_performance(cpu);
   }
   else {
-    printBug("Found invalid cpu_family: 0x%.8X", cpu_family);
+    printBugCheckRelease("Found invalid cpu_family: 0x%.8X", cpu_family);
     return NULL;
   }
 
@@ -479,7 +479,10 @@ void print_debug(struct cpuInfo* cpu) {
   #if defined(__APPLE__) || defined(__MACH__)
     printf("hw.cpufamily: 0x%.8X\n", get_sys_info_by_name("hw.cpufamily"));
     printf("hw.cpusubfamily: 0x%.8X\n", get_sys_info_by_name("hw.cpusubfamily"));
+    printf("hw.nperflevels: %d\n", get_sys_info_by_name("hw.nperflevels"));
     printf("hw.physicalcpu: %d\n", get_sys_info_by_name("hw.physicalcpu"));
+    printf("hw.perflevel0.physicalcpu: %d\n", get_sys_info_by_name("hw.perflevel0.physicalcpu"));
+    printf("hw.perflevel1.physicalcpu: %d\n", get_sys_info_by_name("hw.perflevel1.physicalcpu"));
   #endif
 }
 

src/arm/soc.c

@@ -6,6 +6,7 @@
 #include "soc.h"
 #include "socs.h"
 #include "udev.h"
+#include "uarch.h"
 #include "../common/global.h"
 
 #if defined(__APPLE__) || defined(__MACH__)
@@ -50,6 +51,8 @@ uint32_t get_sid_from_nvmem(char* buf) {
 // SIDs list:
 // - https://linux-sunxi.org/SID_Register_Guide#Currently_known_SID.27s
 // - https://github.com/Dr-Noob/cpufetch/issues/173
+// - https://github.com/ThomasKaiser/sbc-bench/blob/master/sbc-bench.sh
+// - https://linux-sunxi.org/*CHIP_NAME*
 bool get_sunxisoc_from_sid(struct system_on_chip* soc, char* raw_name, uint32_t sid) {
   typedef struct {
     uint32_t sid;
@@ -58,23 +61,41 @@ bool get_sunxisoc_from_sid(struct system_on_chip* soc, char* raw_name, uint32_t
 
   sidToSoC socFromSid[] = {
     // --- sun8i Family ---
+    // A33
+    {0x0461872a, {SOC_ALLWINNER_A33,    SOC_VENDOR_ALLWINNER, 40, "A33",  raw_name} },
+    // A83T
+    {0x32c00401, {SOC_ALLWINNER_A83T,   SOC_VENDOR_ALLWINNER, 28, "A83T", raw_name} },
+    {0x32c00403, {SOC_ALLWINNER_A83T,   SOC_VENDOR_ALLWINNER, 28, "A83T", raw_name} },
+    // S3
+    {0x12c00001, {SOC_ALLWINNER_S3,     SOC_VENDOR_ALLWINNER, 40, "S3",   raw_name} },
     // H2+
     {0x02c00042, {SOC_ALLWINNER_H2PLUS, SOC_VENDOR_ALLWINNER, 40, "H2+",  raw_name} },
     {0x02c00142, {SOC_ALLWINNER_H2PLUS, SOC_VENDOR_ALLWINNER, 40, "H2+",  raw_name} },
+    {0x02c00242, {SOC_ALLWINNER_H2PLUS, SOC_VENDOR_ALLWINNER, 40, "H2+",  raw_name} },
     // H3
     {0x02c00181, {SOC_ALLWINNER_H3,     SOC_VENDOR_ALLWINNER, 40, "H3",   raw_name} },
     {0x02c00081, {SOC_ALLWINNER_H3,     SOC_VENDOR_ALLWINNER, 40, "H3",   raw_name} },
-    // Others
+    // R40
     {0x12c00017, {SOC_ALLWINNER_R40,    SOC_VENDOR_ALLWINNER, 40, "R40",  raw_name} },
+    // V3S
     {0x12c00000, {SOC_ALLWINNER_V3S,    SOC_VENDOR_ALLWINNER, 40, "V3s",  raw_name} }, // 40nm is only my guess, no source
     // --- sun50i Family ---
+    // H5
     {0x82800001, {SOC_ALLWINNER_H5,     SOC_VENDOR_ALLWINNER, 40, "H5",   raw_name} },
+    // H6
+    {0x82c00001, {SOC_ALLWINNER_H6,     SOC_VENDOR_ALLWINNER, 28, "H6",   raw_name} },
     {0x82c00007, {SOC_ALLWINNER_H6,     SOC_VENDOR_ALLWINNER, 28, "H6",   raw_name} },
-    {0x92c000bb, {SOC_ALLWINNER_H64,    SOC_VENDOR_ALLWINNER, 40, "H64",  raw_name} }, // Same as A64
+    // H64
+    {0x92c000bb, {SOC_ALLWINNER_H64,    SOC_VENDOR_ALLWINNER, 40, "H64",  raw_name} }, // Same manufacturing process as A64
+    // H616
     {0x32c05000, {SOC_ALLWINNER_H616,   SOC_VENDOR_ALLWINNER, 28, "H616", raw_name} },
+    // H618
+    {0x33802000, {SOC_ALLWINNER_H618,   SOC_VENDOR_ALLWINNER, 28, "H618", raw_name} },
+    // A64
     {0x92c000ba, {SOC_ALLWINNER_A64,    SOC_VENDOR_ALLWINNER, 40, "A64",  raw_name} },
+    {0x92c001ba, {SOC_ALLWINNER_A64,    SOC_VENDOR_ALLWINNER, 40, "A64",  raw_name} },
     // Unknown
-    {0x00000000, {UNKNOWN,              SOC_VENDOR_UNKNOWN,   -1, "",    raw_name} }
+    {0x00000000, {UNKNOWN,              SOC_VENDOR_UNKNOWN,   -1, "",     raw_name} }
   };
 
   int index = 0;
@@ -781,6 +802,38 @@ struct system_on_chip* guess_soc_from_nvmem(struct system_on_chip* soc) {
   return soc;
 }
 
+struct system_on_chip* guess_soc_from_uarch(struct system_on_chip* soc, struct cpuInfo* cpu) {
+  // Currently we only support CPUs with only one uarch (in other words, one socket)
+  struct uarch* arch = cpu->arch;
+  if (arch == NULL) {
+    printWarn("guess_soc_from_uarch: uarch is NULL");
+    return soc;
+  }
+
+  typedef struct {
+    MICROARCH u;
+    struct system_on_chip soc;
+  } uarchToSoC;
+
+  uarchToSoC socFromUarch[] = {
+    {UARCH_TAISHAN_V110, {SOC_KUNPENG_920,  SOC_VENDOR_KUNPENG,  7, "920", NULL} },
+    {UARCH_TAISHAN_V200, {SOC_KUNPENG_930,  SOC_VENDOR_KUNPENG,  7, "930", NULL} }, // manufacturing process is not well-known
+    {UARCH_UNKNOWN,      {UNKNOWN,          SOC_VENDOR_UNKNOWN, -1,    "", NULL} }
+  };
+
+  int index = 0;
+  while(socFromUarch[index].u != UARCH_UNKNOWN) {
+    if(socFromUarch[index].u == get_uarch(arch)) {
+      fill_soc(soc, socFromUarch[index].soc.soc_name, socFromUarch[index].soc.soc_model, socFromUarch[index].soc.process);
+      return soc;
+    }
+    index++;
+  }
+
+  printWarn("guess_soc_from_uarch: No uarch matched the list");
+  return soc;
+}
+
 int hex2int(char c) {
   if (c >= '0' && c <= '9')
     return c - '0';
@@ -858,7 +911,7 @@ struct system_on_chip* guess_soc_apple(struct system_on_chip* soc) {
       }
     }
     else {
-      printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
+      printBugCheckRelease("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
       soc->soc_vendor = SOC_VENDOR_UNKNOWN;
     }
   }
@@ -885,7 +938,7 @@ struct system_on_chip* guess_soc_apple(struct system_on_chip* soc) {
       }
     }
     else {
-      printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
+      printBugCheckRelease("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
       soc->soc_vendor = SOC_VENDOR_UNKNOWN;
     }
   }
@@ -903,19 +956,19 @@ struct system_on_chip* guess_soc_apple(struct system_on_chip* soc) {
       fill_soc(soc, "M3 Max", SOC_APPLE_M3_MAX, 3);
     }
     else {
-      printBug("Found invalid cpu_family: 0x%.8X", cpu_family);
+      printBugCheckRelease("Found invalid cpu_family: 0x%.8X", cpu_family);
       soc->soc_vendor = SOC_VENDOR_UNKNOWN;
     }
   }
   else {
-    printBug("Found invalid cpu_family: 0x%.8X", cpu_family);
+    printBugCheckRelease("Found invalid cpu_family: 0x%.8X", cpu_family);
     soc->soc_vendor = SOC_VENDOR_UNKNOWN;
   }
   return soc;
 }
 #endif
 
-struct system_on_chip* get_soc(void) {
+struct system_on_chip* get_soc(struct cpuInfo* cpu) {
   struct system_on_chip* soc = emalloc(sizeof(struct system_on_chip));
   soc->raw_name = NULL;
   soc->soc_vendor = SOC_VENDOR_UNKNOWN;
@@ -955,6 +1008,10 @@ struct system_on_chip* get_soc(void) {
     if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
       soc = guess_soc_from_nvmem(soc);
     }
+    // If everything else failed, try infering it from the microarchitecture
+    if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+      soc = guess_soc_from_uarch(soc, cpu);
+    }
   }
 #elif defined __APPLE__ || __MACH__
   soc = guess_soc_apple(soc);

src/arm/soc.h

@@ -5,6 +5,6 @@
 #include "../common/soc.h"
 #include <stdint.h>
 
-struct system_on_chip* get_soc(void);
+struct system_on_chip* get_soc(struct cpuInfo* cpu);
 
 #endif

src/arm/socs.h

@@ -29,6 +29,9 @@ enum {
   SOC_HISILICON_3670,
   SOC_HISILICON_3680,
   SOC_HISILICON_3690,
+  // Kunpeng //
+  SOC_KUNPENG_920,
+  SOC_KUNPENG_930,
   // Exynos //
   SOC_EXYNOS_3475,
   SOC_EXYNOS_4210,
@@ -329,12 +332,14 @@ enum {
   SOC_ALLWINNER_V3S,
   SOC_ALLWINNER_HZP,
   SOC_ALLWINNER_H2PLUS,
+  SOC_ALLWINNER_S3,
   SOC_ALLWINNER_H3,
   SOC_ALLWINNER_H8,
   SOC_ALLWINNER_H5,
   SOC_ALLWINNER_H6,
   SOC_ALLWINNER_H64,
   SOC_ALLWINNER_H616,
+  SOC_ALLWINNER_H618,
   SOC_ALLWINNER_R8,
   SOC_ALLWINNER_R16,
   SOC_ALLWINNER_R40,
@@ -365,6 +370,7 @@ enum {
 inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
   if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_2712) return SOC_VENDOR_BROADCOM;
   else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_3690) return SOC_VENDOR_KIRIN;
+  else if(soc >= SOC_KUNPENG_920 && soc <= SOC_KUNPENG_930) return SOC_VENDOR_KUNPENG;
   else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
   else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
   else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8450) return SOC_VENDOR_SNAPDRAGON;

src/arm/uarch.c

@@ -10,7 +10,6 @@
 // Data not available
 #define NA                   -1
 
-typedef uint32_t MICROARCH;
 typedef uint32_t ISA;
 
 struct uarch {
@@ -37,89 +36,6 @@ enum {
   ISA_ARMv9_A
 };
 
-enum {
-  UARCH_UNKNOWN,
-  // ARM
-  UARCH_ARM7,
-  UARCH_ARM9,
-  UARCH_ARM1136,
-  UARCH_ARM1156,
-  UARCH_ARM1176,
-  UARCH_ARM11MPCORE,
-  UARCH_CORTEX_A5,
-  UARCH_CORTEX_A7,
-  UARCH_CORTEX_A8,
-  UARCH_CORTEX_A9,
-  UARCH_CORTEX_A12,
-  UARCH_CORTEX_A15,
-  UARCH_CORTEX_A17,
-  UARCH_CORTEX_A32,
-  UARCH_CORTEX_A35,
-  UARCH_CORTEX_A53,
-  UARCH_CORTEX_A55r0, // ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+).
-  UARCH_CORTEX_A55,
-  UARCH_CORTEX_A57,
-  UARCH_CORTEX_A65,
-  UARCH_CORTEX_A72,
-  UARCH_CORTEX_A73,
-  UARCH_CORTEX_A75,
-  UARCH_CORTEX_A76,
-  UARCH_CORTEX_A77,
-  UARCH_CORTEX_A78,
-  UARCH_CORTEX_A510,
-  UARCH_CORTEX_A710,
-  UARCH_CORTEX_A715,
-  UARCH_CORTEX_X1,
-  UARCH_CORTEX_X2,
-  UARCH_CORTEX_X3,
-  UARCH_NEOVERSE_N1,
-  UARCH_NEOVERSE_E1,
-  UARCH_NEOVERSE_V1,
-  UARCH_SCORPION,
-  UARCH_KRAIT,
-  UARCH_KYRO,
-  UARCH_FALKOR,
-  UARCH_SAPHIRA,
-  UARCH_DENVER,
-  UARCH_DENVER2,
-  UARCH_CARMEL,
-  // SAMSUNG
-  UARCH_EXYNOS_M1,  // Samsung Exynos M1 (Exynos 8890 big cores)
-  UARCH_EXYNOS_M2,  // Samsung Exynos M2 (Exynos 8895 big cores)
-  UARCH_EXYNOS_M3,  // Samsung Exynos M3 (Exynos 9810 big cores)
-  UARCH_EXYNOS_M4,  // Samsung Exynos M4 (Exynos 9820 big cores)
-  UARCH_EXYNOS_M5,  // Samsung Exynos M5 (Exynos 9830 big cores)
-  // APPLE
-  UARCH_SWIFT,      // Apple A6 and A6X processors.
-  UARCH_CYCLONE,    // Apple A7 processor.
-  UARCH_TYPHOON,    // Apple A8 and A8X processor
-  UARCH_TWISTER,    // Apple A9 and A9X processor.
-  UARCH_HURRICANE,  // Apple A10 and A10X processor.
-  UARCH_MONSOON,    // Apple A11 processor (big cores).
-  UARCH_MISTRAL,    // Apple A11 processor (little cores).
-  UARCH_VORTEX,     // Apple A12 processor (big cores).
-  UARCH_TEMPEST,    // Apple A12 processor (big cores).
-  UARCH_LIGHTNING,  // Apple A13 processor (big cores).
-  UARCH_THUNDER,    // Apple A13 processor (little cores).
-  UARCH_ICESTORM,   // Apple M1 processor (little cores).
-  UARCH_FIRESTORM,  // Apple M1 processor (big cores).
-  UARCH_BLIZZARD,   // Apple M2 processor (little cores).
-  UARCH_AVALANCHE,  // Apple M2 processor (big cores).
-  UARCH_SAWTOOTH,   // Apple M3 processor (little cores).
-  UARCH_EVEREST,    // Apple M3 processor (big cores).
-  // CAVIUM
-  UARCH_THUNDERX,   // Cavium ThunderX
-  UARCH_THUNDERX2,  // Cavium ThunderX2 (originally Broadcom Vulkan).
-  // MARVELL
-  UARCH_PJ4,
-  UARCH_BRAHMA_B15,
-  UARCH_BRAHMA_B53,
-  UARCH_XGENE,        // Applied Micro X-Gene.
-  UARCH_TAISHAN_V110, // HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors).
-  // PHYTIUM
-  UARCH_XIAOMI,       // Not to be confused with Xiaomi Inc
-};
-
 static const ISA isas_uarch[] = {
   [UARCH_ARM1136]      = ISA_ARMv6,
   [UARCH_ARM1156]      = ISA_ARMv6_T2,
@@ -159,6 +75,7 @@ static const ISA isas_uarch[] = {
   [UARCH_THUNDERX]     = ISA_ARMv8_A,
   [UARCH_THUNDERX2]    = ISA_ARMv8_1_A,
   [UARCH_TAISHAN_V110] = ISA_ARMv8_2_A,
+  [UARCH_TAISHAN_V200] = ISA_ARMv8_2_A, // Not confirmed
   [UARCH_DENVER]       = ISA_ARMv8_A,
   [UARCH_DENVER2]      = ISA_ARMv8_A,
   [UARCH_CARMEL]       = ISA_ARMv8_A,
@@ -200,8 +117,7 @@ static char* isas_string[] = {
 #define UARCH_START if (false) {}
 #define CHECK_UARCH(arch, cpu, im_, p_, v_, r_, str, uarch, vendor) \
    else if (im_ == im && p_ == p && (v_ == NA || v_ == v) && (r_ == NA || r_ == r)) fill_uarch(arch, cpu, str, uarch, vendor);
-#define UARCH_END else { printErr("Unknown microarchitecture detected: IM=0x%X P=0x%X V=0x%X R=0x%X", im, p, v, r); \
-fprintf(stderr, "Please see https://github.com/Dr-Noob/cpufetch#61-unknown-microarchitecture-error to know how to report this error\n"); \
+#define UARCH_END else { printBugCheckRelease("Unknown microarchitecture detected: IM=0x%X P=0x%X V=0x%X R=0x%X", im, p, v, r); \
 fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
 
 void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
@@ -285,8 +201,9 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   CHECK_UARCH(arch, cpu, 'C', 0x0A3, NA, NA, "ThunderX 81XX",         UARCH_THUNDERX,     CPU_VENDOR_CAVIUM)
   CHECK_UARCH(arch, cpu, 'C', 0x0AF, NA, NA, "ThunderX2 99XX",        UARCH_THUNDERX2,    CPU_VENDOR_CAVIUM)
 
-  CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110",          UARCH_TAISHAN_V110, CPU_VENDOR_HUAWUEI) // Kunpeng 920 series
-  CHECK_UARCH(arch, cpu, 'H', 0xD40, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)     // Kirin 980 Big/Medium cores -> Cortex-A76
+  CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110",          UARCH_TAISHAN_V110, CPU_VENDOR_HUAWEI) // Kunpeng 920 series
+  CHECK_UARCH(arch, cpu, 'H', 0xD02, NA, NA, "TaiShan v200",          UARCH_TAISHAN_V200, CPU_VENDOR_HUAWEI) // Kunpeng 930 series (found in openeuler: https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/XQCV7NX2UKRIUWUFKRF4PO3QENCOUFR3)
+  CHECK_UARCH(arch, cpu, 'H', 0xD40, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)    // Kirin 980 Big/Medium cores -> Cortex-A76
 
   CHECK_UARCH(arch, cpu, 'N', 0x000, NA, NA, "Denver",                UARCH_DENVER,       CPU_VENDOR_NVIDIA)
   CHECK_UARCH(arch, cpu, 'N', 0x003, NA, NA, "Denver2",               UARCH_DENVER2,      CPU_VENDOR_NVIDIA)
@@ -407,6 +324,8 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
       return 3;
     case UARCH_ICESTORM:    // [https://dougallj.github.io/applecpu/icestorm-simd.html]
     case UARCH_BLIZZARD:    // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
+    case UARCH_TAISHAN_V110:// [https://www-file.huawei.com/-/media/corp2020/pdf/publications/huawei-research/2022/huawei-research-issue1-en.pdf]: "128-bit x 2 for single precision"
+    case UARCH_TAISHAN_V200:// Not confirmed, asssuming same as v110
     case UARCH_CORTEX_A57:  // [https://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/5]
     case UARCH_CORTEX_A72:  // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]
     case UARCH_CORTEX_A73:  // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]
@@ -438,6 +357,10 @@ char* get_str_uarch(struct cpuInfo* cpu) {
   return cpu->arch->uarch_str;
 }
 
+MICROARCH get_uarch(struct uarch* arch) {
+  return arch->uarch;
+}
+
 void free_uarch_struct(struct uarch* arch) {
   free(arch->uarch_str);
   free(arch);

src/arm/uarch.h

@@ -5,11 +5,98 @@
 
 #include "midr.h"
 
+enum {
+  UARCH_UNKNOWN,
+  // ARM
+  UARCH_ARM7,
+  UARCH_ARM9,
+  UARCH_ARM1136,
+  UARCH_ARM1156,
+  UARCH_ARM1176,
+  UARCH_ARM11MPCORE,
+  UARCH_CORTEX_A5,
+  UARCH_CORTEX_A7,
+  UARCH_CORTEX_A8,
+  UARCH_CORTEX_A9,
+  UARCH_CORTEX_A12,
+  UARCH_CORTEX_A15,
+  UARCH_CORTEX_A17,
+  UARCH_CORTEX_A32,
+  UARCH_CORTEX_A35,
+  UARCH_CORTEX_A53,
+  UARCH_CORTEX_A55r0, // ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+).
+  UARCH_CORTEX_A55,
+  UARCH_CORTEX_A57,
+  UARCH_CORTEX_A65,
+  UARCH_CORTEX_A72,
+  UARCH_CORTEX_A73,
+  UARCH_CORTEX_A75,
+  UARCH_CORTEX_A76,
+  UARCH_CORTEX_A77,
+  UARCH_CORTEX_A78,
+  UARCH_CORTEX_A510,
+  UARCH_CORTEX_A710,
+  UARCH_CORTEX_A715,
+  UARCH_CORTEX_X1,
+  UARCH_CORTEX_X2,
+  UARCH_CORTEX_X3,
+  UARCH_NEOVERSE_N1,
+  UARCH_NEOVERSE_E1,
+  UARCH_NEOVERSE_V1,
+  UARCH_SCORPION,
+  UARCH_KRAIT,
+  UARCH_KYRO,
+  UARCH_FALKOR,
+  UARCH_SAPHIRA,
+  UARCH_DENVER,
+  UARCH_DENVER2,
+  UARCH_CARMEL,
+  // SAMSUNG
+  UARCH_EXYNOS_M1,  // Samsung Exynos M1 (Exynos 8890 big cores)
+  UARCH_EXYNOS_M2,  // Samsung Exynos M2 (Exynos 8895 big cores)
+  UARCH_EXYNOS_M3,  // Samsung Exynos M3 (Exynos 9810 big cores)
+  UARCH_EXYNOS_M4,  // Samsung Exynos M4 (Exynos 9820 big cores)
+  UARCH_EXYNOS_M5,  // Samsung Exynos M5 (Exynos 9830 big cores)
+  // APPLE
+  UARCH_SWIFT,      // Apple A6 and A6X processors.
+  UARCH_CYCLONE,    // Apple A7 processor.
+  UARCH_TYPHOON,    // Apple A8 and A8X processor
+  UARCH_TWISTER,    // Apple A9 and A9X processor.
+  UARCH_HURRICANE,  // Apple A10 and A10X processor.
+  UARCH_MONSOON,    // Apple A11 processor (big cores).
+  UARCH_MISTRAL,    // Apple A11 processor (little cores).
+  UARCH_VORTEX,     // Apple A12 processor (big cores).
+  UARCH_TEMPEST,    // Apple A12 processor (big cores).
+  UARCH_LIGHTNING,  // Apple A13 processor (big cores).
+  UARCH_THUNDER,    // Apple A13 processor (little cores).
+  UARCH_ICESTORM,   // Apple M1 processor (little cores).
+  UARCH_FIRESTORM,  // Apple M1 processor (big cores).
+  UARCH_BLIZZARD,   // Apple M2 processor (little cores).
+  UARCH_AVALANCHE,  // Apple M2 processor (big cores).
+  UARCH_SAWTOOTH,   // Apple M3 processor (little cores).
+  UARCH_EVEREST,    // Apple M3 processor (big cores).
+  // CAVIUM
+  UARCH_THUNDERX,   // Cavium ThunderX
+  UARCH_THUNDERX2,  // Cavium ThunderX2 (originally Broadcom Vulkan).
+  // MARVELL
+  UARCH_PJ4,
+  UARCH_BRAHMA_B15,
+  UARCH_BRAHMA_B53,
+  UARCH_XGENE,        // Applied Micro X-Gene.
+  UARCH_TAISHAN_V110, // HiSilicon TaiShan v110
+  UARCH_TAISHAN_V200, // HiSilicon TaiShan v200
+  // PHYTIUM
+  UARCH_XIAOMI,       // Not to be confused with Xiaomi Inc
+};
+
+typedef uint32_t MICROARCH;
+
 struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu);
 int get_number_of_vpus(struct cpuInfo* cpu);
 int get_vpus_width(struct cpuInfo* cpu);
 bool has_fma_support(struct cpuInfo* cpu);
 char* get_str_uarch(struct cpuInfo* cpu);
 void free_uarch_struct(struct uarch* arch);
+MICROARCH get_uarch(struct uarch* arch);
 
 #endif

src/common/ascii.h

@@ -145,6 +145,25 @@ $C2     Exynos           \
 $C2                      \
 $C2                      "
 
+#define ASCII_KUNPENG \
+"$C2                                             .  \
+$C2                                          ..    \
+$C2                                       .##      \
+$C1                                 .$CR  $C2.###.       \
+$C1                            ..$CR   $C2#####.         \
+$C1                       .#.$CR   $C2.#######.          \
+$C1                 .####.$CR   $C2.#######.             \
+$C1           ..######*$CR  $C2.#######.   .             \
+$C1      .#########*$CR  $C2.#######*   .                \
+$C1      ######*$CR  $C2.#######.   .#.                  \
+$C1*#######*$CR   $C2.#######.   *##.                    \
+$C1    ##*$CR $C2.#######.   #######                     \
+$C2          ###.$CR $C1#####$C2   *###                     \
+$C1              *##########                       \
+$C1                    *########                   \
+$C1                          #####.                \
+$C1                             *###.              "
+
 #define ASCII_KIRIN \
 "$C1                                #######              \
 $C1    #####             ####################           \
@@ -485,6 +504,7 @@ asciiL logo_snapd       = { ASCII_SNAPD,       39, 16, false, {C_FG_RED, C_FG_WH
 asciiL logo_mtk         = { ASCII_MTK,         59,  5, false, {C_FG_BLUE, C_FG_YELLOW},                       {C_FG_BLUE,    C_FG_YELLOW}  };
 asciiL logo_exynos      = { ASCII_EXYNOS,      22, 13, true,  {C_BG_BLUE, C_FG_WHITE},                        {C_FG_BLUE,    C_FG_WHITE}   };
 asciiL logo_kirin       = { ASCII_KIRIN,       53, 12, false, {C_FG_RED},                                     {C_FG_WHITE,   C_FG_RED}     };
+asciiL logo_kunpeng     = { ASCII_KUNPENG,     48, 17, false, {C_FG_RED, C_FG_WHITE},                         {C_FG_WHITE,   C_FG_RED}     };
 asciiL logo_broadcom    = { ASCII_BROADCOM,    44, 19, false, {C_FG_WHITE, C_FG_RED},                         {C_FG_WHITE,   C_FG_RED}     };
 asciiL logo_arm         = { ASCII_ARM,         42,  5, false, {C_FG_CYAN},                                    {C_FG_WHITE,   C_FG_CYAN}    };
 asciiL logo_ibm         = { ASCII_IBM,         42,  9, false, {C_FG_CYAN, C_FG_WHITE},                        {C_FG_CYAN,    C_FG_WHITE}   };

src/common/cpu.h

@@ -16,7 +16,7 @@ enum {
   CPU_VENDOR_NVIDIA,
   CPU_VENDOR_APM,
   CPU_VENDOR_QUALCOMM,
-  CPU_VENDOR_HUAWUEI,
+  CPU_VENDOR_HUAWEI,
   CPU_VENDOR_SAMSUNG,
   CPU_VENDOR_MARVELL,
   CPU_VENDOR_PHYTIUM,
@@ -32,6 +32,7 @@ enum {
 enum {
   HV_VENDOR_KVM,
   HV_VENDOR_QEMU,
+  HV_VENDOR_VBOX,
   HV_VENDOR_HYPERV,
   HV_VENDOR_VMWARE,
   HV_VENDOR_XEN,

src/common/global.c

@@ -21,7 +21,7 @@
 #endif
 
 #ifdef ARCH_X86
-  static const char* ARCH_STR = "x86_64 build";
+  static const char* ARCH_STR = "x86 / x86_64 build";
   #include "../x86/cpuid.h"
 #elif ARCH_PPC
   static const char* ARCH_STR = "PowerPC build";
@@ -51,7 +51,7 @@
 #endif
 
 #ifndef GIT_FULL_VERSION
-  static const char* VERSION = "1.04";
+  static const char* VERSION = "1.05";
 #endif
 
 enum {
@@ -61,6 +61,14 @@ enum {
 
 int LOG_LEVEL;
 
+void printBugMessage(FILE *restrict stream) {
+  #if defined(ARCH_X86) || defined(ARCH_PPC)
+    fprintf(stream, "Please, create a new issue with this error message, the output of 'cpufetch' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
+  #elif ARCH_ARM
+    fprintf(stream, "Please, create a new issue with this error message, your smartphone/computer model, the output of 'cpufetch --verbose' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
+  #endif
+}
+
 void printWarn(const char *fmt, ...) {
   if(LOG_LEVEL == LOG_LEVEL_VERBOSE) {
     int buffer_size = 4096;
@@ -95,10 +103,40 @@ void printBug(const char *fmt, ...) {
   fprintf(stderr,RED "[ERROR]: "RESET "%s\n",buffer);
   fprintf(stderr,"[VERSION]: ");
   print_version(stderr);
-#if defined(ARCH_X86) || defined(ARCH_PPC)
-  fprintf(stderr, "Please, create a new issue with this error message, the output of 'cpufetch' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
-#elif ARCH_ARM
-  fprintf(stderr, "Please, create a new issue with this error message, your smartphone/computer model, the output of 'cpufetch --verbose' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
+  printBugMessage(stderr);
+}
+
+bool isReleaseVersion(char *git_full_version) {
+  return strstr(git_full_version, "-") == NULL;
+}
+
+/// The unknown uarch errors are by far the most common error a user will encounter.
+/// Rather than using the generic printBug function, which asks the user to report
+/// the problem on the issues webpage, this function will check if the program is
+/// the release version. In such case, support for this feature is most likely already
+/// in the last version, so just tell the user to compile that one and not report this
+/// in github.
+void printBugCheckRelease(const char *fmt, ...) {
+  int buffer_size = 4096;
+  char buffer[buffer_size];
+  va_list args;
+  va_start(args, fmt);
+  vsnprintf(buffer,buffer_size, fmt, args);
+  va_end(args);
+
+  fprintf(stderr, RED "[ERROR]: "RESET "%s\n", buffer);
+  fprintf(stderr, "[VERSION]: ");
+  print_version(stderr);
+
+#ifdef GIT_FULL_VERSION
+  if (isReleaseVersion(GIT_FULL_VERSION)) {
+    fprintf(stderr, RED "[ERROR]: "RESET "You are using an outdated version of cpufetch. Please compile cpufetch from source (see https://github.com/Dr-Noob/cpufetch?tab=readme-ov-file#22-building-from-source)");
+  }
+  else {
+    printBugMessage(stderr);
+  }
+#else
+  printBugMessage(stderr);
 #endif
 }
 

src/common/global.h

@@ -12,6 +12,7 @@ void set_log_level(bool verbose);
 void printWarn(const char *fmt, ...);
 void printErr(const char *fmt, ...);
 void printBug(const char *fmt, ...);
+void printBugCheckRelease(const char *fmt, ...);
 int min(int a, int b);
 int max(int a, int b);
 char *strremove(char *str, const char *sub);

src/common/printer.c

@@ -336,6 +336,13 @@ struct ascii_logo* choose_ascii_art_aux(struct ascii_logo* logo_long, struct asc
   }
 }
 
+// https://no-color.org/
+bool is_color_enabled(void) {
+  const char *var_name = "NO_COLOR";
+  char *no_color = getenv(var_name);
+  return no_color == NULL || no_color[0] == '\0';
+}
+
 void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* term, int lf) {
   // 1. Choose logo
 #ifdef ARCH_X86
@@ -364,6 +371,8 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
     art->art = &logo_exynos;
   else if(art->vendor == SOC_VENDOR_KIRIN)
     art->art = &logo_kirin;
+  else if(art->vendor == SOC_VENDOR_KUNPENG)
+    art->art = &logo_kunpeng;
   else if(art->vendor == SOC_VENDOR_BROADCOM)
     art->art = &logo_broadcom;
   else if(art->vendor == SOC_VENDOR_APPLE)
@@ -392,6 +401,9 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
 
   // 2. Choose colors
   struct ascii_logo* logo = art->art;
+  bool color = is_color_enabled();
+  if (!color)
+    art->style = STYLE_LEGACY;
 
   switch(art->style) {
     case STYLE_LEGACY:

src/common/soc.c

@@ -15,6 +15,7 @@ static char* soc_trademark_string[] = {
   [SOC_VENDOR_MEDIATEK]   = "MediaTek ",
   [SOC_VENDOR_EXYNOS]     = "Exynos ",
   [SOC_VENDOR_KIRIN]      = "Kirin ",
+  [SOC_VENDOR_KUNPENG]    = "Kunpeng ",
   [SOC_VENDOR_BROADCOM]   = "Broadcom BCM",
   [SOC_VENDOR_APPLE]      = "Apple ",
   [SOC_VENDOR_ROCKCHIP]   = "Rockchip ",

src/common/soc.h

@@ -19,6 +19,7 @@ enum {
   SOC_VENDOR_MEDIATEK,
   SOC_VENDOR_EXYNOS,
   SOC_VENDOR_KIRIN,
+  SOC_VENDOR_KUNPENG,
   SOC_VENDOR_BROADCOM,
   SOC_VENDOR_APPLE,
   SOC_VENDOR_ROCKCHIP,
@@ -39,7 +40,7 @@ struct system_on_chip {
   char* raw_name;
 };
 
-struct system_on_chip* get_soc(void);
+struct system_on_chip* get_soc(struct cpuInfo* cpu);
 char* get_soc_name(struct system_on_chip* soc);
 VENDOR get_soc_vendor(struct system_on_chip* soc);
 bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process);

src/ppc/ppc.c

@@ -14,6 +14,7 @@
 static char *hv_vendors_name[] = {
   [HV_VENDOR_KVM]       = "KVM",
   [HV_VENDOR_QEMU]      = "QEMU",
+  [HV_VENDOR_VBOX]      = "VirtualBox",
   [HV_VENDOR_HYPERV]    = "Microsoft Hyper-V",
   [HV_VENDOR_VMWARE]    = "VMware",
   [HV_VENDOR_XEN]       = "Xen",
@@ -80,9 +81,13 @@ struct topology* get_topology_info(struct cache* cach) {
   if(!fill_package_ids_from_sys(package_ids, topo->total_cores)) {
     printWarn("fill_package_ids_from_sys failed, output may be incomplete/invalid");
     for(int i=0; i < topo->total_cores; i++) package_ids[i] = 0;
-    // fill_package_ids_from_sys failed, use a
-    // more sophisticated wat to find the number of sockets
+    // fill_package_ids_from_sys failed, use udev to try
+    // to find the number of sockets
     topo->sockets = get_num_sockets_package_cpus(topo);
+    if (topo->sockets == UNKNOWN_DATA) {
+      printWarn("get_num_sockets_package_cpus failed: assuming 1 socket");
+      topo->sockets = 1;
+    }
   }
   else {
     // fill_package_ids_from_sys succeeded, use the

src/ppc/uarch.c

@@ -25,6 +25,7 @@ enum {
   UARCH_PPC603,
   UARCH_PPC440,
   UARCH_PPC470,
+  UARCH_ESPRESSO, // Not exactly an uarch, but the codename of Wii U
   UARCH_PPC970,
   UARCH_PPC970FX,
   UARCH_PPC970MP,
@@ -75,6 +76,7 @@ void fill_uarch(struct uarch* arch, MICROARCH u) {
   FILL_UARCH(arch->uarch, UARCH_PPC603,      "PowerPC 603",   UNK) // varies
   FILL_UARCH(arch->uarch, UARCH_PPC440,      "PowerPC 440",   UNK)
   FILL_UARCH(arch->uarch, UARCH_PPC470,      "PowerPC 470",    45) // strange...
+  FILL_UARCH(arch->uarch, UARCH_ESPRESSO,    "Espresso",       45) // https://en.wikipedia.org/wiki/PowerPC_7xx#Espresso, https://en.wikipedia.org/wiki/Espresso_(processor)
   FILL_UARCH(arch->uarch, UARCH_PPC970,      "PowerPC 970",   130)
   FILL_UARCH(arch->uarch, UARCH_PPC970FX,    "PowerPC 970FX",  90)
   FILL_UARCH(arch->uarch, UARCH_PPC970MP,    "PowerPC 970MP",  90)
@@ -234,6 +236,7 @@ struct uarch* get_uarch_from_pvr(uint32_t pvr) {
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x7ff50000, UARCH_PPC470)
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x00050000, UARCH_PPC470)
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x11a50000, UARCH_PPC470)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x70010201, UARCH_ESPRESSO)
   UARCH_END
 
   return arch;
@@ -280,9 +283,6 @@ char* get_str_process(struct cpuInfo* cpu) {
   if(process == UNK) {
     snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
   }
-  else if(process > 100) {
-    sprintf(str, "%.2fum", (double)process/100);
-  }
   else if(process > 0){
     sprintf(str, "%dnm", process);
   }

src/riscv/riscv.c

@@ -163,7 +163,7 @@ struct cpuInfo* get_cpu_info(void) {
   cpu->ext = get_extensions_from_str(ext_str);
   if(cpu->ext->str != NULL && cpu->ext->mask == 0) return NULL;
   cpu->arch = get_uarch_from_cpuinfo_str(cpuinfo_str, cpu);
-  cpu->soc = get_soc();
+  cpu->soc = get_soc(cpu);
   cpu->freq = get_frequency_info(0);
   cpu->peak_performance = get_peak_performance(cpu);
 

src/riscv/soc.c

@@ -65,7 +65,7 @@ struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
   return soc;
 }
 
-struct system_on_chip* get_soc(void) {
+struct system_on_chip* get_soc(struct cpuInfo* cpu) {
   struct system_on_chip* soc = emalloc(sizeof(struct system_on_chip));
   soc->raw_name = NULL;
   soc->soc_vendor = SOC_VENDOR_UNKNOWN;

src/riscv/soc.h

@@ -5,6 +5,6 @@
 #include "../common/cpu.h"
 #include <stdint.h>
 
-struct system_on_chip* get_soc(void);
+struct system_on_chip* get_soc(struct cpuInfo* cpu);
 
 #endif

src/x86/cpuid.c

@@ -26,6 +26,7 @@
 static const char *hv_vendors_string[] = {
   [HV_VENDOR_KVM]       = "KVMKVMKVM",
   [HV_VENDOR_QEMU]      = "TCGTCGTCGTCG",
+  [HV_VENDOR_VBOX]      = "VBoxVBoxVBox",
   [HV_VENDOR_HYPERV]    = "Microsoft Hv",
   [HV_VENDOR_VMWARE]    = "VMwareVMware",
   [HV_VENDOR_XEN]       = "XenVMMXenVMM",
@@ -38,6 +39,7 @@ static const char *hv_vendors_string[] = {
 static char *hv_vendors_name[] = {
   [HV_VENDOR_KVM]       = "KVM",
   [HV_VENDOR_QEMU]      = "QEMU",
+  [HV_VENDOR_VBOX]      = "VirtualBox",
   [HV_VENDOR_HYPERV]    = "Microsoft Hyper-V",
   [HV_VENDOR_VMWARE]    = "VMware",
   [HV_VENDOR_XEN]       = "Xen",
@@ -486,9 +488,8 @@ struct cpuInfo* get_cpu_info(void) {
     cpu->cpu_name = get_str_cpu_name_internal();
   }
   else {
-    cpu->cpu_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN) + 1));
-    strcpy(cpu->cpu_name, STRING_UNKNOWN);
-    printWarn("Can't read cpu name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);
+    cpu->cpu_name = NULL;
+    printWarn("Can't read CPU name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);
   }
 
   cpu->topology_extensions = false;
@@ -538,12 +539,17 @@ struct cpuInfo* get_cpu_info(void) {
     ptr->first_core_id = first_core;
     ptr->feat = get_features_info(ptr);
 
-    // If any field of the struct is NULL,
-    // return inmideately, as further functions
-    // require valid fields (cach, topo, etc)
     ptr->arch = get_cpu_uarch(ptr);
     ptr->freq = get_frequency_info(ptr);
 
+    if (cpu->cpu_name == NULL && ptr == cpu) {
+      // If we couldnt read CPU name from cpuid, infer it now
+      cpu->cpu_name = infer_cpu_name_from_uarch(cpu->arch);
+    }
+
+    // If any field of the struct is NULL,
+    // return early, as next functions
+    // require non NULL fields in cach and topo
     ptr->cach = get_cache_info(ptr);
     if(ptr->cach == NULL) return cpu;
 

src/x86/uarch.c

@@ -48,7 +48,9 @@ enum {
   UARCH_UNKNOWN,
   // INTEL //
   UARCH_P5,
-  UARCH_P6,
+  UARCH_P5_MMX,
+  UARCH_P6_PENTIUM_II,
+  UARCH_P6_PENTIUM_III,
   UARCH_DOTHAN,
   UARCH_YONAH,
   UARCH_MEROM,
@@ -125,8 +127,7 @@ struct uarch {
 #define UARCH_START if (false) {}
 #define CHECK_UARCH(arch, ef_, f_, em_, m_, s_, str, uarch, process) \
    else if (ef_ == ef && f_ == f && (em_ == NA || em_ == em) && (m_ == NA || m_ == m) && (s_ == NA || s_ == s)) fill_uarch(arch, str, uarch, process);
-#define UARCH_END else { printErr("Unknown microarchitecture detected: M=0x%X EM=0x%X F=0x%X EF=0x%X S=0x%X", m, em, f, ef, s); \
-fprintf(stderr, "Please see https://github.com/Dr-Noob/cpufetch#61-unknown-microarchitecture-error to know how to report this error\n"); \
+#define UARCH_END else { printBugCheckRelease("Unknown microarchitecture detected: M=0x%X EM=0x%X F=0x%X EF=0x%X S=0x%X", m, em, f, ef, s); \
 fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK); }
 
 void fill_uarch(struct uarch* arch, char* str, MICROARCH u, uint32_t process) {
@@ -140,128 +141,128 @@ void fill_uarch(struct uarch* arch, char* str, MICROARCH u, uint32_t process) {
 struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
   struct uarch* arch = emalloc(sizeof(struct uarch));
 
-  // EF: Extended Family                                                           //
-  // F:  Family                                                                    //
-  // EM: Extended Model                                                            //
-  // M: Model                                                                      //
-  // S: Stepping                                                                   //
-  // ----------------------------------------------------------------------------- //
-  //                EF  F  EM   M   S                                              //
+  // EF: Extended Family                                                             //
+  // F:  Family                                                                      //
+  // EM: Extended Model                                                              //
+  // M: Model                                                                        //
+  // S: Stepping                                                                     //
+  // ------------------------------------------------------------------------------- //
+  //                EF  F  EM   M   S                                                //
   UARCH_START
-  CHECK_UARCH(arch, 0,  5,  0,  0, NA, "P5",              UARCH_P5,              800)
-  CHECK_UARCH(arch, 0,  5,  0,  1, NA, "P5",              UARCH_P5,              800)
-  CHECK_UARCH(arch, 0,  5,  0,  2, NA, "P5",              UARCH_P5,              UNK)
-  CHECK_UARCH(arch, 0,  5,  0,  3, NA, "P5",              UARCH_P5,              600)
-  CHECK_UARCH(arch, 0,  5,  0,  4, NA, "P5 MMX",          UARCH_P5,              UNK)
-  CHECK_UARCH(arch, 0,  5,  0,  7, NA, "P5 MMX",          UARCH_P5,              UNK)
-  CHECK_UARCH(arch, 0,  5,  0,  8, NA, "P5 MMX",          UARCH_P5,              250)
-  CHECK_UARCH(arch, 0,  5,  0,  9,  0, "Lakemont",        UARCH_LAKEMONT,         32)
-  CHECK_UARCH(arch, 0,  5,  0,  9, NA, "P5 MMX",          UARCH_P5,              UNK)
-  CHECK_UARCH(arch, 0,  5,  0, 10,  0, "Lakemont",        UARCH_LAKEMONT,         32)
-  CHECK_UARCH(arch, 0,  6,  0,  0, NA, "P6 Pentium II",   UARCH_P6,              UNK)
-  CHECK_UARCH(arch, 0,  6,  0,  1, NA, "P6 Pentium II",   UARCH_P6,              UNK) // process depends on core
-  CHECK_UARCH(arch, 0,  6,  0,  2, NA, "P6 Pentium II",   UARCH_P6,              UNK)
-  CHECK_UARCH(arch, 0,  6,  0,  3, NA, "P6 Pentium II",   UARCH_P6,              350)
-  CHECK_UARCH(arch, 0,  6,  0,  4, NA, "P6 Pentium II",   UARCH_P6,              UNK)
-  CHECK_UARCH(arch, 0,  6,  0,  5, NA, "P6 Pentium II",   UARCH_P6,              250)
-  CHECK_UARCH(arch, 0,  6,  0,  6, NA, "P6 Pentium II",   UARCH_P6,              UNK)
-  CHECK_UARCH(arch, 0,  6,  0,  7, NA, "P6 Pentium III",  UARCH_P6,              250)
-  CHECK_UARCH(arch, 0,  6,  0,  8, NA, "P6 Pentium III",  UARCH_P6,              180)
-  CHECK_UARCH(arch, 0,  6,  0,  9, NA, "P6 Pentium M",    UARCH_P6,              130)
-  CHECK_UARCH(arch, 0,  6,  0, 10, NA, "P6 Pentium III",  UARCH_P6,              180)
-  CHECK_UARCH(arch, 0,  6,  0, 11, NA, "P6 Pentium III",  UARCH_P6,              130)
-  CHECK_UARCH(arch, 0,  6,  0, 13, NA, "Dothan",          UARCH_DOTHAN,          UNK)  // process depends on core
-  CHECK_UARCH(arch, 0,  6,  0, 14, NA, "Yonah",           UARCH_YONAH,            65)
-  CHECK_UARCH(arch, 0,  6,  0, 15, NA, "Merom",           UARCH_MEROM,            65)
-  CHECK_UARCH(arch, 0,  6,  1,  5, NA, "Dothan",          UARCH_DOTHAN,           90)
-  CHECK_UARCH(arch, 0,  6,  1,  6, NA, "Merom",           UARCH_MEROM,            65)
-  CHECK_UARCH(arch, 0,  6,  1,  7, NA, "Penryn",          UARCH_PENYR,            45)
-  CHECK_UARCH(arch, 0,  6,  1, 10, NA, "Nehalem",         UARCH_NEHALEM,          45)
-  CHECK_UARCH(arch, 0,  6,  1, 12, NA, "Bonnell",         UARCH_BONNELL,          45)
-  CHECK_UARCH(arch, 0,  6,  1, 13, NA, "Penryn",          UARCH_PENYR,            45)
-  CHECK_UARCH(arch, 0,  6,  1, 14, NA, "Nehalem",         UARCH_NEHALEM,          45)
-  CHECK_UARCH(arch, 0,  6,  1, 15, NA, "Nehalem",         UARCH_NEHALEM,          45)
-  CHECK_UARCH(arch, 0,  6,  2,  5, NA, "Westmere",        UARCH_WESTMERE,         32)
-  CHECK_UARCH(arch, 0,  6,  2 , 6, NA, "Bonnell",         UARCH_BONNELL,          45)
-  CHECK_UARCH(arch, 0,  6,  2,  7, NA, "Saltwell",        UARCH_SALTWELL,         32)
-  CHECK_UARCH(arch, 0,  6,  2, 10, NA, "Sandy Bridge",    UARCH_SANDY_BRIDGE,     32)
-  CHECK_UARCH(arch, 0,  6,  2, 12, NA, "Westmere",        UARCH_WESTMERE,         32)
-  CHECK_UARCH(arch, 0,  6,  2, 13, NA, "Sandy Bridge",    UARCH_SANDY_BRIDGE,     32)
-  CHECK_UARCH(arch, 0,  6,  2, 14, NA, "Nehalem",         UARCH_NEHALEM,          45)
-  CHECK_UARCH(arch, 0,  6,  2, 15, NA, "Westmere",        UARCH_WESTMERE,         32)
-  CHECK_UARCH(arch, 0,  6,  3,  5, NA, "Saltwell",        UARCH_SALTWELL,         14)
-  CHECK_UARCH(arch, 0,  6,  3,  6, NA, "Saltwell",        UARCH_SALTWELL,         32)
-  CHECK_UARCH(arch, 0,  6,  3,  7, NA, "Silvermont",      UARCH_SILVERMONT,       22)
-  CHECK_UARCH(arch, 0,  6,  3, 10, NA, "Ivy Bridge",      UARCH_IVY_BRIDGE,       22)
-  CHECK_UARCH(arch, 0,  6,  3, 12, NA, "Haswell",         UARCH_HASWELL,          22)
-  CHECK_UARCH(arch, 0,  6,  3, 13, NA, "Broadwell",       UARCH_BROADWELL,        14)
-  CHECK_UARCH(arch, 0,  6,  3, 14, NA, "Ivy Bridge",      UARCH_IVY_BRIDGE,       22)
-  CHECK_UARCH(arch, 0,  6,  3, 15, NA, "Haswell",         UARCH_HASWELL,          22)
-  CHECK_UARCH(arch, 0,  6,  4,  5, NA, "Haswell",         UARCH_HASWELL,          22)
-  CHECK_UARCH(arch, 0,  6,  4,  6, NA, "Haswell",         UARCH_HASWELL,          22)
-  CHECK_UARCH(arch, 0,  6,  4,  7, NA, "Broadwell",       UARCH_BROADWELL,        14)
-  CHECK_UARCH(arch, 0,  6,  4, 10, NA, "Silvermont",      UARCH_SILVERMONT,       22) // no docs, but /proc/cpuinfo seen in wild
-  CHECK_UARCH(arch, 0,  6,  4, 12, NA, "Airmont",         UARCH_AIRMONT,          14)
-  CHECK_UARCH(arch, 0,  6,  4, 13, NA, "Silvermont",      UARCH_SILVERMONT,       22)
-  CHECK_UARCH(arch, 0,  6,  4, 14,  8, "Kaby Lake",       UARCH_KABY_LAKE,        14)
-  CHECK_UARCH(arch, 0,  6,  4, 14, NA, "Skylake",         UARCH_SKYLAKE,          14)
-  CHECK_UARCH(arch, 0,  6,  4, 15, NA, "Broadwell",       UARCH_BROADWELL,        14)
-  CHECK_UARCH(arch, 0,  6,  5,  5,  6, "Cascade Lake",    UARCH_CASCADE_LAKE,     14) // no docs, but example from Greg Stewart
-  CHECK_UARCH(arch, 0,  6,  5,  5,  7, "Cascade Lake",    UARCH_CASCADE_LAKE,     14)
-  CHECK_UARCH(arch, 0,  6,  5,  5, 10, "Cooper Lake",     UARCH_COOPER_LAKE,      14)
-  CHECK_UARCH(arch, 0,  6,  5,  5, NA, "Skylake",         UARCH_SKYLAKE,          14)
-  CHECK_UARCH(arch, 0,  6,  5,  6, NA, "Broadwell",       UARCH_BROADWELL,        14)
-  CHECK_UARCH(arch, 0,  6,  5,  7, NA, "Knights Landing", UARCH_KNIGHTS_LANDING,  14)
-  CHECK_UARCH(arch, 0,  6,  5, 10, NA, "Silvermont",      UARCH_SILVERMONT,       22) // no spec update; only MSR_CPUID_table* so far
-  CHECK_UARCH(arch, 0,  6,  5, 12, NA, "Goldmont",        UARCH_GOLDMONT,         14)
-  CHECK_UARCH(arch, 0,  6,  5, 13, NA, "Silvermont",      UARCH_SILVERMONT,       22) // no spec update; only MSR_CPUID_table* so far
-  CHECK_UARCH(arch, 0,  6,  5, 14,  8, "Kaby Lake",       UARCH_KABY_LAKE,        14)
-  CHECK_UARCH(arch, 0,  6,  5, 14, NA, "Skylake",         UARCH_SKYLAKE,          14)
-  CHECK_UARCH(arch, 0,  6,  5, 15, NA, "Goldmont",        UARCH_GOLDMONT,         14)
-  CHECK_UARCH(arch, 0,  6,  6,  6, NA, "Palm Cove",       UARCH_PALM_COVE,        10) // no spec update; only MSR_CPUID_table* so far
-  CHECK_UARCH(arch, 0,  6,  6, 10, NA, "Sunny Cove",      UARCH_SUNNY_COVE,       10) // no spec update; only MSR_CPUID_table* so far
-  CHECK_UARCH(arch, 0,  6,  6, 12, NA, "Sunny Cove",      UARCH_SUNNY_COVE,       10) // no spec update; only MSR_CPUID_table* so far
-  CHECK_UARCH(arch, 0,  6,  7,  5, NA, "Airmont",         UARCH_AIRMONT,          14) // no spec update; whispers & rumors
-  CHECK_UARCH(arch, 0,  6,  7, 10, NA, "Goldmont Plus",   UARCH_GOLDMONT_PLUS,    14)
-  CHECK_UARCH(arch, 0,  6,  7, 13, NA, "Sunny Cove",      UARCH_SUNNY_COVE,       10) // no spec update; only MSR_CPUID_table* so far
-  CHECK_UARCH(arch, 0,  6,  7, 14, NA, "Ice Lake",        UARCH_ICE_LAKE,         10)
-  CHECK_UARCH(arch, 0,  6,  8,  5, NA, "Knights Mill",    UARCH_KNIGHTS_MILL,     14) // no spec update; only MSR_CPUID_table* so far
-  CHECK_UARCH(arch, 0,  6,  8,  6, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
-  CHECK_UARCH(arch, 0,  6,  8, 10, NA, "Tremont",         UARCH_TREMONT,          10) // no spec update; only geekbench.com example
-  CHECK_UARCH(arch, 0,  6,  8, 12, NA, "Tiger Lake",      UARCH_TIGER_LAKE,       10) // instlatx64
-  CHECK_UARCH(arch, 0,  6,  8, 13, NA, "Tiger Lake",      UARCH_TIGER_LAKE,       10) // instlatx64
+  CHECK_UARCH(arch, 0,  5,  0,  0, NA, "P5",                UARCH_P5,              800)
+  CHECK_UARCH(arch, 0,  5,  0,  1, NA, "P5",                UARCH_P5,              800)
+  CHECK_UARCH(arch, 0,  5,  0,  2, NA, "P5",                UARCH_P5,              UNK)
+  CHECK_UARCH(arch, 0,  5,  0,  3, NA, "P5",                UARCH_P5,              600)
+  CHECK_UARCH(arch, 0,  5,  0,  4, NA, "P5 (MMX)",          UARCH_P5_MMX,          UNK)
+  CHECK_UARCH(arch, 0,  5,  0,  7, NA, "P5 (MMX)",          UARCH_P5_MMX,          UNK)
+  CHECK_UARCH(arch, 0,  5,  0,  8, NA, "P5 (MMX)",          UARCH_P5_MMX,          250)
+  CHECK_UARCH(arch, 0,  5,  0,  9,  0, "Lakemont",          UARCH_LAKEMONT,         32)
+  CHECK_UARCH(arch, 0,  5,  0,  9, NA, "P5 (MMX)",          UARCH_P5_MMX,          UNK)
+  CHECK_UARCH(arch, 0,  5,  0, 10,  0, "Lakemont",          UARCH_LAKEMONT,         32)
+  CHECK_UARCH(arch, 0,  6,  0,  0, NA, "P6 (Pentium II)",   UARCH_P6_PENTIUM_II,   UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  1, NA, "P6 (Pentium II)",   UARCH_P6_PENTIUM_II,   UNK) // process depends on core
+  CHECK_UARCH(arch, 0,  6,  0,  2, NA, "P6 (Pentium II)",   UARCH_P6_PENTIUM_II,   UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  3, NA, "P6 (Klamath)",      UARCH_P6_PENTIUM_II,   350) // http://instlatx64.atw.hu.
+  CHECK_UARCH(arch, 0,  6,  0,  4, NA, "P6 (Pentium II)",   UARCH_P6_PENTIUM_II,   UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  5, NA, "P6 (Deschutes)",    UARCH_P6_PENTIUM_II,   250) // http://instlatx64.atw.hu.
+  CHECK_UARCH(arch, 0,  6,  0,  6, NA, "P6 (Dixon)",        UARCH_P6_PENTIUM_II,   UNK) // http://instlatx64.atw.hu.
+  CHECK_UARCH(arch, 0,  6,  0,  7, NA, "P6 (Katmai)",       UARCH_P6_PENTIUM_III,  250) // Core names from: https://en.wikichip.org/wiki/intel/cpuid. NOTE: Xeon core names are different! https://www.techpowerup.com/cpu-specs/?generation=Intel+Pentium+III+Xeon
+  CHECK_UARCH(arch, 0,  6,  0,  8, NA, "P6 (Coppermine)",   UARCH_P6_PENTIUM_III,  180) // Also: https://en.wikipedia.org/wiki/Pentium_III
+  CHECK_UARCH(arch, 0,  6,  0,  9, NA, "P6 (Pentium M)",    UARCH_P6_PENTIUM_III,  130)
+  CHECK_UARCH(arch, 0,  6,  0, 10, NA, "P6 (Coppermine T)", UARCH_P6_PENTIUM_III,  180)
+  CHECK_UARCH(arch, 0,  6,  0, 11, NA, "P6 (Tualatin)",     UARCH_P6_PENTIUM_III,  130)
+  CHECK_UARCH(arch, 0,  6,  0, 13, NA, "Dothan",            UARCH_DOTHAN,          UNK)  // process depends on core
+  CHECK_UARCH(arch, 0,  6,  0, 14, NA, "Yonah",             UARCH_YONAH,            65)
+  CHECK_UARCH(arch, 0,  6,  0, 15, NA, "Merom",             UARCH_MEROM,            65)
+  CHECK_UARCH(arch, 0,  6,  1,  5, NA, "Dothan",            UARCH_DOTHAN,           90)
+  CHECK_UARCH(arch, 0,  6,  1,  6, NA, "Merom",             UARCH_MEROM,            65)
+  CHECK_UARCH(arch, 0,  6,  1,  7, NA, "Penryn",            UARCH_PENYR,            45)
+  CHECK_UARCH(arch, 0,  6,  1, 10, NA, "Nehalem",           UARCH_NEHALEM,          45)
+  CHECK_UARCH(arch, 0,  6,  1, 12, NA, "Bonnell",           UARCH_BONNELL,          45)
+  CHECK_UARCH(arch, 0,  6,  1, 13, NA, "Penryn",            UARCH_PENYR,            45)
+  CHECK_UARCH(arch, 0,  6,  1, 14, NA, "Nehalem",           UARCH_NEHALEM,          45)
+  CHECK_UARCH(arch, 0,  6,  1, 15, NA, "Nehalem",           UARCH_NEHALEM,          45)
+  CHECK_UARCH(arch, 0,  6,  2,  5, NA, "Westmere",          UARCH_WESTMERE,         32)
+  CHECK_UARCH(arch, 0,  6,  2 , 6, NA, "Bonnell",           UARCH_BONNELL,          45)
+  CHECK_UARCH(arch, 0,  6,  2,  7, NA, "Saltwell",          UARCH_SALTWELL,         32)
+  CHECK_UARCH(arch, 0,  6,  2, 10, NA, "Sandy Bridge",      UARCH_SANDY_BRIDGE,     32)
+  CHECK_UARCH(arch, 0,  6,  2, 12, NA, "Westmere",          UARCH_WESTMERE,         32)
+  CHECK_UARCH(arch, 0,  6,  2, 13, NA, "Sandy Bridge",      UARCH_SANDY_BRIDGE,     32)
+  CHECK_UARCH(arch, 0,  6,  2, 14, NA, "Nehalem",           UARCH_NEHALEM,          45)
+  CHECK_UARCH(arch, 0,  6,  2, 15, NA, "Westmere",          UARCH_WESTMERE,         32)
+  CHECK_UARCH(arch, 0,  6,  3,  5, NA, "Saltwell",          UARCH_SALTWELL,         14)
+  CHECK_UARCH(arch, 0,  6,  3,  6, NA, "Saltwell",          UARCH_SALTWELL,         32)
+  CHECK_UARCH(arch, 0,  6,  3,  7, NA, "Silvermont",        UARCH_SILVERMONT,       22)
+  CHECK_UARCH(arch, 0,  6,  3, 10, NA, "Ivy Bridge",        UARCH_IVY_BRIDGE,       22)
+  CHECK_UARCH(arch, 0,  6,  3, 12, NA, "Haswell",           UARCH_HASWELL,          22)
+  CHECK_UARCH(arch, 0,  6,  3, 13, NA, "Broadwell",         UARCH_BROADWELL,        14)
+  CHECK_UARCH(arch, 0,  6,  3, 14, NA, "Ivy Bridge",        UARCH_IVY_BRIDGE,       22)
+  CHECK_UARCH(arch, 0,  6,  3, 15, NA, "Haswell",           UARCH_HASWELL,          22)
+  CHECK_UARCH(arch, 0,  6,  4,  5, NA, "Haswell",           UARCH_HASWELL,          22)
+  CHECK_UARCH(arch, 0,  6,  4,  6, NA, "Haswell",           UARCH_HASWELL,          22)
+  CHECK_UARCH(arch, 0,  6,  4,  7, NA, "Broadwell",         UARCH_BROADWELL,        14)
+  CHECK_UARCH(arch, 0,  6,  4, 10, NA, "Silvermont",        UARCH_SILVERMONT,       22) // no docs, but /proc/cpuinfo seen in wild
+  CHECK_UARCH(arch, 0,  6,  4, 12, NA, "Airmont",           UARCH_AIRMONT,          14)
+  CHECK_UARCH(arch, 0,  6,  4, 13, NA, "Silvermont",        UARCH_SILVERMONT,       22)
+  CHECK_UARCH(arch, 0,  6,  4, 14,  8, "Kaby Lake",         UARCH_KABY_LAKE,        14)
+  CHECK_UARCH(arch, 0,  6,  4, 14, NA, "Skylake",           UARCH_SKYLAKE,          14)
+  CHECK_UARCH(arch, 0,  6,  4, 15, NA, "Broadwell",         UARCH_BROADWELL,        14)
+  CHECK_UARCH(arch, 0,  6,  5,  5,  6, "Cascade Lake",      UARCH_CASCADE_LAKE,     14) // no docs, but example from Greg Stewart
+  CHECK_UARCH(arch, 0,  6,  5,  5,  7, "Cascade Lake",      UARCH_CASCADE_LAKE,     14)
+  CHECK_UARCH(arch, 0,  6,  5,  5, 10, "Cooper Lake",       UARCH_COOPER_LAKE,      14)
+  CHECK_UARCH(arch, 0,  6,  5,  5, NA, "Skylake",           UARCH_SKYLAKE,          14)
+  CHECK_UARCH(arch, 0,  6,  5,  6, NA, "Broadwell",         UARCH_BROADWELL,        14)
+  CHECK_UARCH(arch, 0,  6,  5,  7, NA, "Knights Landing",   UARCH_KNIGHTS_LANDING,  14)
+  CHECK_UARCH(arch, 0,  6,  5, 10, NA, "Silvermont",        UARCH_SILVERMONT,       22) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  5, 12, NA, "Goldmont",          UARCH_GOLDMONT,         14)
+  CHECK_UARCH(arch, 0,  6,  5, 13, NA, "Silvermont",        UARCH_SILVERMONT,       22) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  5, 14,  8, "Kaby Lake",         UARCH_KABY_LAKE,        14)
+  CHECK_UARCH(arch, 0,  6,  5, 14, NA, "Skylake",           UARCH_SKYLAKE,          14)
+  CHECK_UARCH(arch, 0,  6,  5, 15, NA, "Goldmont",          UARCH_GOLDMONT,         14)
+  CHECK_UARCH(arch, 0,  6,  6,  6, NA, "Palm Cove",         UARCH_PALM_COVE,        10) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  6, 10, NA, "Sunny Cove",        UARCH_SUNNY_COVE,       10) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  6, 12, NA, "Sunny Cove",        UARCH_SUNNY_COVE,       10) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  7,  5, NA, "Airmont",           UARCH_AIRMONT,          14) // no spec update; whispers & rumors
+  CHECK_UARCH(arch, 0,  6,  7, 10, NA, "Goldmont Plus",     UARCH_GOLDMONT_PLUS,    14)
+  CHECK_UARCH(arch, 0,  6,  7, 13, NA, "Sunny Cove",        UARCH_SUNNY_COVE,       10) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  7, 14, NA, "Ice Lake",          UARCH_ICE_LAKE,         10)
+  CHECK_UARCH(arch, 0,  6,  8,  5, NA, "Knights Mill",      UARCH_KNIGHTS_MILL,     14) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  8,  6, NA, "Tremont",           UARCH_TREMONT,          10) // LX*
+  CHECK_UARCH(arch, 0,  6,  8, 10, NA, "Tremont",           UARCH_TREMONT,          10) // no spec update; only geekbench.com example
+  CHECK_UARCH(arch, 0,  6,  8, 12, NA, "Tiger Lake",        UARCH_TIGER_LAKE,       10) // instlatx64
+  CHECK_UARCH(arch, 0,  6,  8, 13, NA, "Tiger Lake",        UARCH_TIGER_LAKE,       10) // instlatx64
   // CHECK_UARCH(arch, 0,  6,  8, 14,  9, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
   // CHECK_UARCH(arch, 0,  6,  8, 14, 10, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake R or Coffee Lake U)
-  CHECK_UARCH(arch, 0,  6,  8, 14, 11, "Whiskey Lake",    UARCH_WHISKEY_LAKE,     14) // wikichip
-  CHECK_UARCH(arch, 0,  6,  8, 14, 12, "Comet Lake",      UARCH_COMET_LAKE,       14) // wikichip
-  CHECK_UARCH(arch, 0,  6,  9,  6, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
-  CHECK_UARCH(arch, 0,  6,  9,  7, NA, "Alder Lake",      UARCH_ALDER_LAKE,       10) // instlatx64 (Alder Lake-S)
-  CHECK_UARCH(arch, 0,  6,  9, 10, NA, "Alder Lake",      UARCH_ALDER_LAKE,       10) // instlatx64 (Alder Lake-P)
-  CHECK_UARCH(arch, 0,  6,  9, 12, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
-  CHECK_UARCH(arch, 0,  6,  9, 13, NA, "Sunny Cove",      UARCH_SUNNY_COVE,       10) // LX*
-  CHECK_UARCH(arch, 0,  6,  9, 14,  9, "Kaby Lake",       UARCH_KABY_LAKE,        14)
-  CHECK_UARCH(arch, 0,  6,  9, 14, 10, "Coffee Lake",     UARCH_COFFEE_LAKE,      14)
-  CHECK_UARCH(arch, 0,  6,  9, 14, 11, "Coffee Lake",     UARCH_COFFEE_LAKE,      14)
-  CHECK_UARCH(arch, 0,  6,  9, 14, 12, "Coffee Lake",     UARCH_COFFEE_LAKE,      14)
-  CHECK_UARCH(arch, 0,  6,  9, 14, 13, "Coffee Lake",     UARCH_COFFEE_LAKE,      14)
-  CHECK_UARCH(arch, 0,  6, 10,  5, NA, "Comet Lake",      UARCH_COMET_LAKE,       14) // wikichip
-  CHECK_UARCH(arch, 0,  6, 10,  6, NA, "Comet Lake",      UARCH_COMET_LAKE,       14) // instlatx64.atw.hu (i7-10710U)
-  CHECK_UARCH(arch, 0,  6, 10,  7, NA, "Rocket Lake",     UARCH_ROCKET_LAKE,      14) // instlatx64.atw.hu (i7-11700K)
-  CHECK_UARCH(arch, 0,  6, 11,  7, NA, "Raptor Lake",     UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i5-13600K)
-  CHECK_UARCH(arch, 0,  6, 11, 10, NA, "Raptor Lake",     UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i7-1370P)
-  CHECK_UARCH(arch, 0,  6, 11, 14, NA, "Alder Lake",      UARCH_ALDER_LAKE,       10) // instlatx64.atw.hu (Alder Lake-N)
-  CHECK_UARCH(arch, 0,  6, 11, 15, NA, "Raptor Lake",     UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i5-13500)
-  CHECK_UARCH(arch, 0, 11,  0,  0, NA, "Knights Ferry",   UARCH_KNIGHTS_FERRY,    45) // found only on en.wikichip.org
-  CHECK_UARCH(arch, 0, 11,  0,  1, NA, "Knights Corner",  UARCH_KNIGHTS_CORNER,   22)
-  CHECK_UARCH(arch, 0, 15,  0,  0, NA, "Willamette",      UARCH_WILLAMETTE,      180)
-  CHECK_UARCH(arch, 0, 15,  0,  1, NA, "Willamette",      UARCH_WILLAMETTE,      180)
-  CHECK_UARCH(arch, 0, 15,  0,  2, NA, "Northwood",       UARCH_NORTHWOOD,       130)
-  CHECK_UARCH(arch, 0, 15,  0,  3, NA, "Prescott",        UARCH_PRESCOTT,         90)
-  CHECK_UARCH(arch, 0, 15,  0,  4, NA, "Prescott",        UARCH_PRESCOTT,         90)
-  CHECK_UARCH(arch, 0, 15,  0,  6, NA, "Cedar Mill",      UARCH_CEDAR_MILL,       65)
-  CHECK_UARCH(arch, 1, 15,  0,  0, NA, "Itanium2",        UARCH_ITANIUM2,        180)
-  CHECK_UARCH(arch, 1, 15,  0,  1, NA, "Itanium2",        UARCH_ITANIUM2,        130)
-  CHECK_UARCH(arch, 1, 15,  0,  2, NA, "Itanium2",        UARCH_ITANIUM2,        130)
+  CHECK_UARCH(arch, 0,  6,  8, 14, 11, "Whiskey Lake",      UARCH_WHISKEY_LAKE,     14) // wikichip
+  CHECK_UARCH(arch, 0,  6,  8, 14, 12, "Comet Lake",        UARCH_COMET_LAKE,       14) // wikichip
+  CHECK_UARCH(arch, 0,  6,  9,  6, NA, "Tremont",           UARCH_TREMONT,          10) // LX*
+  CHECK_UARCH(arch, 0,  6,  9,  7, NA, "Alder Lake",        UARCH_ALDER_LAKE,       10) // instlatx64 (Alder Lake-S)
+  CHECK_UARCH(arch, 0,  6,  9, 10, NA, "Alder Lake",        UARCH_ALDER_LAKE,       10) // instlatx64 (Alder Lake-P)
+  CHECK_UARCH(arch, 0,  6,  9, 12, NA, "Tremont",           UARCH_TREMONT,          10) // LX*
+  CHECK_UARCH(arch, 0,  6,  9, 13, NA, "Sunny Cove",        UARCH_SUNNY_COVE,       10) // LX*
+  CHECK_UARCH(arch, 0,  6,  9, 14,  9, "Kaby Lake",         UARCH_KABY_LAKE,        14)
+  CHECK_UARCH(arch, 0,  6,  9, 14, 10, "Coffee Lake",       UARCH_COFFEE_LAKE,      14)
+  CHECK_UARCH(arch, 0,  6,  9, 14, 11, "Coffee Lake",       UARCH_COFFEE_LAKE,      14)
+  CHECK_UARCH(arch, 0,  6,  9, 14, 12, "Coffee Lake",       UARCH_COFFEE_LAKE,      14)
+  CHECK_UARCH(arch, 0,  6,  9, 14, 13, "Coffee Lake",       UARCH_COFFEE_LAKE,      14)
+  CHECK_UARCH(arch, 0,  6, 10,  5, NA, "Comet Lake",        UARCH_COMET_LAKE,       14) // wikichip
+  CHECK_UARCH(arch, 0,  6, 10,  6, NA, "Comet Lake",        UARCH_COMET_LAKE,       14) // instlatx64.atw.hu (i7-10710U)
+  CHECK_UARCH(arch, 0,  6, 10,  7, NA, "Rocket Lake",       UARCH_ROCKET_LAKE,      14) // instlatx64.atw.hu (i7-11700K)
+  CHECK_UARCH(arch, 0,  6, 11,  7, NA, "Raptor Lake",       UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i5-13600K)
+  CHECK_UARCH(arch, 0,  6, 11, 10, NA, "Raptor Lake",       UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i7-1370P)
+  CHECK_UARCH(arch, 0,  6, 11, 14, NA, "Alder Lake",        UARCH_ALDER_LAKE,       10) // instlatx64.atw.hu (Alder Lake-N)
+  CHECK_UARCH(arch, 0,  6, 11, 15, NA, "Raptor Lake",       UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i5-13500)
+  CHECK_UARCH(arch, 0, 11,  0,  0, NA, "Knights Ferry",     UARCH_KNIGHTS_FERRY,    45) // found only on en.wikichip.org
+  CHECK_UARCH(arch, 0, 11,  0,  1, NA, "Knights Corner",    UARCH_KNIGHTS_CORNER,   22)
+  CHECK_UARCH(arch, 0, 15,  0,  0, NA, "Willamette",        UARCH_WILLAMETTE,      180)
+  CHECK_UARCH(arch, 0, 15,  0,  1, NA, "Willamette",        UARCH_WILLAMETTE,      180)
+  CHECK_UARCH(arch, 0, 15,  0,  2, NA, "Northwood",         UARCH_NORTHWOOD,       130)
+  CHECK_UARCH(arch, 0, 15,  0,  3, NA, "Prescott",          UARCH_PRESCOTT,         90)
+  CHECK_UARCH(arch, 0, 15,  0,  4, NA, "Prescott",          UARCH_PRESCOTT,         90)
+  CHECK_UARCH(arch, 0, 15,  0,  6, NA, "Cedar Mill",        UARCH_CEDAR_MILL,       65)
+  CHECK_UARCH(arch, 1, 15,  0,  0, NA, "Itanium2",          UARCH_ITANIUM2,        180)
+  CHECK_UARCH(arch, 1, 15,  0,  1, NA, "Itanium2",          UARCH_ITANIUM2,        130)
+  CHECK_UARCH(arch, 1, 15,  0,  2, NA, "Itanium2",          UARCH_ITANIUM2,        130)
   UARCH_END
   return arch;
 }
@@ -381,6 +382,7 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
   CHECK_UARCH(arch, 10, 15,  5,  0, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
   CHECK_UARCH(arch, 10, 15,  6,  1,  2, "Zen 4",       UARCH_ZEN4,         5) // instlatx64
   CHECK_UARCH(arch, 10, 15,  7,  4,  1, "Zen 4",       UARCH_ZEN4,         4) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  7,  5,  2, "Zen 4",       UARCH_ZEN4,         4) // instlatx64
   CHECK_UARCH(arch, 10, 15,  7,  8,  0, "Zen 4",       UARCH_ZEN4,         4) // instlatx64
   CHECK_UARCH(arch, 10, 15,  8, NA, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64 (AMD MI300C)
   CHECK_UARCH(arch, 10, 15,  9, NA, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64 (AMD MI300A)
@@ -392,11 +394,16 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
 
 struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
   if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
+    struct uarch* arch = emalloc(sizeof(struct uarch));
     if(dump == 0x000806E9) {
+      if (cpu->cpu_name == NULL) {
+        printErr("Unable to find uarch without CPU name");
+        fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK);
+        return arch;
+      }
+
       // It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
       // See issue https://github.com/Dr-Noob/cpufetch/issues/122
-      struct uarch* arch = emalloc(sizeof(struct uarch));
-
       if(strstr(cpu->cpu_name, "Y") != NULL) {
         fill_uarch(arch, "Amber Lake", UARCH_AMBER_LAKE, 14);
       }
@@ -407,10 +414,14 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
       return arch;
     }
     else if (dump == 0x000806EA) {
+      if (cpu->cpu_name == NULL) {
+        printErr("Unable to find uarch without CPU name");
+        fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK);
+        return arch;
+      }
+
       // It is not possible to determine uarch only from CPUID dump (can be Kaby Lake R or Coffee Lake U)
       // See issue https://github.com/Dr-Noob/cpufetch/issues/149
-      struct uarch* arch = emalloc(sizeof(struct uarch));
-
       if(strstr(cpu->cpu_name, "i5-8250U") != NULL ||
          strstr(cpu->cpu_name, "i5-8350U") != NULL ||
          strstr(cpu->cpu_name, "i7-8550U") != NULL ||
@@ -429,6 +440,41 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
     return get_uarch_from_cpuid_amd(ef, f, em, m, s);
 }
 
+// If we cannot get the CPU name from CPUID, try to infer it from uarch
+char* infer_cpu_name_from_uarch(struct uarch* arch) {
+  char* cpu_name = NULL;
+  if (arch == NULL) {
+    printErr("infer_cpu_name_from_uarch: Unable to find CPU name");
+    cpu_name = ecalloc(strlen(STRING_UNKNOWN) + 1, sizeof(char));
+    strcpy(cpu_name, STRING_UNKNOWN);
+    return cpu_name;
+  }
+
+  char *str = NULL;
+
+  if (arch->uarch == UARCH_P5)
+    str = "Intel Pentium";
+  else if (arch->uarch == UARCH_P5_MMX)
+    str = "Intel Pentium MMX";
+  else if (arch->uarch == UARCH_P6_PENTIUM_II)
+    str = "Intel Pentium II";
+  else if (arch->uarch == UARCH_P6_PENTIUM_III)
+    str = "Intel Pentium III";
+  else
+    printErr("Unable to find name from uarch: %d", arch->uarch);
+
+  if (str == NULL) {
+    cpu_name = ecalloc(strlen(STRING_UNKNOWN) + 1, sizeof(char));
+    strcpy(cpu_name, STRING_UNKNOWN);
+  }
+  else {
+    cpu_name = ecalloc(strlen(str) + 1, sizeof(char));
+    strcpy(cpu_name, str);
+  }
+
+  return cpu_name;
+}
+
 bool vpus_are_AVX512(struct cpuInfo* cpu) {
   return cpu->arch->uarch != UARCH_ICE_LAKE &&
          cpu->arch->uarch != UARCH_TIGER_LAKE &&
@@ -499,9 +545,6 @@ char* get_str_process(struct cpuInfo* cpu) {
   if(process == UNK) {
     snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
   }
-  else if(process > 100) {
-    sprintf(str, "%.2fum", (double)process/100);
-  }
   else if(process > 0){
     sprintf(str, "%dnm", process);
   }

src/x86/uarch.h

@@ -8,6 +8,7 @@
 struct uarch;
 
 struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s);
+char* infer_cpu_name_from_uarch(struct uarch* arch);
 bool vpus_are_AVX512(struct cpuInfo* cpu);
 bool is_knights_landing(struct cpuInfo* cpu);
 int get_number_of_vpus(struct cpuInfo* cpu);