[v1.05][X86] Fix for Meteor Lake (#255)

- Use udev to get topo when apic failed or is not available.
- Assume single core in udev when total cores is 1.
- Print core/cores accordingly to the number of cores.

README.md

@@ -175,6 +175,7 @@ Thanks to the fellow contributors and interested people in the project. Special
 - [mdoksa76](https://github.com/mdoksa76) and [exkc](https://github.com/exkc): Excellent ideas and feedback for supporting Allwinner SoCs.
 - [Sakura286](https://github.com/Sakura286), [exkc](https://github.com/exkc) and [Patola](https://github.com/Patola): Helped with RISC-V port with ssh access, ideas, testing, etc.
 - [ThomasKaiser](https://github.com/ThomasKaiser): Very valuable feedback on improving ARM SoC detection (Apple, Allwinner, Rockchip).
+- [zerkerX](https://github.com/zerkerX): Helped with feedback for supporting old (e.g., Pentium III) Intel CPUs.
 
 ## 8. cpufetch for GPUs (gpufetch)
 See [gpufetch](https://github.com/Dr-Noob/gpufetch) project!

src/arm/soc.c

@@ -578,6 +578,14 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "SM8250-AB",      "865+",      SOC_SNAPD_SM8250_AB,      soc,  7)
   SOC_EQ(tmp, "SM8350",         "888",       SOC_SNAPD_SM8350,         soc,  5)
   SOC_EQ(tmp, "SM8350-AC",      "888+",      SOC_SNAPD_SM8350,         soc,  5)
+  // Snapdragon Gen //
+  SOC_EQ(tmp, "SM4450",         "4 Gen 2",   SOC_SNAPD_SM4450,         soc,  4)
+  SOC_EQ(tmp, "SM6450",         "6 Gen 1",   SOC_SNAPD_SM6450,         soc,  4)
+  SOC_EQ(tmp, "SM7435-AB",      "7s Gen 2",  SOC_SNAPD_SM7435_AB,      soc,  4)
+  SOC_EQ(tmp, "SM7450",         "7 Gen 1",   SOC_SNAPD_SM7450,         soc,  4)
+  SOC_EQ(tmp, "SM7475",         "7+ Gen 2",  SOC_SNAPD_SM7475,         soc,  4)
+  SOC_EQ(tmp, "SM8450",         "8 Gen 1",   SOC_SNAPD_SM8450,         soc,  4)
+  SOC_EQ(tmp, "SM8475",         "8+ Gen 1",  SOC_SNAPD_SM8475,         soc,  4)
   SOC_END
 }
 
@@ -624,12 +632,37 @@ bool match_special(char* soc_name, struct system_on_chip* soc) {
     return true;
   }
 
-  // Snapdragon 8 Gen 1 reported as "taro"
+  // New Snapdragon SoCs codenames
+  // https://github.com/sm8450-mainline/fdt?tab=readme-ov-file#chipsets
+  // https://github.com/Dr-Noob/cpufetch/issues/253
+  if (strcmp(soc_name, "cape") == 0) {
+    fill_soc(soc, "8+ Gen 1", SOC_SNAPD_SM8475, 4);
+    return true;
+  }
+
   if(strcmp(soc_name, "taro") == 0) {
     fill_soc(soc, "8 Gen 1", SOC_SNAPD_SM8450, 4);
     return true;
   }
 
+  if(strcmp(soc_name, "ukee") == 0) {
+    fill_soc(soc, "7+ Gen 2", SOC_SNAPD_SM7475, 4);
+    return true;
+  }
+
+  if(strcmp(soc_name, "diwali") == 0) {
+    fill_soc(soc, "7 Gen 1", SOC_SNAPD_SM7450, 4);
+    return true;
+  }
+
+  // parrot can be either SM7435 or SM6450, we need more data
+  // to distingish between those two
+
+  if(strcmp(soc_name, "ravelin") == 0) {
+    fill_soc(soc, "4 Gen 2", SOC_SNAPD_SM4450, 4);
+    return true;
+  }
+
   // Google Pixel 6
   // https://github.com/Dr-Noob/cpufetch/issues/134
   if(strcmp(soc_name, "oriole") == 0) {
@@ -702,6 +735,16 @@ struct system_on_chip* guess_soc_from_android(struct system_on_chip* soc) {
     else return soc;
   }
 
+  // https://github.com/Dr-Noob/cpufetch/issues/253
+  // ro.soc.model might be more reliable than ro.product.board or
+  // ro.board.platform, so try with it first
+  property_len = android_property_get("ro.soc.model", (char *) &tmp);
+  if(property_len > 0) {
+    try_parse_soc_from_string(soc, property_len, tmp);
+    if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) printWarn("SoC detection failed using Android property ro.soc.model: %s", tmp);
+    else return soc;
+  }
+
   property_len = android_property_get("ro.product.board", (char *) &tmp);
   if(property_len > 0) {
     try_parse_soc_from_string(soc, property_len, tmp);

src/arm/socs.h

@@ -270,11 +270,13 @@ enum {
   SOC_SNAPD_SDM660,
   SOC_SNAPD_SM6115,
   SOC_SNAPD_SM6125,
+  SOC_SNAPD_SM6450,
   SOC_SNAPD_SDM670,
   SOC_SNAPD_SM6150,
   SOC_SNAPD_SM6350,
   SOC_SNAPD_SDM710,
   SOC_SNAPD_SDM712,
+  SOC_SNAPD_SM4450,
   SOC_SNAPD_SM7125,
   SOC_SNAPD_SM7150_AA,
   SOC_SNAPD_SM7150_AB,
@@ -283,6 +285,9 @@ enum {
   SOC_SNAPD_SM7250_AA,
   SOC_SNAPD_SM7250_AB,
   SOC_SNAPD_SM7250_AC,
+  SOC_SNAPD_SM7435_AB,
+  SOC_SNAPD_SM7450,
+  SOC_SNAPD_SM7475,
   SOC_SNAPD_MSM8974AA,
   SOC_SNAPD_MSM8974AB,
   SOC_SNAPD_MSM8974AC,
@@ -303,6 +308,7 @@ enum {
   SOC_SNAPD_SM8250_AB,
   SOC_SNAPD_SM8350,
   SOC_SNAPD_SM8450,
+  SOC_SNAPD_SM8475,
   // APPLE
   SOC_APPLE_M1,
   SOC_APPLE_M1_PRO,
@@ -375,7 +381,7 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
   else if(soc >= SOC_KUNPENG_920 && soc <= SOC_KUNPENG_930) return SOC_VENDOR_KUNPENG;
   else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
   else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
-  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8450) return SOC_VENDOR_SNAPDRAGON;
+  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8475) return SOC_VENDOR_SNAPDRAGON;
   else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE;
   else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
   else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP;

src/common/cpu.h

@@ -45,8 +45,9 @@ enum {
 };
 
 enum {
-  CORE_TYPE_EFFICIENCY,
   CORE_TYPE_PERFORMANCE,
+  CORE_TYPE_EFFICIENCY,
+  CORE_TYPE_LP_EFFICIENCY,
   CORE_TYPE_UNKNOWN
 };
 

src/common/printer.c

@@ -614,8 +614,9 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     }
 
     if(hybrid_architecture) {
-      if(ptr->core_type == CORE_TYPE_EFFICIENCY) sprintf(cpu_num, "E-cores:");
-      else if(ptr->core_type == CORE_TYPE_PERFORMANCE) sprintf(cpu_num, "P-cores:");
+      if (ptr->core_type == CORE_TYPE_PERFORMANCE) sprintf(cpu_num, "P-cores:");
+      else if (ptr->core_type == CORE_TYPE_EFFICIENCY) sprintf(cpu_num, "E-cores:");
+      else if (ptr->core_type == CORE_TYPE_LP_EFFICIENCY) sprintf(cpu_num, "LP-E-cores:");
       else printBug("Found invalid core type!\n");
 
       setAttribute(art, ATTRIBUTE_CPU_NUM, cpu_num);

src/x86/apic.c

@@ -91,6 +91,7 @@ int get_total_cores_module(int total_cores, int module) {
 
   while(!end) {
     if(!bind_to_cpu(i)) {
+      printBug("get_total_cores_module: Cannot bind to core %d", i);
       return -1;
     }
     uint32_t eax = 0x0000001A;
@@ -99,6 +100,17 @@ int get_total_cores_module(int total_cores, int module) {
     uint32_t edx = 0;
     cpuid(&eax, &ebx, &ecx, &edx);
     int32_t core_type = eax >> 24 & 0xFF;
+
+    // Here we artificially create a new core type for
+    // LP-E cores. In case the core has no L3 (on a hybrid)
+    // architecture, then we now it's an LP-E core.
+    eax = 0x4;
+    ebx = 0;
+    ecx = 0x3;
+    edx = 0;
+    cpuid(&eax, &ebx, &ecx, &edx);
+    core_type += eax == 0;
+
     bool found = false;
 
     for(int j=0; j < total_modules && !found; j++) {

src/x86/cpuid.c

@@ -137,39 +137,31 @@ bool abbreviate_intel_cpu_name(char** name) {
   char* new_name_ptr = new_name;
   char* aux_ptr = NULL;
 
-  // 1. Remove "(R)"
+  // 1. Find "Intel(R)"
   old_name_ptr = strstr(old_name_ptr, "Intel(R)");
   if(old_name_ptr == NULL) return false;
-  strcpy(new_name_ptr, "Intel");
-  new_name_ptr += strlen("Intel");
-  old_name_ptr += strlen("Intel(R)");
 
-  // 2. Remove "(R)" or "(TM)"
-  aux_ptr = strstr(old_name_ptr, "(");
-  if(aux_ptr == NULL) return false;
-  strncpy(new_name_ptr, old_name_ptr, aux_ptr-old_name_ptr);
-
-  new_name_ptr += aux_ptr-old_name_ptr;
-  strcpy(new_name_ptr, " ");
-  new_name_ptr++;
-  old_name_ptr = strstr(aux_ptr, ")");
-  if(old_name_ptr == NULL) return false;
-  old_name_ptr++;
-  while(*old_name_ptr == ' ') old_name_ptr++;
-
-  // 3. Copy the CPU name
+  // 2. Search for "@"
   aux_ptr = strstr(old_name_ptr, "@");
-  if(aux_ptr == NULL) return false;
-  strncpy(new_name_ptr, old_name_ptr, (aux_ptr-1)-old_name_ptr);
+  if(aux_ptr == NULL) {
+    // New CPUs, copy end ptr is end of string
+    aux_ptr = old_name + strlen(old_name);
+    strncpy(new_name_ptr, old_name_ptr, (aux_ptr)-old_name_ptr);
+  }
+  else {
+    // Copy end ptr is "@"
+    strncpy(new_name_ptr, old_name_ptr, (aux_ptr-1)-old_name_ptr);
+  }
 
-  // 4. Remove dummy strings in Intel CPU names
+  // 3. Remove dummy strings in Intel CPU names
+  strremove(new_name, "(R)");
+  strremove(new_name, "(TM)");
   strremove(new_name, " CPU");
   strremove(new_name, " Dual");
   strremove(new_name, " 0");
 
   free(old_name);
   *name = new_name;
-
   return true;
 }
 
@@ -397,6 +389,17 @@ bool set_cpu_module(int m, int total_modules, int32_t* first_core) {
       uint32_t edx = 0;
       cpuid(&eax, &ebx, &ecx, &edx);
       int32_t core_type = eax >> 24 & 0xFF;
+
+      // Here we artificially create a new core type for
+      // LP-E cores. In case the core has no L3 (on a hybrid)
+      // architecture, then we now it's an LP-E core.
+      eax = 0x4;
+      ebx = 0;
+      ecx = 0x3;
+      edx = 0;
+      cpuid(&eax, &ebx, &ecx, &edx);
+      core_type += eax == 0;
+
       bool found = false;
 
       for(int j=0; j < total_modules && !found; j++) {
@@ -423,13 +426,19 @@ bool set_cpu_module(int m, int total_modules, int32_t* first_core) {
     #endif
   }
   else {
-    // This is a normal architecture
+    // This is a non-hybrid architecture
     *first_core = 0;
   }
 
   return true;
 }
 
+// Difference between E and LP-E cores:
+// According to Intel Core Ultra Processor Datasheet Volume 1 of 2
+// (https://www.intel.com/content/www/us/en/content-details/792044/intel-core-ultra-processor-datasheet-volume-1-of-2.html),
+// LP-E cores do not have L3 cache. This seems to be the only way of differentiating them.
+// - https://community.intel.com/t5/Processors/Detecting-LP-E-Cores-on-Meteor-Lake-in-software/m-p/1584555/highlight/true#M70732
+// - https://x.com/InstLatX64/status/1741416428538941718
 int32_t get_core_type(void) {
   uint32_t eax = 0x0000001A;
   uint32_t ebx = 0;
@@ -440,8 +449,26 @@ int32_t get_core_type(void) {
   cpuid(&eax, &ebx, &ecx, &edx);
 
   int32_t type = eax >> 24 & 0xFF;
-  if(type == 0x20) return CORE_TYPE_EFFICIENCY;
-  else if(type == 0x40) return CORE_TYPE_PERFORMANCE;
+  if (type == 0x40) return CORE_TYPE_PERFORMANCE;
+  else if (type == 0x20) {
+    // get_core_type is only called iff hybrid_flag is true, which can only
+    // happen if CPUID maxLevel >= 0x7 so we can assume the CPU supports
+    // CPUID leaf 0x4
+    eax = 0x4;
+    ebx = 0;
+    ecx = 0x3;
+    edx = 0;
+
+    cpuid(&eax, &ebx, &ecx, &edx);
+
+    if (eax == 0) {
+      // No L3 access, this is LP-E
+      return CORE_TYPE_LP_EFFICIENCY;
+    }
+    else {
+      return CORE_TYPE_EFFICIENCY;
+    }
+  }
   else {
     printErr("Found invalid core type: 0x%.8X\n", type);
     return CORE_TYPE_UNKNOWN;
@@ -456,7 +483,6 @@ struct cpuInfo* get_cpu_info(void) {
   cpu->cach = NULL;
   cpu->feat = NULL;
 
-  cpu->num_cpus = 1;
   uint32_t eax = 0;
   uint32_t ebx = 0;
   uint32_t ecx = 0;
@@ -514,7 +540,13 @@ struct cpuInfo* get_cpu_info(void) {
     cpu->hybrid_flag = (edx >> 15) & 0x1;
   }
 
-  if(cpu->hybrid_flag) cpu->num_cpus = 2;
+  if(cpu->hybrid_flag) {
+    struct uarch* tmp = get_cpu_uarch(cpu);
+    cpu->num_cpus = get_hybrid_num_cpus(tmp);
+  }
+  else {
+    cpu->num_cpus = 1;
+  }
 
   struct cpuInfo* ptr = cpu;
   for(uint32_t i=0; i < cpu->num_cpus; i++) {
@@ -529,8 +561,9 @@ struct cpuInfo* get_cpu_info(void) {
       ptr->topo = NULL;
       ptr->cach = NULL;
       ptr->feat = NULL;
-      // We assume that this cores have the
-      // same cpuid capabilities
+      // We assume that this core has the
+      // same cpuid capabilities as the core in the
+      // first module
       ptr->cpu_vendor = cpu->cpu_vendor;
       ptr->maxLevels = cpu->maxLevels;
       ptr->maxExtendedLevels = cpu->maxExtendedLevels;
@@ -656,10 +689,15 @@ bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
 void get_topology_from_udev(struct topology* topo) {
   topo->total_cores = get_ncores_from_cpuinfo();
   // TODO: To be improved in the future
-  // Conservative setting as we only know the total
-  // number of cores.
-  topo->logical_cores = UNKNOWN_DATA;
-  topo->physical_cores = UNKNOWN_DATA;
+  if (topo->total_cores == 1) {
+    // We can assume it's a single core CPU
+    topo->logical_cores = topo->total_cores;
+    topo->physical_cores = topo->total_cores;
+  }
+  else {
+    topo->logical_cores = UNKNOWN_DATA;
+    topo->physical_cores = UNKNOWN_DATA;
+  }
   topo->smt_available = 1;
   topo->smt_supported = 1;
   topo->sockets = 1;
@@ -695,6 +733,8 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
   if(cpu->hybrid_flag) {
     #ifdef __linux__
       topo->total_cores_module = get_total_cores_module(topo->total_cores, module);
+      printBug("get_total_cores_module: Failed to get number of cores in module");
+      return NULL;
     #else
       UNUSED(module);
       topo->total_cores_module = topo->total_cores;
@@ -706,27 +746,25 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
 
   switch(cpu->cpu_vendor) {
     case CPU_VENDOR_INTEL:
+      bool toporet = false;
       if (cpu->maxLevels >= 0x00000004) {
-        bool toporet = get_topology_from_apic(cpu, topo);
-        if(!toporet) {
-          #ifdef __linux__
-            printWarn("Failed to retrieve topology from APIC, using udev...\n");
-            get_topology_from_udev(topo);
-          #else
-            printErr("Failed to retrieve topology from APIC, assumming default values...\n");
-            topo->logical_cores = UNKNOWN_DATA;
-            topo->physical_cores = UNKNOWN_DATA;
-            topo->smt_available = 1;
-            topo->smt_supported = 1;
-          #endif
-        }
+        toporet = get_topology_from_apic(cpu, topo);
       }
       else {
-        printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
-        topo->physical_cores = UNKNOWN_DATA;
-        topo->logical_cores = UNKNOWN_DATA;
-        topo->smt_available = 1;
-        topo->smt_supported = 1;
+        printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000004, cpu->maxLevels);
+      }
+      if(!toporet) {
+        #ifdef __linux__
+          printWarn("Failed to retrieve topology from APIC, using udev...");
+          get_topology_from_udev(topo);
+        #else
+          if (cpu->maxLevels >= 0x00000004)
+            printErr("Failed to retrieve topology from APIC, assumming default values...");
+          topo->logical_cores = UNKNOWN_DATA;
+          topo->physical_cores = UNKNOWN_DATA;
+          topo->smt_available = 1;
+          topo->smt_supported = 1;
+        #endif
       }
       break;
     case CPU_VENDOR_AMD:
@@ -1006,24 +1044,33 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_soc
     string = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN) + 1));
     strcpy(string, STRING_UNKNOWN);
   }
-  else if(topo->smt_supported > 1) {
-    // 4 for digits, 21 for ' cores (SMT disabled)' which is the longest possible output
-    uint32_t max_size = 4+21+1;
-    string = emalloc(sizeof(char) * max_size);
-
-    if(topo->smt_available > 1)
-      snprintf(string, max_size, "%d cores (%d threads)", topo->physical_cores * topo_sockets, topo->logical_cores * topo_sockets);
-    else {
-      if(cpu->cpu_vendor == CPU_VENDOR_AMD)
-        snprintf(string, max_size, "%d cores (SMT disabled)", topo->physical_cores * topo_sockets);
-      else
-        snprintf(string, max_size, "%d cores (HT disabled)", topo->physical_cores * topo_sockets);
-    }
-  }
   else {
-    uint32_t max_size = 4+7+1;
-    string = emalloc(sizeof(char) * max_size);
-    snprintf(string, max_size, "%d cores",topo->physical_cores * topo_sockets);
+    char cores_str[6];
+    memset(cores_str, 0, sizeof(char) * 6);
+    if (topo->physical_cores * topo_sockets > 1)
+      strcpy(cores_str, "cores");
+    else
+      strcpy(cores_str, "core");
+
+    if(topo->smt_supported > 1) {
+      // 4 for digits, 21 for ' cores (SMT disabled)' which is the longest possible output
+      uint32_t max_size = 4+21+1;
+      string = emalloc(sizeof(char) * max_size);
+
+      if(topo->smt_available > 1)
+        snprintf(string, max_size, "%d %s (%d threads)", topo->physical_cores * topo_sockets, cores_str, topo->logical_cores * topo_sockets);
+      else {
+        if(cpu->cpu_vendor == CPU_VENDOR_AMD)
+          snprintf(string, max_size, "%d %s (SMT disabled)", topo->physical_cores * topo_sockets, cores_str);
+        else
+          snprintf(string, max_size, "%d %s (HT disabled)", topo->physical_cores * topo_sockets, cores_str);
+      }
+    }
+    else {
+      uint32_t max_size = 4+7+1;
+      string = emalloc(sizeof(char) * max_size);
+      snprintf(string, max_size, "%d %s",topo->physical_cores * topo_sockets, cores_str);
+    }
   }
 
   return string;

src/x86/uarch.c

@@ -94,6 +94,7 @@ enum {
   UARCH_TIGER_LAKE,
   UARCH_ALDER_LAKE,
   UARCH_RAPTOR_LAKE,
+  UARCH_METEOR_LAKE,
   // AMD //
   UARCH_AM486,
   UARCH_AM5X86,
@@ -248,6 +249,7 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 0,  6, 10,  5, NA, "Comet Lake",        UARCH_COMET_LAKE,       14) // wikichip
   CHECK_UARCH(arch, 0,  6, 10,  6, NA, "Comet Lake",        UARCH_COMET_LAKE,       14) // instlatx64.atw.hu (i7-10710U)
   CHECK_UARCH(arch, 0,  6, 10,  7, NA, "Rocket Lake",       UARCH_ROCKET_LAKE,      14) // instlatx64.atw.hu (i7-11700K)
+  CHECK_UARCH(arch, 0,  6, 10, 10, NA, "Meteor Lake",       UARCH_METEOR_LAKE,       7) // instlatx64.atw.hu (Ultra 7 155H)
   CHECK_UARCH(arch, 0,  6, 11,  7, NA, "Raptor Lake",       UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i5-13600K)
   CHECK_UARCH(arch, 0,  6, 11, 10, NA, "Raptor Lake",       UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i7-1370P)
   CHECK_UARCH(arch, 0,  6, 11, 14, NA, "Alder Lake",        UARCH_ALDER_LAKE,       10) // instlatx64.atw.hu (Alder Lake-N)
@@ -536,6 +538,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
       case UARCH_TIGER_LAKE:
       case UARCH_ALDER_LAKE:
       case UARCH_RAPTOR_LAKE:
+      case UARCH_METEOR_LAKE:
 
       // AMD
       case UARCH_ZEN2:
@@ -549,6 +552,11 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
   }
 }
 
+uint32_t get_hybrid_num_cpus(struct uarch* arch) {
+  if (arch->uarch == UARCH_METEOR_LAKE) return 3;
+  else return 2;
+}
+
 bool choose_new_intel_logo_uarch(struct cpuInfo* cpu) {
   switch(cpu->arch->uarch) {
     case UARCH_ALDER_LAKE:

src/x86/uarch.h

@@ -12,6 +12,7 @@ char* infer_cpu_name_from_uarch(struct uarch* arch);
 bool vpus_are_AVX512(struct cpuInfo* cpu);
 bool is_knights_landing(struct cpuInfo* cpu);
 int get_number_of_vpus(struct cpuInfo* cpu);
+uint32_t get_hybrid_num_cpus(struct uarch* arch);
 bool choose_new_intel_logo_uarch(struct cpuInfo* cpu);
 char* get_str_uarch(struct cpuInfo* cpu);
 char* get_str_process(struct cpuInfo* cpu);