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https://github.com/Dr-Noob/cpufetch.git
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3 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
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64ef0d889c | ||
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d297878a51 | ||
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ac308204c7 |
15
Makefile
15
Makefile
@@ -30,10 +30,6 @@ ifneq ($(OS),Windows_NT)
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HEADERS += $(SRC_DIR)freq/freq.h
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CFLAGS += -pthread
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endif
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ifeq ($(os), FreeBSD)
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SOURCE += $(SRC_COMMON)sysctl.c
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HEADERS += $(SRC_COMMON)sysctl.h
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endif
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CFLAGS += -DARCH_X86 -std=c99 -fstack-protector-all
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else ifeq ($(arch), $(filter $(arch), ppc64le ppc64 ppcle ppc))
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SRC_DIR=src/ppc/
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@@ -42,16 +38,10 @@ ifneq ($(OS),Windows_NT)
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CFLAGS += -DARCH_PPC -std=gnu99 -fstack-protector-all -Wno-language-extension-token
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else ifeq ($(arch), $(filter $(arch), arm aarch64_be aarch64 arm64 armv8b armv8l armv7l armv6l))
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SRC_DIR=src/arm/
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SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_COMMON)pci.c $(SRC_DIR)udev.c sve.o
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SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_COMMON)pci.c $(SRC_DIR)udev.c
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HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_COMMON)pci.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
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CFLAGS += -DARCH_ARM -Wno-unused-parameter -std=c99 -fstack-protector-all
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# Check if the compiler supports -march=armv8-a+sve. We will use it (if supported) to compile SVE detection code later
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is_sve_flag_supported := $(shell $(CC) -march=armv8-a+sve -c $(SRC_DIR)sve.c -o sve_test.o 2> /dev/null && echo 'yes'; rm -f sve_test.o)
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ifeq ($(is_sve_flag_supported), yes)
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SVE_FLAGS += -march=armv8-a+sve
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endif
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ifeq ($(os), Darwin)
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SOURCE += $(SRC_COMMON)sysctl.c
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HEADERS += $(SRC_COMMON)sysctl.h
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@@ -101,9 +91,6 @@ freq_avx.o: Makefile $(SRC_DIR)freq/freq_avx.c $(SRC_DIR)freq/freq_avx.h $(SRC_D
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freq_avx512.o: Makefile $(SRC_DIR)freq/freq_avx512.c $(SRC_DIR)freq/freq_avx512.h $(SRC_DIR)freq/freq.h
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$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -mavx512f -pthread $(SRC_DIR)freq/freq_avx512.c -o $@
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sve.o: Makefile $(SRC_DIR)sve.c $(SRC_DIR)sve.h
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$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SVE_FLAGS) -c $(SRC_DIR)sve.c -o $@
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$(OUTPUT): Makefile $(SOURCE) $(HEADERS)
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ifeq ($(GIT_VERSION),"")
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$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SOURCE) -o $(OUTPUT)
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@@ -45,7 +45,6 @@ cpufetch is a command-line tool written in C that displays the CPU information i
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- [3.1 x86_64](#31-x86_64)
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- [3.2 ARM](#32-arm)
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- [3.3 PowerPC](#33-powerpc)
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- [3.4 RISC-V](#34-risc-v)
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- [4. Colors](#4-colors)
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- [4.1 Specifying a name](#41-specifying-a-name)
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- [4.2 Specifying the colors in RGB format](#42-specifying-the-colors-in-rgb-format)
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@@ -121,11 +120,6 @@ make
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<p align="center"><img width=90% src="pictures/ibm.png"></p>
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<p align="center">Talos II</p>
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## 3.4 RISC-V
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<p align="center"><img width=80% src="pictures/starfive.png"></p>
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<p align="center">StarFive VisionFive 2</p>
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## 4. Colors
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By default, `cpufetch` will print the CPU logo with the system colorscheme. However, you can set a custom color scheme in two different ways:
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Binary file not shown.
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Before Width: | Height: | Size: 42 KiB |
@@ -19,7 +19,6 @@
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#include "udev.h"
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#include "midr.h"
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#include "uarch.h"
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#include "sve.h"
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bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
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return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
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@@ -169,15 +168,6 @@ struct features* get_features_info(void) {
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feat->SHA1 = hwcaps & HWCAP_SHA1;
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feat->SHA2 = hwcaps & HWCAP_SHA2;
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feat->NEON = hwcaps & HWCAP_ASIMD;
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feat->SVE = hwcaps & HWCAP_SVE;
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hwcaps = getauxval(AT_HWCAP2);
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if (errno == ENOENT) {
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printWarn("Unable to retrieve AT_HWCAP2 using getauxval");
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}
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else {
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feat->SVE2 = hwcaps & HWCAP2_SVE2;
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}
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}
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#else
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else {
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@@ -193,8 +183,6 @@ struct features* get_features_info(void) {
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feat->CRC32 = hwcaps & HWCAP2_CRC32;
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feat->SHA1 = hwcaps & HWCAP2_SHA1;
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feat->SHA2 = hwcaps & HWCAP2_SHA2;
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feat->SVE = false;
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feat->SVE2 = false;
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}
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#endif // ifdef __aarch64__
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#elif defined __APPLE__ || __MACH__
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@@ -204,14 +192,8 @@ struct features* get_features_info(void) {
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feat->SHA1 = true;
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feat->SHA2 = true;
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feat->NEON = true;
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feat->SVE = false;
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feat->SVE2 = false;
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#endif // ifdef __linux__
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if (feat->SVE || feat->SVE2) {
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feat->cntb = sve_cntb();
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}
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return feat;
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}
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@@ -412,7 +394,6 @@ struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
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cpu->peak_performance = get_peak_performance(cpu);
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}
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else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
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cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_2 ||
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cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
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cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
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fill_cpu_info_everest_sawtooth(cpu, pcores, ecores);
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@@ -449,7 +430,7 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_soc
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char* get_str_features(struct cpuInfo* cpu) {
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struct features* feat = cpu->feat;
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uint32_t max_len = strlen("NEON,SHA1,SHA2,AES,CRC32,SVE,SVE2,") + 1;
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uint32_t max_len = strlen("NEON,SHA1,SHA2,AES,CRC32,") + 1;
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uint32_t len = 0;
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char* string = ecalloc(max_len, sizeof(char));
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@@ -457,14 +438,6 @@ char* get_str_features(struct cpuInfo* cpu) {
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strcat(string, "NEON,");
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len += 5;
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}
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if(feat->SVE) {
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strcat(string, "SVE,");
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len += 4;
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}
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if(feat->SVE2) {
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strcat(string, "SVE2,");
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len += 5;
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}
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if(feat->SHA1) {
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strcat(string, "SHA1,");
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len += 5;
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@@ -514,10 +487,6 @@ void print_debug(struct cpuInfo* cpu) {
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}
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}
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if (cpu->feat->SVE || cpu->feat->SVE2) {
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printf("- cntb: %d\n", (int) cpu->feat->cntb);
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}
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#if defined(__APPLE__) || defined(__MACH__)
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printf("hw.cpufamily: 0x%.8X\n", get_sys_info_by_name("hw.cpufamily"));
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printf("hw.cpusubfamily: 0x%.8X\n", get_sys_info_by_name("hw.cpusubfamily"));
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111
src/arm/soc.c
111
src/arm/soc.c
@@ -167,13 +167,11 @@ bool match_google(char* soc_name, struct system_on_chip* soc) {
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// https://www.techinsights.com/
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// https://datasheetspdf.com/pdf-file/1316605/HiSilicon/Hi3660/1
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// https://github.com/Dr-Noob/cpufetch/issues/259
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bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
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char* tmp;
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if((tmp = strstr(soc_name, "hi")) != NULL);
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else if((tmp = strstr(soc_name, "kirin")) != NULL);
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else return false;
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if((tmp = strstr(soc_name, "hi")) == NULL)
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return false;
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soc->soc_vendor = SOC_VENDOR_KIRIN;
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@@ -206,7 +204,6 @@ bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
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SOC_EQ(tmp, "hi3680", "980", SOC_HISILICON_3680, soc, 7)
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//SOC_EQ(tmp, "?", "985", SOC_KIRIN, soc, 7)
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SOC_EQ(tmp, "hi3690", "990", SOC_HISILICON_3690, soc, 7)
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SOC_EQ(tmp, "kirin9000s", "9000s", SOC_HISILICON_9000S,soc, 7)
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SOC_END
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}
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@@ -424,9 +421,6 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
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}
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/*
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* Good sources:
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* https://www.geektopia.es/es/products/company/qualcomm/socs/
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*
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* APQ: Application Processor Qualcomm
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* MSM: Mobile Station Modem
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* In a APQXXXX or MSMXXXX, the second digit represents:
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@@ -584,25 +578,14 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
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SOC_EQ(tmp, "SM8250-AB", "865+", SOC_SNAPD_SM8250_AB, soc, 7)
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SOC_EQ(tmp, "SM8350", "888", SOC_SNAPD_SM8350, soc, 5)
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SOC_EQ(tmp, "SM8350-AC", "888+", SOC_SNAPD_SM8350, soc, 5)
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// Snapdragon Gen 4 //
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SOC_EQ(tmp, "SM4375", "4 Gen 1", SOC_SNAPD_SM4375, soc, 6)
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// Snapdragon Gen //
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SOC_EQ(tmp, "SM4450", "4 Gen 2", SOC_SNAPD_SM4450, soc, 4)
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SOC_EQ(tmp, "SM4635", "4s Gen 2", SOC_SNAPD_SM4635, soc, 4)
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// Snapdragon Gen 6 //
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SOC_EQ(tmp, "SM6375-AC", "6s Gen 3", SOC_SNAPD_SM6375_AC, soc, 6)
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SOC_EQ(tmp, "SM6450", "6 Gen 1", SOC_SNAPD_SM6450, soc, 4)
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// Snapdragon Gen 7 //
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SOC_EQ(tmp, "SM7435-AB", "7s Gen 2", SOC_SNAPD_SM7435_AB, soc, 4)
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SOC_EQ(tmp, "SM7450", "7 Gen 1", SOC_SNAPD_SM7450, soc, 4)
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SOC_EQ(tmp, "SM7475", "7+ Gen 2", SOC_SNAPD_SM7475, soc, 4)
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SOC_EQ(tmp, "SM7550-AB", "7 Gen 3", SOC_SNAPD_SM7550_AB, soc, 4)
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SOC_EQ(tmp, "SM7675-AB", "7+ Gen 3", SOC_SNAPD_SM7675_AB, soc, 4)
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// Snapdragon Gen 8 //
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SOC_EQ(tmp, "SM8450", "8 Gen 1", SOC_SNAPD_SM8450, soc, 4)
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SOC_EQ(tmp, "SM8475", "8+ Gen 1", SOC_SNAPD_SM8475, soc, 4)
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SOC_EQ(tmp, "SM8550-AB", "8 Gen 2", SOC_SNAPD_SM8550_AB, soc, 4)
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SOC_EQ(tmp, "SM8635", "8s Gen 3", SOC_SNAPD_SM8635, soc, 4)
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SOC_EQ(tmp, "SM8650-AB", "8 Gen 3", SOC_SNAPD_SM8650_AB, soc, 4)
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SOC_END
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}
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@@ -895,79 +878,6 @@ struct system_on_chip* guess_soc_from_uarch(struct system_on_chip* soc, struct c
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return soc;
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}
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// Return the dt string without the NULL characters.
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char* get_dt_str(char* dt, int filelen) {
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char* dt_without_null = (char *) malloc(sizeof(char) * filelen);
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memcpy(dt_without_null, dt, filelen);
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for (int i=0; i < filelen-1; i++) {
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if (dt_without_null[i] == '\0')
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dt_without_null[i] = ',';
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}
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return dt_without_null;
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}
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bool match_dt(struct system_on_chip* soc, char* dt, int filelen, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
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// The /proc/device-tree/compatible file (passed by dt) uses NULL
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// to separate the strings, so we need to make an special case here
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// and iterate over the NULL characters, thus iterating over each
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// individual compatible strings.
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if (strstr(dt, expected_name) != NULL) {
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fill_soc(soc, soc_name, soc_model, process);
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return true;
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}
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char *compatible = dt;
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char *end_of_dt = dt + filelen;
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while ((compatible = strchr(compatible, '\0')) != end_of_dt) {
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compatible++;
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if (strstr(compatible, expected_name) != NULL) {
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fill_soc(soc, soc_name, soc_model, process);
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return true;
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}
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}
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return false;
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}
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#define DT_START if (false) {}
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#define DT_EQ(dt, filelen, soc, expected_name, soc_name, soc_model, process) \
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else if (match_dt(soc, dt, filelen, expected_name, soc_name, soc_model, process)) return soc;
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#define DT_END(dt, filelen) else { printWarn("guess_soc_from_devtree: No match found for '%s'", get_dt_str(dt, filelen)); return soc; }
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// TODO: Move this to doc
|
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// The number of fields seems non-standard, so for now it seems wiser
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// to just get the entire string with all fields and just look for the
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// substring.
|
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// TODO: Implement this by going trough NULL-separated fields rather than
|
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// using strstr.
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struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
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int len;
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char* dt = get_devtree_compatible(&len);
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if (dt == NULL) {
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return soc;
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}
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// The following are internal codenames of Asahi Linux
|
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// https://github.com/AsahiLinux/docs/wiki/Codenames
|
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DT_START
|
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DT_EQ(dt, len, soc, "apple,t8103", "M1", SOC_APPLE_M1, 5)
|
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DT_EQ(dt, len, soc, "apple,t6000", "M1 Pro", SOC_APPLE_M1_PRO, 5)
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DT_EQ(dt, len, soc, "apple,t6001", "M1 Max", SOC_APPLE_M1_MAX, 5)
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DT_EQ(dt, len, soc, "apple,t6002", "M1 Ultra", SOC_APPLE_M1_ULTRA, 5)
|
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DT_EQ(dt, len, soc, "apple,t8112", "M2", SOC_APPLE_M2, 5)
|
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DT_EQ(dt, len, soc, "apple,t6020", "M2 Pro", SOC_APPLE_M2_PRO, 5)
|
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DT_EQ(dt, len, soc, "apple,t6021", "M2 Max", SOC_APPLE_M2_MAX, 5)
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DT_EQ(dt, len, soc, "apple,t6022", "M2 Ultra", SOC_APPLE_M2_ULTRA, 5)
|
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DT_EQ(dt, len, soc, "apple,t8122", "M3", SOC_APPLE_M3, 3)
|
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DT_EQ(dt, len, soc, "apple,t6030", "M3 Pro", SOC_APPLE_M3_PRO, 3)
|
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DT_EQ(dt, len, soc, "apple,t6031", "M3 Max", SOC_APPLE_M3_MAX, 3)
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DT_EQ(dt, len, soc, "apple,t6034", "M3 Max", SOC_APPLE_M3_MAX, 3)
|
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DT_END(dt, len)
|
||||
}
|
||||
|
||||
struct system_on_chip* guess_soc_from_pci(struct system_on_chip* soc, struct cpuInfo* cpu) {
|
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struct pci_devices * pci = get_pci_devices();
|
||||
if (pci == NULL) {
|
||||
@@ -982,10 +892,9 @@ struct system_on_chip* guess_soc_from_pci(struct system_on_chip* soc, struct cpu
|
||||
} pciToSoC;
|
||||
|
||||
pciToSoC socFromPCI[] = {
|
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{PCI_VENDOR_NVIDIA, PCI_DEVICE_TEGRA_X1, {SOC_TEGRA_X1, SOC_VENDOR_NVIDIA, 20, "Tegra X1", NULL} },
|
||||
// {PCI_VENDOR_NVIDIA, PCI_DEVICE_GH_200,{SOC_GH_200, SOC_VENDOR_NVIDIA, ?, "Grace Hopper", NULL} },
|
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{PCI_VENDOR_AMPERE, PCI_DEVICE_ALTRA, {SOC_AMPERE_ALTRA, SOC_VENDOR_AMPERE, 7, "Altra", NULL} }, // https://www.anandtech.com/show/15575/amperes-altra-80-core-n1-soc-for-hyperscalers-against-rome-and-xeon
|
||||
{0x0000, 0x0000, {UNKNOWN, SOC_VENDOR_UNKNOWN, -1, "", NULL} }
|
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{PCI_VENDOR_NVIDIA, PCI_DEVICE_TEGRA_X1, {SOC_TEGRA_X1, SOC_VENDOR_NVIDIA, 20, "Tegra X1", NULL} },
|
||||
// {PCI_VENDOR_NVIDIA, PCI_DEVICE_GH_200,{SOC_GH_200, SOC_VENDOR_NVIDIA, ?, "Grace Hopper", NULL} },
|
||||
{0x0000, 0x0000, {UNKNOWN, SOC_VENDOR_UNKNOWN, -1, "", NULL} }
|
||||
};
|
||||
|
||||
int index = 0;
|
||||
@@ -1115,12 +1024,10 @@ struct system_on_chip* guess_soc_apple(struct system_on_chip* soc) {
|
||||
}
|
||||
}
|
||||
else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
|
||||
cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_2 ||
|
||||
cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
|
||||
cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
|
||||
// Check M3 version
|
||||
if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
|
||||
cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_2) {
|
||||
if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH) {
|
||||
fill_soc(soc, "M3", SOC_APPLE_M3, 3);
|
||||
}
|
||||
else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO) {
|
||||
@@ -1178,10 +1085,6 @@ struct system_on_chip* get_soc(struct cpuInfo* cpu) {
|
||||
printWarn("SoC detection failed using Android: Found '%s' string", soc->raw_name);
|
||||
}
|
||||
#endif // ifdef __ANDROID__
|
||||
// If previous steps failed, try with the device tree
|
||||
if (soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
|
||||
soc = guess_soc_from_devtree(soc);
|
||||
}
|
||||
// If previous steps failed, try with nvmem
|
||||
if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
|
||||
soc = guess_soc_from_nvmem(soc);
|
||||
|
||||
@@ -29,7 +29,6 @@ enum {
|
||||
SOC_HISILICON_3670,
|
||||
SOC_HISILICON_3680,
|
||||
SOC_HISILICON_3690,
|
||||
SOC_HISILICON_9000S,
|
||||
// Kunpeng //
|
||||
SOC_KUNPENG_920,
|
||||
SOC_KUNPENG_930,
|
||||
@@ -271,16 +270,13 @@ enum {
|
||||
SOC_SNAPD_SDM660,
|
||||
SOC_SNAPD_SM6115,
|
||||
SOC_SNAPD_SM6125,
|
||||
SOC_SNAPD_SM6375_AC,
|
||||
SOC_SNAPD_SM6450,
|
||||
SOC_SNAPD_SDM670,
|
||||
SOC_SNAPD_SM6150,
|
||||
SOC_SNAPD_SM6350,
|
||||
SOC_SNAPD_SDM710,
|
||||
SOC_SNAPD_SDM712,
|
||||
SOC_SNAPD_SM4375,
|
||||
SOC_SNAPD_SM4450,
|
||||
SOC_SNAPD_SM4635,
|
||||
SOC_SNAPD_SM7125,
|
||||
SOC_SNAPD_SM7150_AA,
|
||||
SOC_SNAPD_SM7150_AB,
|
||||
@@ -292,8 +288,6 @@ enum {
|
||||
SOC_SNAPD_SM7435_AB,
|
||||
SOC_SNAPD_SM7450,
|
||||
SOC_SNAPD_SM7475,
|
||||
SOC_SNAPD_SM7550_AB,
|
||||
SOC_SNAPD_SM7675_AB,
|
||||
SOC_SNAPD_MSM8974AA,
|
||||
SOC_SNAPD_MSM8974AB,
|
||||
SOC_SNAPD_MSM8974AC,
|
||||
@@ -315,9 +309,6 @@ enum {
|
||||
SOC_SNAPD_SM8350,
|
||||
SOC_SNAPD_SM8450,
|
||||
SOC_SNAPD_SM8475,
|
||||
SOC_SNAPD_SM8550_AB,
|
||||
SOC_SNAPD_SM8635,
|
||||
SOC_SNAPD_SM8650_AB,
|
||||
// APPLE
|
||||
SOC_APPLE_M1,
|
||||
SOC_APPLE_M1_PRO,
|
||||
@@ -380,25 +371,22 @@ enum {
|
||||
SOC_GOOGLE_TENSOR_G3,
|
||||
// NVIDIA,
|
||||
SOC_TEGRA_X1,
|
||||
// ALTRA
|
||||
SOC_AMPERE_ALTRA,
|
||||
// UNKNOWN
|
||||
SOC_MODEL_UNKNOWN
|
||||
};
|
||||
|
||||
inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
|
||||
if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_2712) return SOC_VENDOR_BROADCOM;
|
||||
else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_9000S) return SOC_VENDOR_KIRIN;
|
||||
else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_3690) return SOC_VENDOR_KIRIN;
|
||||
else if(soc >= SOC_KUNPENG_920 && soc <= SOC_KUNPENG_930) return SOC_VENDOR_KUNPENG;
|
||||
else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
|
||||
else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
|
||||
else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8650_AB) return SOC_VENDOR_SNAPDRAGON;
|
||||
else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8475) return SOC_VENDOR_SNAPDRAGON;
|
||||
else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE;
|
||||
else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
|
||||
else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP;
|
||||
else if(soc >= SOC_GOOGLE_TENSOR && soc <= SOC_GOOGLE_TENSOR_G3) return SOC_VENDOR_GOOGLE;
|
||||
else if(soc >= SOC_TEGRA_X1 && soc <= SOC_TEGRA_X1) return SOC_VENDOR_NVIDIA;
|
||||
else if(soc >= SOC_AMPERE_ALTRA && soc <= SOC_AMPERE_ALTRA) return SOC_VENDOR_AMPERE;
|
||||
return SOC_VENDOR_UNKNOWN;
|
||||
}
|
||||
|
||||
|
||||
@@ -1,15 +0,0 @@
|
||||
#include <stdint.h>
|
||||
#include "../common/global.h"
|
||||
|
||||
// https://learn.arm.com/learning-paths/servers-and-cloud-computing/sve/sve_basics/#:~:text=Using%20a%20text%20editor%20of%20your%20choice%2C%20copy,svcntb%28%29%29%3B%20%7D%20This%20program%20prints%20the%20vector%20length
|
||||
uint64_t sve_cntb(void) {
|
||||
#ifdef __ARM_FEATURE_SVE
|
||||
uint64_t x0 = 0;
|
||||
__asm volatile("cntb %0"
|
||||
: "=r"(x0));
|
||||
return x0;
|
||||
#else
|
||||
printWarn("sve_cntb: Hardware supports SVE, but it was not enabled by the compiler");
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
@@ -1,6 +0,0 @@
|
||||
#ifndef __SVE_DETECTION__
|
||||
#define __SVE_DETECTION__
|
||||
|
||||
uint64_t sve_cntb(void);
|
||||
|
||||
#endif
|
||||
@@ -33,7 +33,6 @@ enum {
|
||||
ISA_ARMv8_3_A,
|
||||
ISA_ARMv8_4_A,
|
||||
ISA_ARMv8_5_A,
|
||||
ISA_ARMv8_6_A,
|
||||
ISA_ARMv9_A
|
||||
};
|
||||
|
||||
@@ -76,7 +75,6 @@ static const ISA isas_uarch[] = {
|
||||
[UARCH_THUNDERX] = ISA_ARMv8_A,
|
||||
[UARCH_THUNDERX2] = ISA_ARMv8_1_A,
|
||||
[UARCH_TAISHAN_V110] = ISA_ARMv8_2_A,
|
||||
[UARCH_TAISHAN_V120] = ISA_ARMv8_2_A, // Not confirmed
|
||||
[UARCH_TAISHAN_V200] = ISA_ARMv8_2_A, // Not confirmed
|
||||
[UARCH_DENVER] = ISA_ARMv8_A,
|
||||
[UARCH_DENVER2] = ISA_ARMv8_A,
|
||||
@@ -94,10 +92,8 @@ static const ISA isas_uarch[] = {
|
||||
[UARCH_EXYNOS_M5] = ISA_ARMv8_2_A,
|
||||
[UARCH_ICESTORM] = ISA_ARMv8_5_A, // https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/AArch64TargetParser.def
|
||||
[UARCH_FIRESTORM] = ISA_ARMv8_5_A,
|
||||
[UARCH_BLIZZARD] = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
|
||||
[UARCH_AVALANCHE] = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
|
||||
[UARCH_SAWTOOTH] = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
|
||||
[UARCH_EVEREST] = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
|
||||
[UARCH_BLIZZARD] = ISA_ARMv8_5_A, // Not confirmed
|
||||
[UARCH_AVALANCHE] = ISA_ARMv8_5_A,
|
||||
[UARCH_PJ4] = ISA_ARMv7_A,
|
||||
[UARCH_XIAOMI] = ISA_ARMv8_A,
|
||||
};
|
||||
@@ -115,7 +111,6 @@ static char* isas_string[] = {
|
||||
[ISA_ARMv8_3_A] = "ARMv8.3",
|
||||
[ISA_ARMv8_4_A] = "ARMv8.4",
|
||||
[ISA_ARMv8_5_A] = "ARMv8.5",
|
||||
[ISA_ARMv8_6_A] = "ARMv8.6",
|
||||
[ISA_ARMv9_A] = "ARMv9"
|
||||
};
|
||||
|
||||
@@ -207,10 +202,8 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
|
||||
CHECK_UARCH(arch, cpu, 'C', 0x0AF, NA, NA, "ThunderX2 99XX", UARCH_THUNDERX2, CPU_VENDOR_CAVIUM)
|
||||
|
||||
CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110", UARCH_TAISHAN_V110, CPU_VENDOR_HUAWEI) // Kunpeng 920 series
|
||||
CHECK_UARCH(arch, cpu, 'H', 0xD02, 2, 2, "TaiShan v120", UARCH_TAISHAN_V120, CPU_VENDOR_HUAWEI) // Kiring 9000S Big cores (https://github.com/Dr-Noob/cpufetch/issues/259)
|
||||
CHECK_UARCH(arch, cpu, 'H', 0xD02, NA, NA, "TaiShan v200", UARCH_TAISHAN_V200, CPU_VENDOR_HUAWEI) // Kunpeng 930 series (found in openeuler: https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/XQCV7NX2UKRIUWUFKRF4PO3QENCOUFR3)
|
||||
CHECK_UARCH(arch, cpu, 'H', 0xD40, NA, NA, "Cortex-A76", UARCH_CORTEX_A76, CPU_VENDOR_ARM) // Kirin 980 Big/Medium cores -> Cortex-A76
|
||||
CHECK_UARCH(arch, cpu, 'H', 0xD42, NA, NA, "TaiShan v120", UARCH_TAISHAN_V120, CPU_VENDOR_HUAWEI) // Kiring 9000S Small Cores (https://github.com/Dr-Noob/cpufetch/issues/259)
|
||||
|
||||
CHECK_UARCH(arch, cpu, 'N', 0x000, NA, NA, "Denver", UARCH_DENVER, CPU_VENDOR_NVIDIA)
|
||||
CHECK_UARCH(arch, cpu, 'N', 0x003, NA, NA, "Denver2", UARCH_DENVER2, CPU_VENDOR_NVIDIA)
|
||||
@@ -252,8 +245,6 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
|
||||
|
||||
CHECK_UARCH(arch, cpu, 'a', 0x022, NA, NA, "Icestorm", UARCH_ICESTORM, CPU_VENDOR_APPLE)
|
||||
CHECK_UARCH(arch, cpu, 'a', 0x023, NA, NA, "Firestorm", UARCH_FIRESTORM, CPU_VENDOR_APPLE)
|
||||
CHECK_UARCH(arch, cpu, 'a', 0x024, NA, NA, "Icestorm", UARCH_ICESTORM, CPU_VENDOR_APPLE) // https://github.com/Dr-Noob/cpufetch/issues/263
|
||||
CHECK_UARCH(arch, cpu, 'a', 0x025, NA, NA, "Firestorm", UARCH_FIRESTORM, CPU_VENDOR_APPLE) // https://github.com/Dr-Noob/cpufetch/issues/263
|
||||
CHECK_UARCH(arch, cpu, 'a', 0x030, NA, NA, "Blizzard", UARCH_BLIZZARD, CPU_VENDOR_APPLE)
|
||||
CHECK_UARCH(arch, cpu, 'a', 0x031, NA, NA, "Avalanche", UARCH_AVALANCHE, CPU_VENDOR_APPLE)
|
||||
CHECK_UARCH(arch, cpu, 'a', 0x048, NA, NA, "Sawtooth", UARCH_SAWTOOTH, CPU_VENDOR_APPLE)
|
||||
@@ -275,7 +266,6 @@ bool is_ARMv8_or_newer(struct cpuInfo* cpu) {
|
||||
cpu->arch->isa == ISA_ARMv8_3_A ||
|
||||
cpu->arch->isa == ISA_ARMv8_4_A ||
|
||||
cpu->arch->isa == ISA_ARMv8_5_A ||
|
||||
cpu->arch->isa == ISA_ARMv8_6_A ||
|
||||
cpu->arch->isa == ISA_ARMv9_A;
|
||||
}
|
||||
|
||||
@@ -301,10 +291,7 @@ int get_vpus_width(struct cpuInfo* cpu) {
|
||||
case UARCH_NEOVERSE_V1:
|
||||
return 256;
|
||||
default:
|
||||
if (cpu->feat->SVE && cpu->feat->cntb > 0) {
|
||||
return cpu->feat->cntb * 8;
|
||||
}
|
||||
else if (cpu->feat->NEON) {
|
||||
if(cpu->feat->NEON) {
|
||||
if(is_ARMv8_or_newer(cpu)) {
|
||||
return 128;
|
||||
}
|
||||
@@ -338,7 +325,6 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
|
||||
case UARCH_ICESTORM: // [https://dougallj.github.io/applecpu/icestorm-simd.html]
|
||||
case UARCH_BLIZZARD: // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
|
||||
case UARCH_TAISHAN_V110:// [https://www-file.huawei.com/-/media/corp2020/pdf/publications/huawei-research/2022/huawei-research-issue1-en.pdf]: "128-bit x 2 for single precision"
|
||||
case UARCH_TAISHAN_V120:// Not confirmed, asssuming same as v110
|
||||
case UARCH_TAISHAN_V200:// Not confirmed, asssuming same as v110
|
||||
case UARCH_CORTEX_A57: // [https://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/5]
|
||||
case UARCH_CORTEX_A72: // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]
|
||||
|
||||
@@ -83,9 +83,7 @@ enum {
|
||||
UARCH_BRAHMA_B15,
|
||||
UARCH_BRAHMA_B53,
|
||||
UARCH_XGENE, // Applied Micro X-Gene.
|
||||
// HUAWEI
|
||||
UARCH_TAISHAN_V110, // HiSilicon TaiShan v110
|
||||
UARCH_TAISHAN_V120, // HiSilicon TaiShan v120
|
||||
UARCH_TAISHAN_V200, // HiSilicon TaiShan v200
|
||||
// PHYTIUM
|
||||
UARCH_XIAOMI, // Not to be confused with Xiaomi Inc
|
||||
|
||||
@@ -394,25 +394,6 @@ $C2## ## ## ## ## ## ## ## #: :# \
|
||||
$C2## ## ## ## ## ## ## ## ####### \
|
||||
$C2## ## ### ## ###### ## ## ## "
|
||||
|
||||
#define ASCII_AMPERE \
|
||||
"$C1 \
|
||||
$C1 \
|
||||
$C1 ## \
|
||||
$C1 #### \
|
||||
$C1 ### ## \
|
||||
$C1 ### ### \
|
||||
$C1 ### ### \
|
||||
$C1 ### ### \
|
||||
$C1 ## ### \
|
||||
$C1 ####### ### ### \
|
||||
$C1 ###### ## ###### ### \
|
||||
$C1 #### ### ######## \
|
||||
$C1 #### ### #### \
|
||||
$C1 ### ### #### \
|
||||
$C1 ## ### ### \
|
||||
$C1 \
|
||||
$C1 "
|
||||
|
||||
// --------------------- LONG LOGOS ------------------------- //
|
||||
#define ASCII_AMD_L \
|
||||
"$C1 \
|
||||
@@ -588,7 +569,6 @@ asciiL logo_sifive = { ASCII_SIFIVE, 48, 19, true, {C_BG_WHITE, C_BG_
|
||||
asciiL logo_starfive = { ASCII_STARFIVE, 33, 17, false, {C_FG_WHITE}, {C_FG_WHITE, C_FG_BLUE} };
|
||||
asciiL logo_sipeed = { ASCII_SIPEED, 41, 16, true, {C_BG_RED, C_BG_WHITE}, {C_FG_RED, C_FG_WHITE} };
|
||||
asciiL logo_nvidia = { ASCII_NVIDIA, 45, 19, false, {C_FG_GREEN, C_FG_WHITE}, {C_FG_WHITE, C_FG_GREEN} };
|
||||
asciiL logo_ampere = { ASCII_AMPERE, 50, 17, false, {C_FG_RED}, {C_FG_WHITE, C_FG_RED} };
|
||||
|
||||
// Long variants | ----------------------------------------------------------------------------------------------------------------|
|
||||
asciiL logo_amd_l = { ASCII_AMD_L, 62, 19, true, {C_BG_WHITE, C_BG_GREEN}, {C_FG_WHITE, C_FG_GREEN} };
|
||||
|
||||
@@ -45,8 +45,9 @@ enum {
|
||||
};
|
||||
|
||||
enum {
|
||||
CORE_TYPE_EFFICIENCY,
|
||||
CORE_TYPE_PERFORMANCE,
|
||||
CORE_TYPE_EFFICIENCY,
|
||||
CORE_TYPE_LP_EFFICIENCY,
|
||||
CORE_TYPE_UNKNOWN
|
||||
};
|
||||
|
||||
@@ -124,9 +125,6 @@ struct features {
|
||||
bool SHA1;
|
||||
bool SHA2;
|
||||
bool CRC32;
|
||||
bool SVE;
|
||||
bool SVE2;
|
||||
uint64_t cntb;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
@@ -62,7 +62,7 @@
|
||||
#endif
|
||||
|
||||
#ifndef GIT_FULL_VERSION
|
||||
static const char* VERSION = "1.06";
|
||||
static const char* VERSION = "1.05";
|
||||
#endif
|
||||
|
||||
enum {
|
||||
|
||||
@@ -14,6 +14,14 @@
|
||||
#define PCI_PATH "/sys/bus/pci/devices/"
|
||||
#define MAX_LENGTH_PCI_DIR_NAME 1024
|
||||
|
||||
/*
|
||||
* doc: https://wiki.osdev.org/PCI#Class_Codes
|
||||
* https://pci-ids.ucw.cz/read/PC
|
||||
*/
|
||||
#define PCI_VENDOR_ID_AMD 0x1002
|
||||
#define CLASS_VGA_CONTROLLER 0x0300
|
||||
#define CLASS_3D_CONTROLLER 0x0302
|
||||
|
||||
// Return a list of PCI devices containing only
|
||||
// the sysfs path
|
||||
struct pci_devices * get_pci_paths(void) {
|
||||
@@ -90,9 +98,9 @@ void populate_pci_devices(struct pci_devices * pci) {
|
||||
int path_size = strlen(PCI_PATH) + strlen(dev->path) + 2;
|
||||
|
||||
// Read vendor_id
|
||||
char *vendor_id_path = emalloc(sizeof(char) * (path_size + strlen("vendor") + 1));
|
||||
char *vendor_id_path = emalloc(sizeof(char) * (path_size + strlen("vendor")));
|
||||
sprintf(vendor_id_path, "%s/%s/%s", PCI_PATH, dev->path, "vendor");
|
||||
|
||||
|
||||
if ((buf = read_file(vendor_id_path, &filelen)) == NULL) {
|
||||
printWarn("read_file: %s: %s\n", vendor_id_path, strerror(errno));
|
||||
dev->vendor_id = 0;
|
||||
@@ -102,7 +110,7 @@ void populate_pci_devices(struct pci_devices * pci) {
|
||||
}
|
||||
|
||||
// Read device_id
|
||||
char *device_id_path = emalloc(sizeof(char) * (path_size + strlen("device") + 1));
|
||||
char *device_id_path = emalloc(sizeof(char) * (path_size + strlen("device")));
|
||||
sprintf(device_id_path, "%s/%s/%s", PCI_PATH, dev->path, "device");
|
||||
|
||||
if ((buf = read_file(device_id_path, &filelen)) == NULL) {
|
||||
@@ -118,6 +126,43 @@ void populate_pci_devices(struct pci_devices * pci) {
|
||||
}
|
||||
}
|
||||
|
||||
// Right now, we are interested in PCI devices which
|
||||
// vendor is NVIDIA (to be extended in the future).
|
||||
// Should we also restrict to VGA controllers only?
|
||||
bool pci_device_is_useful(struct pci_device* dev) {
|
||||
return dev->vendor_id == PCI_VENDOR_NVIDIA;
|
||||
}
|
||||
|
||||
// Filter the input list in order to get only those PCI devices which
|
||||
// we are interested in (decided by pci_device_is_useful)
|
||||
// and return the filtered result.
|
||||
struct pci_devices * filter_pci_devices(struct pci_devices * pci) {
|
||||
int * devices_to_get = emalloc(sizeof(int) * pci->num_devices);
|
||||
int dev_ptr = 0;
|
||||
|
||||
for (int i=0; i < pci->num_devices; i++) {
|
||||
if (pci_device_is_useful(pci->devices[i])) {
|
||||
devices_to_get[dev_ptr] = i;
|
||||
dev_ptr++;
|
||||
}
|
||||
}
|
||||
|
||||
struct pci_devices * pci_filtered = emalloc(sizeof(struct pci_devices));
|
||||
pci_filtered->num_devices = dev_ptr;
|
||||
|
||||
if (pci_filtered->num_devices == 0) {
|
||||
pci_filtered->devices = NULL;
|
||||
}
|
||||
else {
|
||||
pci_filtered->devices = emalloc(sizeof(struct pci_device) * pci_filtered->num_devices);
|
||||
|
||||
for (int i=0; i < pci_filtered->num_devices; i++)
|
||||
pci_filtered->devices[i] = pci->devices[devices_to_get[i]];
|
||||
}
|
||||
|
||||
return pci_filtered;
|
||||
}
|
||||
|
||||
// Return a list of PCI devices that could be used to infer the SoC.
|
||||
// The criteria to determine which devices are suitable for this task
|
||||
// is decided in filter_pci_devices.
|
||||
@@ -129,5 +174,5 @@ struct pci_devices * get_pci_devices(void) {
|
||||
|
||||
populate_pci_devices(pci);
|
||||
|
||||
return pci;
|
||||
return filter_pci_devices(pci);
|
||||
}
|
||||
|
||||
@@ -1,11 +1,8 @@
|
||||
#ifndef __PCI__
|
||||
#define __PCI__
|
||||
|
||||
#define PCI_VENDOR_NVIDIA 0x10de
|
||||
#define PCI_VENDOR_AMPERE 0x1def
|
||||
|
||||
#define PCI_VENDOR_NVIDIA 0x10de
|
||||
#define PCI_DEVICE_TEGRA_X1 0x0faf
|
||||
#define PCI_DEVICE_ALTRA 0xe100
|
||||
|
||||
struct pci_device {
|
||||
char * path;
|
||||
|
||||
@@ -389,8 +389,6 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
|
||||
art->art = &logo_allwinner;
|
||||
else if(art->vendor == SOC_VENDOR_ROCKCHIP)
|
||||
art->art = &logo_rockchip;
|
||||
else if(art->vendor == SOC_VENDOR_AMPERE)
|
||||
art->art = &logo_ampere;
|
||||
else if(art->vendor == SOC_VENDOR_NVIDIA)
|
||||
art->art = choose_ascii_art_aux(&logo_nvidia_l, &logo_nvidia, term, lf);
|
||||
else {
|
||||
@@ -616,8 +614,9 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
|
||||
}
|
||||
|
||||
if(hybrid_architecture) {
|
||||
if(ptr->core_type == CORE_TYPE_EFFICIENCY) sprintf(cpu_num, "E-cores:");
|
||||
else if(ptr->core_type == CORE_TYPE_PERFORMANCE) sprintf(cpu_num, "P-cores:");
|
||||
if (ptr->core_type == CORE_TYPE_PERFORMANCE) sprintf(cpu_num, "P-cores:");
|
||||
else if (ptr->core_type == CORE_TYPE_EFFICIENCY) sprintf(cpu_num, "E-cores:");
|
||||
else if (ptr->core_type == CORE_TYPE_LP_EFFICIENCY) sprintf(cpu_num, "LP-E-cores:");
|
||||
else printBug("Found invalid core type!\n");
|
||||
|
||||
setAttribute(art, ATTRIBUTE_CPU_NUM, cpu_num);
|
||||
@@ -636,10 +635,9 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
|
||||
}
|
||||
|
||||
// Show the most modern vector instructions.
|
||||
// If AVX is supported show it, otherwise show SSE
|
||||
if (strcmp(avx, "No") == 0) {
|
||||
if (strcmp(sse, "No") != 0) {
|
||||
setAttribute(art, ATTRIBUTE_SSE, sse);
|
||||
}
|
||||
setAttribute(art, ATTRIBUTE_SSE, sse);
|
||||
}
|
||||
else {
|
||||
setAttribute(art, ATTRIBUTE_AVX, avx);
|
||||
|
||||
@@ -21,7 +21,6 @@ static char* soc_trademark_string[] = {
|
||||
[SOC_VENDOR_ROCKCHIP] = "Rockchip ",
|
||||
[SOC_VENDOR_GOOGLE] = "Google ",
|
||||
[SOC_VENDOR_NVIDIA] = "NVIDIA ",
|
||||
[SOC_VENDOR_AMPERE] = "Ampere ",
|
||||
// RISC-V
|
||||
[SOC_VENDOR_SIFIVE] = "SiFive ",
|
||||
[SOC_VENDOR_STARFIVE] = "StarFive ",
|
||||
|
||||
@@ -25,7 +25,6 @@ enum {
|
||||
SOC_VENDOR_ROCKCHIP,
|
||||
SOC_VENDOR_GOOGLE,
|
||||
SOC_VENDOR_NVIDIA,
|
||||
SOC_VENDOR_AMPERE,
|
||||
// RISC-V
|
||||
SOC_VENDOR_SIFIVE,
|
||||
SOC_VENDOR_STARFIVE,
|
||||
|
||||
@@ -21,12 +21,9 @@
|
||||
#define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D
|
||||
#endif
|
||||
// M3 / A16 / A17
|
||||
// M3: https://ratfactor.com/zig/stdlib-browseable2/c/darwin.zig.html
|
||||
// M3_2: https://github.com/Dr-Noob/cpufetch/issues/230
|
||||
// PRO: https://github.com/Dr-Noob/cpufetch/issues/225
|
||||
// MAX: https://github.com/Dr-Noob/cpufetch/issues/210
|
||||
// https://ratfactor.com/zig/stdlib-browseable2/c/darwin.zig.html
|
||||
// https://github.com/Dr-Noob/cpufetch/issues/210
|
||||
#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765EDEA
|
||||
#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_2 0xFA33415E
|
||||
#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO 0x5F4DEA93
|
||||
#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX 0x72015832
|
||||
|
||||
@@ -43,14 +40,6 @@
|
||||
#define CPUSUBFAMILY_ARM_HC_HD 5
|
||||
#endif
|
||||
|
||||
// For alternative way to get CPU frequency on macOS and *BSD
|
||||
#ifdef __APPLE__
|
||||
#define CPUFREQUENCY_SYSCTL "hw.cpufrequency_max"
|
||||
#else
|
||||
// For FreeBSD, not sure about other *BSD
|
||||
#define CPUFREQUENCY_SYSCTL "dev.cpu.0.freq"
|
||||
#endif
|
||||
|
||||
uint32_t get_sys_info_by_name(char* name);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,10 +1,7 @@
|
||||
#include "../common/global.h"
|
||||
#include "udev.h"
|
||||
#include "global.h"
|
||||
#include "cpu.h"
|
||||
|
||||
#define _PATH_DEVTREE "/proc/device-tree/compatible"
|
||||
|
||||
// https://www.kernel.org/doc/html/latest/core-api/cpu_hotplug.html
|
||||
int get_ncores_from_cpuinfo(void) {
|
||||
// Examples:
|
||||
@@ -352,13 +349,3 @@ bool is_devtree_compatible(char* str) {
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
char* get_devtree_compatible(int *filelen) {
|
||||
char* buf;
|
||||
|
||||
if ((buf = read_file(_PATH_DEVTREE, filelen)) == NULL) {
|
||||
printWarn("read_file: %s: %s", _PATH_DEVTREE, strerror(errno));
|
||||
}
|
||||
|
||||
return buf;
|
||||
}
|
||||
|
||||
@@ -43,6 +43,5 @@ int get_num_sockets_package_cpus(struct topology* topo);
|
||||
int get_ncores_from_cpuinfo(void);
|
||||
char* get_field_from_cpuinfo(char* CPUINFO_FIELD);
|
||||
bool is_devtree_compatible(char* str);
|
||||
char* get_devtree_compatible(int *filelen);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -91,6 +91,7 @@ int get_total_cores_module(int total_cores, int module) {
|
||||
|
||||
while(!end) {
|
||||
if(!bind_to_cpu(i)) {
|
||||
printBug("get_total_cores_module: Cannot bind to core %d", i);
|
||||
return -1;
|
||||
}
|
||||
uint32_t eax = 0x0000001A;
|
||||
@@ -99,6 +100,17 @@ int get_total_cores_module(int total_cores, int module) {
|
||||
uint32_t edx = 0;
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
int32_t core_type = eax >> 24 & 0xFF;
|
||||
|
||||
// Here we artificially create a new core type for
|
||||
// LP-E cores. In case the core has no L3 (on a hybrid)
|
||||
// architecture, then we now it's an LP-E core.
|
||||
eax = 0x4;
|
||||
ebx = 0;
|
||||
ecx = 0x3;
|
||||
edx = 0;
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
core_type += eax == 0;
|
||||
|
||||
bool found = false;
|
||||
|
||||
for(int j=0; j < total_modules && !found; j++) {
|
||||
|
||||
133
src/x86/cpuid.c
133
src/x86/cpuid.c
@@ -5,9 +5,6 @@
|
||||
#include "../common/udev.h"
|
||||
#include <unistd.h>
|
||||
#endif
|
||||
#if defined (__FreeBSD__) || defined (__APPLE__)
|
||||
#include "../common/sysctl.h"
|
||||
#endif
|
||||
|
||||
#ifdef __linux__
|
||||
#include "../common/freq.h"
|
||||
@@ -140,39 +137,31 @@ bool abbreviate_intel_cpu_name(char** name) {
|
||||
char* new_name_ptr = new_name;
|
||||
char* aux_ptr = NULL;
|
||||
|
||||
// 1. Remove "(R)"
|
||||
// 1. Find "Intel(R)"
|
||||
old_name_ptr = strstr(old_name_ptr, "Intel(R)");
|
||||
if(old_name_ptr == NULL) return false;
|
||||
strcpy(new_name_ptr, "Intel");
|
||||
new_name_ptr += strlen("Intel");
|
||||
old_name_ptr += strlen("Intel(R)");
|
||||
|
||||
// 2. Remove "(R)" or "(TM)"
|
||||
aux_ptr = strstr(old_name_ptr, "(");
|
||||
if(aux_ptr == NULL) return false;
|
||||
strncpy(new_name_ptr, old_name_ptr, aux_ptr-old_name_ptr);
|
||||
|
||||
new_name_ptr += aux_ptr-old_name_ptr;
|
||||
strcpy(new_name_ptr, " ");
|
||||
new_name_ptr++;
|
||||
old_name_ptr = strstr(aux_ptr, ")");
|
||||
if(old_name_ptr == NULL) return false;
|
||||
old_name_ptr++;
|
||||
while(*old_name_ptr == ' ') old_name_ptr++;
|
||||
|
||||
// 3. Copy the CPU name
|
||||
// 2. Search for "@"
|
||||
aux_ptr = strstr(old_name_ptr, "@");
|
||||
if(aux_ptr == NULL) return false;
|
||||
strncpy(new_name_ptr, old_name_ptr, (aux_ptr-1)-old_name_ptr);
|
||||
if(aux_ptr == NULL) {
|
||||
// New CPUs, copy end ptr is end of string
|
||||
aux_ptr = old_name + strlen(old_name);
|
||||
strncpy(new_name_ptr, old_name_ptr, (aux_ptr)-old_name_ptr);
|
||||
}
|
||||
else {
|
||||
// Copy end ptr is "@"
|
||||
strncpy(new_name_ptr, old_name_ptr, (aux_ptr-1)-old_name_ptr);
|
||||
}
|
||||
|
||||
// 4. Remove dummy strings in Intel CPU names
|
||||
// 3. Remove dummy strings in Intel CPU names
|
||||
strremove(new_name, "(R)");
|
||||
strremove(new_name, "(TM)");
|
||||
strremove(new_name, " CPU");
|
||||
strremove(new_name, " Dual");
|
||||
strremove(new_name, " 0");
|
||||
|
||||
free(old_name);
|
||||
*name = new_name;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
@@ -400,6 +389,17 @@ bool set_cpu_module(int m, int total_modules, int32_t* first_core) {
|
||||
uint32_t edx = 0;
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
int32_t core_type = eax >> 24 & 0xFF;
|
||||
|
||||
// Here we artificially create a new core type for
|
||||
// LP-E cores. In case the core has no L3 (on a hybrid)
|
||||
// architecture, then we now it's an LP-E core.
|
||||
eax = 0x4;
|
||||
ebx = 0;
|
||||
ecx = 0x3;
|
||||
edx = 0;
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
core_type += eax == 0;
|
||||
|
||||
bool found = false;
|
||||
|
||||
for(int j=0; j < total_modules && !found; j++) {
|
||||
@@ -426,13 +426,19 @@ bool set_cpu_module(int m, int total_modules, int32_t* first_core) {
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
// This is a normal architecture
|
||||
// This is a non-hybrid architecture
|
||||
*first_core = 0;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
// Difference between E and LP-E cores:
|
||||
// According to Intel Core Ultra Processor Datasheet Volume 1 of 2
|
||||
// (https://www.intel.com/content/www/us/en/content-details/792044/intel-core-ultra-processor-datasheet-volume-1-of-2.html),
|
||||
// LP-E cores do not have L3 cache. This seems to be the only way of differentiating them.
|
||||
// - https://community.intel.com/t5/Processors/Detecting-LP-E-Cores-on-Meteor-Lake-in-software/m-p/1584555/highlight/true#M70732
|
||||
// - https://x.com/InstLatX64/status/1741416428538941718
|
||||
int32_t get_core_type(void) {
|
||||
uint32_t eax = 0x0000001A;
|
||||
uint32_t ebx = 0;
|
||||
@@ -443,8 +449,26 @@ int32_t get_core_type(void) {
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
int32_t type = eax >> 24 & 0xFF;
|
||||
if(type == 0x20) return CORE_TYPE_EFFICIENCY;
|
||||
else if(type == 0x40) return CORE_TYPE_PERFORMANCE;
|
||||
if (type == 0x40) return CORE_TYPE_PERFORMANCE;
|
||||
else if (type == 0x20) {
|
||||
// get_core_type is only called iff hybrid_flag is true, which can only
|
||||
// happen if CPUID maxLevel >= 0x7 so we can assume the CPU supports
|
||||
// CPUID leaf 0x4
|
||||
eax = 0x4;
|
||||
ebx = 0;
|
||||
ecx = 0x3;
|
||||
edx = 0;
|
||||
|
||||
cpuid(&eax, &ebx, &ecx, &edx);
|
||||
|
||||
if (eax == 0) {
|
||||
// No L3 access, this is LP-E
|
||||
return CORE_TYPE_LP_EFFICIENCY;
|
||||
}
|
||||
else {
|
||||
return CORE_TYPE_EFFICIENCY;
|
||||
}
|
||||
}
|
||||
else {
|
||||
printErr("Found invalid core type: 0x%.8X\n", type);
|
||||
return CORE_TYPE_UNKNOWN;
|
||||
@@ -459,7 +483,6 @@ struct cpuInfo* get_cpu_info(void) {
|
||||
cpu->cach = NULL;
|
||||
cpu->feat = NULL;
|
||||
|
||||
cpu->num_cpus = 1;
|
||||
uint32_t eax = 0;
|
||||
uint32_t ebx = 0;
|
||||
uint32_t ecx = 0;
|
||||
@@ -517,7 +540,13 @@ struct cpuInfo* get_cpu_info(void) {
|
||||
cpu->hybrid_flag = (edx >> 15) & 0x1;
|
||||
}
|
||||
|
||||
if(cpu->hybrid_flag) cpu->num_cpus = 2;
|
||||
if(cpu->hybrid_flag) {
|
||||
struct uarch* tmp = get_cpu_uarch(cpu);
|
||||
cpu->num_cpus = get_hybrid_num_cpus(tmp);
|
||||
}
|
||||
else {
|
||||
cpu->num_cpus = 1;
|
||||
}
|
||||
|
||||
struct cpuInfo* ptr = cpu;
|
||||
for(uint32_t i=0; i < cpu->num_cpus; i++) {
|
||||
@@ -532,8 +561,9 @@ struct cpuInfo* get_cpu_info(void) {
|
||||
ptr->topo = NULL;
|
||||
ptr->cach = NULL;
|
||||
ptr->feat = NULL;
|
||||
// We assume that this cores have the
|
||||
// same cpuid capabilities
|
||||
// We assume that this core has the
|
||||
// same cpuid capabilities as the core in the
|
||||
// first module
|
||||
ptr->cpu_vendor = cpu->cpu_vendor;
|
||||
ptr->maxLevels = cpu->maxLevels;
|
||||
ptr->maxExtendedLevels = cpu->maxExtendedLevels;
|
||||
@@ -703,6 +733,8 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
|
||||
if(cpu->hybrid_flag) {
|
||||
#ifdef __linux__
|
||||
topo->total_cores_module = get_total_cores_module(topo->total_cores, module);
|
||||
printBug("get_total_cores_module: Failed to get number of cores in module");
|
||||
return NULL;
|
||||
#else
|
||||
UNUSED(module);
|
||||
topo->total_cores_module = topo->total_cores;
|
||||
@@ -712,9 +744,9 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
|
||||
topo->total_cores_module = topo->total_cores;
|
||||
}
|
||||
|
||||
bool toporet = false;
|
||||
switch(cpu->cpu_vendor) {
|
||||
case CPU_VENDOR_INTEL:
|
||||
bool toporet = false;
|
||||
if (cpu->maxLevels >= 0x00000004) {
|
||||
toporet = get_topology_from_apic(cpu, topo);
|
||||
}
|
||||
@@ -753,15 +785,10 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
|
||||
}
|
||||
}
|
||||
else {
|
||||
#ifdef __linux__
|
||||
printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X), using udev...", 0x80000008, cpu->maxExtendedLevels);
|
||||
get_topology_from_udev(topo);
|
||||
#else
|
||||
printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000008, cpu->maxExtendedLevels);
|
||||
topo->physical_cores = 1;
|
||||
topo->logical_cores = 1;
|
||||
topo->smt_supported = 1;
|
||||
#endif
|
||||
printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000008, cpu->maxExtendedLevels);
|
||||
topo->physical_cores = 1;
|
||||
topo->logical_cores = 1;
|
||||
topo->smt_supported = 1;
|
||||
}
|
||||
|
||||
if (cpu->maxLevels >= 0x00000001) {
|
||||
@@ -941,20 +968,10 @@ struct frequency* get_frequency_info(struct cpuInfo* cpu) {
|
||||
freq->measured = false;
|
||||
|
||||
if(cpu->maxLevels < 0x00000016) {
|
||||
#if defined (_WIN32)
|
||||
#if defined (_WIN32) || defined (__APPLE__)
|
||||
printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000016, cpu->maxLevels);
|
||||
freq->base = UNKNOWN_DATA;
|
||||
freq->max = UNKNOWN_DATA;
|
||||
#elif defined (__FreeBSD__) || defined (__APPLE__)
|
||||
printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X). Using sysctl", 0x00000016, cpu->maxLevels);
|
||||
uint32_t freq_hz = get_sys_info_by_name(CPUFREQUENCY_SYSCTL);
|
||||
if (freq_hz == 0) {
|
||||
printWarn("Read max CPU frequency from sysctl and got 0 MHz");
|
||||
freq->max = UNKNOWN_DATA;
|
||||
}
|
||||
|
||||
freq->base = UNKNOWN_DATA;
|
||||
freq->max = freq_hz;
|
||||
#else
|
||||
printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X). Using udev", 0x00000016, cpu->maxLevels);
|
||||
freq->base = UNKNOWN_DATA;
|
||||
@@ -1114,14 +1131,8 @@ char* get_str_sse(struct cpuInfo* cpu) {
|
||||
last+=SSE4_2_sl;
|
||||
}
|
||||
|
||||
if (last == 0) {
|
||||
snprintf(string, 2+1, "No");
|
||||
}
|
||||
else {
|
||||
//Purge last comma
|
||||
string[last-1] = '\0';
|
||||
}
|
||||
|
||||
//Purge last comma
|
||||
string[last-1] = '\0';
|
||||
return string;
|
||||
}
|
||||
|
||||
|
||||
@@ -47,10 +47,8 @@ typedef uint32_t MICROARCH;
|
||||
enum {
|
||||
UARCH_UNKNOWN,
|
||||
// INTEL //
|
||||
UARCH_I486,
|
||||
UARCH_P5,
|
||||
UARCH_P5_MMX,
|
||||
UARCH_P6_PRO,
|
||||
UARCH_P6_PENTIUM_II,
|
||||
UARCH_P6_PENTIUM_III,
|
||||
UARCH_DOTHAN,
|
||||
@@ -96,11 +94,10 @@ enum {
|
||||
UARCH_TIGER_LAKE,
|
||||
UARCH_ALDER_LAKE,
|
||||
UARCH_RAPTOR_LAKE,
|
||||
UARCH_METEOR_LAKE,
|
||||
// AMD //
|
||||
UARCH_AM486,
|
||||
UARCH_AM5X86,
|
||||
UARCH_SSA5,
|
||||
UARCH_K5,
|
||||
UARCH_K6,
|
||||
UARCH_K7,
|
||||
UARCH_K8,
|
||||
@@ -153,30 +150,16 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
|
||||
// ------------------------------------------------------------------------------- //
|
||||
// EF F EM M S //
|
||||
UARCH_START
|
||||
CHECK_UARCH(arch, 0, 4, 0, 0, NA, "i80486DX", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 1, NA, "i80486DX-50", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 2, NA, "i80486SX", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 3, NA, "i80486DX2", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 4, NA, "i80486SL", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 5, NA, "i80486SX2", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 7, NA, "i80486DX2WB", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 8, NA, "i80486DX4", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 9, NA, "i80486DX4WB", UARCH_I486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 5, 0, 0, NA, "P5", UARCH_P5, 800)
|
||||
CHECK_UARCH(arch, 0, 5, 0, 1, NA, "P5", UARCH_P5, 800)
|
||||
CHECK_UARCH(arch, 0, 5, 0, 2, NA, "P54C", UARCH_P5, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 5, 0, 3, NA, "P24T (Overdrive)", UARCH_P5, 600) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 5, 0, 4, NA, "P55C (MMX)", UARCH_P5_MMX, 350) // https://www.cpu-world.com/CPUs/Pentium/TYPE-Pentium%20MMX.html
|
||||
CHECK_UARCH(arch, 0, 5, 0, 7, NA, "P54C", UARCH_P5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 5, 0, 8, NA, "Tillamook", UARCH_P5_MMX, 250) // http://instlatx64.atw.hu./
|
||||
CHECK_UARCH(arch, 0, 5, 0, 2, NA, "P5", UARCH_P5, UNK)
|
||||
CHECK_UARCH(arch, 0, 5, 0, 3, NA, "P5", UARCH_P5, 600)
|
||||
CHECK_UARCH(arch, 0, 5, 0, 4, NA, "P5 (MMX)", UARCH_P5_MMX, UNK)
|
||||
CHECK_UARCH(arch, 0, 5, 0, 7, NA, "P5 (MMX)", UARCH_P5_MMX, UNK)
|
||||
CHECK_UARCH(arch, 0, 5, 0, 8, NA, "P5 (MMX)", UARCH_P5_MMX, 250)
|
||||
CHECK_UARCH(arch, 0, 5, 0, 9, 0, "Lakemont", UARCH_LAKEMONT, 32)
|
||||
CHECK_UARCH(arch, 0, 5, 0, 9, NA, "P5 (MMX)", UARCH_P5_MMX, UNK)
|
||||
CHECK_UARCH(arch, 0, 5, 0, 10, 0, "Lakemont", UARCH_LAKEMONT, 32)
|
||||
CHECK_UARCH(arch, 0, 6, 0, 1, 1, "P6", UARCH_P6_PRO, UNK)
|
||||
CHECK_UARCH(arch, 0, 6, 0, 1, 2, "P6", UARCH_P6_PRO, UNK)
|
||||
CHECK_UARCH(arch, 0, 6, 0, 1, 6, "P6", UARCH_P6_PRO, 350)
|
||||
CHECK_UARCH(arch, 0, 6, 0, 1, 7, "P6", UARCH_P6_PRO, 350)
|
||||
CHECK_UARCH(arch, 0, 6, 0, 1, 9, "P6", UARCH_P6_PRO, 350)
|
||||
CHECK_UARCH(arch, 0, 6, 0, 0, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK)
|
||||
CHECK_UARCH(arch, 0, 6, 0, 1, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK) // process depends on core
|
||||
CHECK_UARCH(arch, 0, 6, 0, 2, NA, "P6 (Pentium II)", UARCH_P6_PENTIUM_II, UNK)
|
||||
@@ -266,6 +249,7 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
|
||||
CHECK_UARCH(arch, 0, 6, 10, 5, NA, "Comet Lake", UARCH_COMET_LAKE, 14) // wikichip
|
||||
CHECK_UARCH(arch, 0, 6, 10, 6, NA, "Comet Lake", UARCH_COMET_LAKE, 14) // instlatx64.atw.hu (i7-10710U)
|
||||
CHECK_UARCH(arch, 0, 6, 10, 7, NA, "Rocket Lake", UARCH_ROCKET_LAKE, 14) // instlatx64.atw.hu (i7-11700K)
|
||||
CHECK_UARCH(arch, 0, 6, 10, 10, NA, "Meteor Lake", UARCH_METEOR_LAKE, 7) // instlatx64.atw.hu (Ultra 7 155H)
|
||||
CHECK_UARCH(arch, 0, 6, 11, 7, NA, "Raptor Lake", UARCH_RAPTOR_LAKE, 10) // instlatx64.atw.hu (i5-13600K)
|
||||
CHECK_UARCH(arch, 0, 6, 11, 10, NA, "Raptor Lake", UARCH_RAPTOR_LAKE, 10) // instlatx64.atw.hu (i7-1370P)
|
||||
CHECK_UARCH(arch, 0, 6, 11, 14, NA, "Alder Lake", UARCH_ALDER_LAKE, 10) // instlatx64.atw.hu (Alder Lake-N)
|
||||
@@ -297,16 +281,11 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
|
||||
// ----------------------------------------------------------------------------- //
|
||||
// EF F EM M S //
|
||||
UARCH_START
|
||||
CHECK_UARCH(arch, 0, 4, 0, 3, NA, "Am486DX2", UARCH_AM486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 7, NA, "Am486DX2WB", UARCH_AM486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 8, NA, "Am486DX4", UARCH_AM486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 9, NA, "Am486DX4WB", UARCH_AM486, UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 14, NA, "Am5x86", UARCH_AM5X86, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 15, NA, "Am5x86WB", UARCH_AM5X86, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 5, 0, 0, NA, "SSA5 (K5)", UARCH_SSA5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 5, 0, 1, NA, "K5", UARCH_K5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 5, 0, 2, NA, "K5", UARCH_K5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 5, 0, 3, NA, "K5", UARCH_K5, 350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
|
||||
CHECK_UARCH(arch, 0, 4, 0, 3, NA, "Am486", UARCH_AM486, UNK)
|
||||
CHECK_UARCH(arch, 0, 4, 0, 7, NA, "Am486", UARCH_AM486, UNK)
|
||||
CHECK_UARCH(arch, 0, 4, 0, 8, NA, "Am486", UARCH_AM486, UNK)
|
||||
CHECK_UARCH(arch, 0, 4, 0, 9, NA, "Am486", UARCH_AM486, UNK)
|
||||
CHECK_UARCH(arch, 0, 4, NA, NA, NA, "Am5x86", UARCH_AM5X86, UNK)
|
||||
CHECK_UARCH(arch, 0, 5, 0, 6, NA, "K6", UARCH_K6, 300)
|
||||
CHECK_UARCH(arch, 0, 5, 0, 7, NA, "K6", UARCH_K6, 250) // *p from sandpile.org
|
||||
CHECK_UARCH(arch, 0, 5, 0, 10, NA, "K7", UARCH_K7, 130) // Geode NX
|
||||
@@ -502,42 +481,16 @@ char* infer_cpu_name_from_uarch(struct uarch* arch) {
|
||||
|
||||
char *str = NULL;
|
||||
|
||||
switch (arch->uarch) {
|
||||
// Intel
|
||||
case UARCH_I486:
|
||||
str = "Intel 486";
|
||||
break;
|
||||
case UARCH_P5:
|
||||
str = "Intel Pentium";
|
||||
break;
|
||||
case UARCH_P5_MMX:
|
||||
str = "Intel Pentium MMX";
|
||||
break;
|
||||
case UARCH_P6_PRO:
|
||||
str = "Intel Pentium Pro";
|
||||
break;
|
||||
case UARCH_P6_PENTIUM_II:
|
||||
str = "Intel Pentium II";
|
||||
break;
|
||||
case UARCH_P6_PENTIUM_III:
|
||||
str = "Intel Pentium III";
|
||||
break;
|
||||
|
||||
// AMD
|
||||
case UARCH_AM486:
|
||||
str = "AMD 486";
|
||||
break;
|
||||
case UARCH_AM5X86:
|
||||
str = "AMD 5x86";
|
||||
break;
|
||||
case UARCH_SSA5:
|
||||
str = "AMD 5k86";
|
||||
break;
|
||||
|
||||
default:
|
||||
printErr("Unable to find name from uarch: %d", arch->uarch);
|
||||
break;
|
||||
}
|
||||
if (arch->uarch == UARCH_P5)
|
||||
str = "Intel Pentium";
|
||||
else if (arch->uarch == UARCH_P5_MMX)
|
||||
str = "Intel Pentium MMX";
|
||||
else if (arch->uarch == UARCH_P6_PENTIUM_II)
|
||||
str = "Intel Pentium II";
|
||||
else if (arch->uarch == UARCH_P6_PENTIUM_III)
|
||||
str = "Intel Pentium III";
|
||||
else
|
||||
printErr("Unable to find name from uarch: %d", arch->uarch);
|
||||
|
||||
if (str == NULL) {
|
||||
cpu_name = ecalloc(strlen(STRING_UNKNOWN) + 1, sizeof(char));
|
||||
@@ -585,6 +538,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
|
||||
case UARCH_TIGER_LAKE:
|
||||
case UARCH_ALDER_LAKE:
|
||||
case UARCH_RAPTOR_LAKE:
|
||||
case UARCH_METEOR_LAKE:
|
||||
|
||||
// AMD
|
||||
case UARCH_ZEN2:
|
||||
@@ -598,6 +552,11 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t get_hybrid_num_cpus(struct uarch* arch) {
|
||||
if (arch->uarch == UARCH_METEOR_LAKE) return 3;
|
||||
else return 2;
|
||||
}
|
||||
|
||||
bool choose_new_intel_logo_uarch(struct cpuInfo* cpu) {
|
||||
switch(cpu->arch->uarch) {
|
||||
case UARCH_ALDER_LAKE:
|
||||
|
||||
@@ -12,6 +12,7 @@ char* infer_cpu_name_from_uarch(struct uarch* arch);
|
||||
bool vpus_are_AVX512(struct cpuInfo* cpu);
|
||||
bool is_knights_landing(struct cpuInfo* cpu);
|
||||
int get_number_of_vpus(struct cpuInfo* cpu);
|
||||
uint32_t get_hybrid_num_cpus(struct uarch* arch);
|
||||
bool choose_new_intel_logo_uarch(struct cpuInfo* cpu);
|
||||
char* get_str_uarch(struct cpuInfo* cpu);
|
||||
char* get_str_process(struct cpuInfo* cpu);
|
||||
|
||||
Reference in New Issue
Block a user