[v1.05][ARM] Improve Ampere logo

Makefile

@@ -38,10 +38,16 @@ ifneq ($(OS),Windows_NT)
 		CFLAGS += -DARCH_PPC -std=gnu99 -fstack-protector-all -Wno-language-extension-token
 	else ifeq ($(arch), $(filter $(arch), arm aarch64_be aarch64 arm64 armv8b armv8l armv7l armv6l))
 		SRC_DIR=src/arm/
-		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_COMMON)pci.c $(SRC_DIR)udev.c
+		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_COMMON)pci.c $(SRC_DIR)udev.c sve.o
 		HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h  $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_COMMON)pci.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
 		CFLAGS += -DARCH_ARM -Wno-unused-parameter -std=c99 -fstack-protector-all
 
+		# Check if the compiler supports -march=armv8-a+sve. We will use it (if supported) to compile SVE detection code later
+		is_sve_flag_supported := $(shell $(CC) -march=armv8-a+sve -c $(SRC_DIR)sve.c -o sve_test.o 2> /dev/null && echo 'yes'; rm -f sve_test.o)
+		ifeq ($(is_sve_flag_supported), yes)
+			SVE_FLAGS += -march=armv8-a+sve
+		endif
+
 		ifeq ($(os), Darwin)
 			SOURCE += $(SRC_COMMON)sysctl.c
 			HEADERS += $(SRC_COMMON)sysctl.h
@@ -91,6 +97,9 @@ freq_avx.o: Makefile $(SRC_DIR)freq/freq_avx.c $(SRC_DIR)freq/freq_avx.h $(SRC_D
 freq_avx512.o: Makefile $(SRC_DIR)freq/freq_avx512.c $(SRC_DIR)freq/freq_avx512.h $(SRC_DIR)freq/freq.h
 	$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -mavx512f -pthread $(SRC_DIR)freq/freq_avx512.c -o $@
 
+sve.o: Makefile $(SRC_DIR)sve.c $(SRC_DIR)sve.h
+	$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SVE_FLAGS) -c $(SRC_DIR)sve.c -o $@
+
 $(OUTPUT): Makefile $(SOURCE) $(HEADERS)
 ifeq ($(GIT_VERSION),"")
 	$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SOURCE) -o $(OUTPUT)

README.md

@@ -45,6 +45,7 @@ cpufetch is a command-line tool written in C that displays the CPU information i
   - [3.1 x86_64](#31-x86_64)
   - [3.2 ARM](#32-arm)
   - [3.3 PowerPC](#33-powerpc)
+  - [3.4 RISC-V](#34-risc-v)
 - [4. Colors](#4-colors)
   - [4.1 Specifying a name](#41-specifying-a-name)
   - [4.2 Specifying the colors in RGB format](#42-specifying-the-colors-in-rgb-format)
@@ -120,6 +121,11 @@ make
 <p align="center"><img width=90% src="pictures/ibm.png"></p>
 <p align="center">Talos II</p>
 
+## 3.4 RISC-V
+
+<p align="center"><img width=80% src="pictures/starfive.png"></p>
+<p align="center">StarFive VisionFive 2</p>
+
 ## 4. Colors
 By default, `cpufetch` will print the CPU logo with the system colorscheme. However, you can set a custom color scheme in two different ways:
 

src/arm/midr.c

@@ -19,6 +19,7 @@
 #include "udev.h"
 #include "midr.h"
 #include "uarch.h"
+#include "sve.h"
 
 bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
   return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
@@ -168,6 +169,15 @@ struct features* get_features_info(void) {
     feat->SHA1 = hwcaps & HWCAP_SHA1;
     feat->SHA2 = hwcaps & HWCAP_SHA2;
     feat->NEON = hwcaps & HWCAP_ASIMD;
+    feat->SVE = hwcaps & HWCAP_SVE;
+
+    hwcaps = getauxval(AT_HWCAP2);
+    if (errno == ENOENT) {
+      printWarn("Unable to retrieve AT_HWCAP2 using getauxval");
+    }
+    else {
+      feat->SVE2 = hwcaps & HWCAP2_SVE2;
+    }
   }
 #else
   else {
@@ -183,6 +193,8 @@ struct features* get_features_info(void) {
     feat->CRC32 = hwcaps & HWCAP2_CRC32;
     feat->SHA1 = hwcaps & HWCAP2_SHA1;
     feat->SHA2 = hwcaps & HWCAP2_SHA2;
+    feat->SVE = false;
+    feat->SVE2 = false;
   }
 #endif // ifdef __aarch64__
 #elif defined __APPLE__ || __MACH__
@@ -192,8 +204,14 @@ struct features* get_features_info(void) {
   feat->SHA1 = true;
   feat->SHA2 = true;
   feat->NEON = true;
+  feat->SVE = false;
+  feat->SVE2 = false;
 #endif  // ifdef __linux__
 
+  if (feat->SVE || feat->SVE2) {
+    feat->cntb = sve_cntb();
+  }
+
   return feat;
 }
 
@@ -430,7 +448,7 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_soc
 
 char* get_str_features(struct cpuInfo* cpu) {
   struct features* feat = cpu->feat;
-  uint32_t max_len = strlen("NEON,SHA1,SHA2,AES,CRC32,") + 1;
+  uint32_t max_len = strlen("NEON,SHA1,SHA2,AES,CRC32,SVE,SVE2") + 1;
   uint32_t len = 0;
   char* string = ecalloc(max_len, sizeof(char));
 
@@ -438,6 +456,14 @@ char* get_str_features(struct cpuInfo* cpu) {
     strcat(string, "NEON,");
     len += 5;
   }
+  if(feat->SVE) {
+    strcat(string, "SVE,");
+    len += 4;
+  }
+  if(feat->SVE2) {
+    strcat(string, "SVE2,");
+    len += 5;
+  }
   if(feat->SHA1) {
     strcat(string, "SHA1,");
     len += 5;
@@ -487,6 +513,10 @@ void print_debug(struct cpuInfo* cpu) {
     }
   }
 
+  if (cpu->feat->SVE || cpu->feat->SVE2) {
+    printf("- cntb: %d\n", (int) cpu->feat->cntb);
+  }
+
   #if defined(__APPLE__) || defined(__MACH__)
     printf("hw.cpufamily: 0x%.8X\n", get_sys_info_by_name("hw.cpufamily"));
     printf("hw.cpusubfamily: 0x%.8X\n", get_sys_info_by_name("hw.cpusubfamily"));

src/arm/soc.c

@@ -167,11 +167,13 @@ bool match_google(char* soc_name, struct system_on_chip* soc) {
 
 // https://www.techinsights.com/
 // https://datasheetspdf.com/pdf-file/1316605/HiSilicon/Hi3660/1
+// https://github.com/Dr-Noob/cpufetch/issues/259
 bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
   char* tmp;
 
-  if((tmp = strstr(soc_name, "hi")) == NULL)
+  if((tmp = strstr(soc_name, "hi")) != NULL);
-    return false;
+  else if((tmp = strstr(soc_name, "kirin")) != NULL);
+  else return false;
 
   soc->soc_vendor = SOC_VENDOR_KIRIN;
 
@@ -204,6 +206,7 @@ bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "hi3680",     "980",   SOC_HISILICON_3680, soc,  7)
   //SOC_EQ(tmp, "?",        "985",   SOC_KIRIN, soc,  7)
   SOC_EQ(tmp, "hi3690",     "990",   SOC_HISILICON_3690, soc,  7)
+  SOC_EQ(tmp, "kirin9000s", "9000s", SOC_HISILICON_9000S,soc,  7)
   SOC_END
 }
 
@@ -421,6 +424,9 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
 }
 
 /*
+ * Good sources:
+ * https://www.geektopia.es/es/products/company/qualcomm/socs/
+ *
  * APQ: Application Processor Qualcomm
  * MSM: Mobile Station Modem
  * In a APQXXXX or MSMXXXX, the second digit represents:
@@ -578,14 +584,25 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "SM8250-AB",      "865+",      SOC_SNAPD_SM8250_AB,      soc,  7)
   SOC_EQ(tmp, "SM8350",         "888",       SOC_SNAPD_SM8350,         soc,  5)
   SOC_EQ(tmp, "SM8350-AC",      "888+",      SOC_SNAPD_SM8350,         soc,  5)
-  // Snapdragon Gen //
+  // Snapdragon Gen 4 //
+  SOC_EQ(tmp, "SM4375",         "4 Gen 1",   SOC_SNAPD_SM4375,         soc,  6)
   SOC_EQ(tmp, "SM4450",         "4 Gen 2",   SOC_SNAPD_SM4450,         soc,  4)
+  SOC_EQ(tmp, "SM4635",         "4s Gen 2",  SOC_SNAPD_SM4635,         soc,  4)
+  // Snapdragon Gen 6 //
+  SOC_EQ(tmp, "SM6375-AC",      "6s Gen 3",  SOC_SNAPD_SM6375_AC,      soc,  6)
   SOC_EQ(tmp, "SM6450",         "6 Gen 1",   SOC_SNAPD_SM6450,         soc,  4)
+  // Snapdragon Gen 7 //
   SOC_EQ(tmp, "SM7435-AB",      "7s Gen 2",  SOC_SNAPD_SM7435_AB,      soc,  4)
   SOC_EQ(tmp, "SM7450",         "7 Gen 1",   SOC_SNAPD_SM7450,         soc,  4)
   SOC_EQ(tmp, "SM7475",         "7+ Gen 2",  SOC_SNAPD_SM7475,         soc,  4)
+  SOC_EQ(tmp, "SM7550-AB",      "7 Gen 3",   SOC_SNAPD_SM7550_AB,      soc,  4)
+  SOC_EQ(tmp, "SM7675-AB",      "7+ Gen 3",  SOC_SNAPD_SM7675_AB,      soc,  4)
+  // Snapdragon Gen 8 //
   SOC_EQ(tmp, "SM8450",         "8 Gen 1",   SOC_SNAPD_SM8450,         soc,  4)
   SOC_EQ(tmp, "SM8475",         "8+ Gen 1",  SOC_SNAPD_SM8475,         soc,  4)
+  SOC_EQ(tmp, "SM8550-AB",      "8 Gen 2",   SOC_SNAPD_SM8550_AB,      soc,  4)
+  SOC_EQ(tmp, "SM8635",         "8s Gen 3",  SOC_SNAPD_SM8635,         soc,  4)
+  SOC_EQ(tmp, "SM8650-AB",      "8 Gen 3",   SOC_SNAPD_SM8650_AB,      soc,  4)
   SOC_END
 }
 
@@ -894,6 +911,7 @@ struct system_on_chip* guess_soc_from_pci(struct system_on_chip* soc, struct cpu
   pciToSoC socFromPCI[] = {
     {PCI_VENDOR_NVIDIA, PCI_DEVICE_TEGRA_X1, {SOC_TEGRA_X1,     SOC_VENDOR_NVIDIA,  20, "Tegra X1", NULL} },
     // {PCI_VENDOR_NVIDIA, PCI_DEVICE_GH_200,{SOC_GH_200,       SOC_VENDOR_NVIDIA,   ?, "Grace Hopper", NULL} },
+    {PCI_VENDOR_AMPERE, PCI_DEVICE_ALTRA,    {SOC_AMPERE_ALTRA, SOC_VENDOR_AMPERE,   7, "Altra",    NULL} }, // https://www.anandtech.com/show/15575/amperes-altra-80-core-n1-soc-for-hyperscalers-against-rome-and-xeon
     {0x0000,            0x0000,              {UNKNOWN,          SOC_VENDOR_UNKNOWN, -1,      "",    NULL} }
   };
 

src/arm/socs.h

@@ -29,6 +29,7 @@ enum {
   SOC_HISILICON_3670,
   SOC_HISILICON_3680,
   SOC_HISILICON_3690,
+  SOC_HISILICON_9000S,
   // Kunpeng //
   SOC_KUNPENG_920,
   SOC_KUNPENG_930,
@@ -270,13 +271,16 @@ enum {
   SOC_SNAPD_SDM660,
   SOC_SNAPD_SM6115,
   SOC_SNAPD_SM6125,
+  SOC_SNAPD_SM6375_AC,
   SOC_SNAPD_SM6450,
   SOC_SNAPD_SDM670,
   SOC_SNAPD_SM6150,
   SOC_SNAPD_SM6350,
   SOC_SNAPD_SDM710,
   SOC_SNAPD_SDM712,
+  SOC_SNAPD_SM4375,
   SOC_SNAPD_SM4450,
+  SOC_SNAPD_SM4635,
   SOC_SNAPD_SM7125,
   SOC_SNAPD_SM7150_AA,
   SOC_SNAPD_SM7150_AB,
@@ -288,6 +292,8 @@ enum {
   SOC_SNAPD_SM7435_AB,
   SOC_SNAPD_SM7450,
   SOC_SNAPD_SM7475,
+  SOC_SNAPD_SM7550_AB,
+  SOC_SNAPD_SM7675_AB,
   SOC_SNAPD_MSM8974AA,
   SOC_SNAPD_MSM8974AB,
   SOC_SNAPD_MSM8974AC,
@@ -309,6 +315,9 @@ enum {
   SOC_SNAPD_SM8350,
   SOC_SNAPD_SM8450,
   SOC_SNAPD_SM8475,
+  SOC_SNAPD_SM8550_AB,
+  SOC_SNAPD_SM8635,
+  SOC_SNAPD_SM8650_AB,
   // APPLE
   SOC_APPLE_M1,
   SOC_APPLE_M1_PRO,
@@ -371,22 +380,25 @@ enum {
   SOC_GOOGLE_TENSOR_G3,
   // NVIDIA,
   SOC_TEGRA_X1,
+  // ALTRA
+  SOC_AMPERE_ALTRA,
   // UNKNOWN
   SOC_MODEL_UNKNOWN
 };
 
 inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
   if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_2712) return SOC_VENDOR_BROADCOM;
-  else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_3690) return SOC_VENDOR_KIRIN;
+  else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_9000S) return SOC_VENDOR_KIRIN;
   else if(soc >= SOC_KUNPENG_920 && soc <= SOC_KUNPENG_930) return SOC_VENDOR_KUNPENG;
   else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
   else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
-  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8475) return SOC_VENDOR_SNAPDRAGON;
+  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8650_AB) return SOC_VENDOR_SNAPDRAGON;
   else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE;
   else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
   else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP;
   else if(soc >= SOC_GOOGLE_TENSOR && soc <= SOC_GOOGLE_TENSOR_G3) return SOC_VENDOR_GOOGLE;
   else if(soc >= SOC_TEGRA_X1 && soc <= SOC_TEGRA_X1) return SOC_VENDOR_NVIDIA;
+  else if(soc >= SOC_AMPERE_ALTRA && soc <= SOC_AMPERE_ALTRA) return SOC_VENDOR_AMPERE;
   return SOC_VENDOR_UNKNOWN;
 }
 

src/arm/sve.c

@@ -0,0 +1,15 @@
+#include <stdint.h>
+#include "../common/global.h"
+
+// https://learn.arm.com/learning-paths/servers-and-cloud-computing/sve/sve_basics/#:~:text=Using%20a%20text%20editor%20of%20your%20choice%2C%20copy,svcntb%28%29%29%3B%20%7D%20This%20program%20prints%20the%20vector%20length
+uint64_t sve_cntb(void) {
+  #ifdef __ARM_FEATURE_SVE
+    uint64_t x0 = 0;
+    __asm volatile("cntb %0"
+         : "=r"(x0));
+    return x0;
+  #else
+    printWarn("sve_cntb: Hardware supports SVE, but it was not enabled by the compiler");
+    return 0;
+  #endif
+}

src/arm/sve.h

@@ -0,0 +1,6 @@
+#ifndef __SVE_DETECTION__
+#define __SVE_DETECTION__
+
+uint64_t sve_cntb(void);
+
+#endif

src/arm/uarch.c

@@ -75,6 +75,7 @@ static const ISA isas_uarch[] = {
   [UARCH_THUNDERX]     = ISA_ARMv8_A,
   [UARCH_THUNDERX2]    = ISA_ARMv8_1_A,
   [UARCH_TAISHAN_V110] = ISA_ARMv8_2_A,
+  [UARCH_TAISHAN_V120] = ISA_ARMv8_2_A, // Not confirmed
   [UARCH_TAISHAN_V200] = ISA_ARMv8_2_A, // Not confirmed
   [UARCH_DENVER]       = ISA_ARMv8_A,
   [UARCH_DENVER2]      = ISA_ARMv8_A,
@@ -202,8 +203,10 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   CHECK_UARCH(arch, cpu, 'C', 0x0AF, NA, NA, "ThunderX2 99XX",        UARCH_THUNDERX2,    CPU_VENDOR_CAVIUM)
 
   CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110",          UARCH_TAISHAN_V110, CPU_VENDOR_HUAWEI) // Kunpeng 920 series
+  CHECK_UARCH(arch, cpu, 'H', 0xD02,  2,  2, "TaiShan v120",          UARCH_TAISHAN_V120, CPU_VENDOR_HUAWEI) // Kiring 9000S Big cores (https://github.com/Dr-Noob/cpufetch/issues/259)
   CHECK_UARCH(arch, cpu, 'H', 0xD02, NA, NA, "TaiShan v200",          UARCH_TAISHAN_V200, CPU_VENDOR_HUAWEI) // Kunpeng 930 series (found in openeuler: https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/XQCV7NX2UKRIUWUFKRF4PO3QENCOUFR3)
   CHECK_UARCH(arch, cpu, 'H', 0xD40, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)    // Kirin 980 Big/Medium cores -> Cortex-A76
+  CHECK_UARCH(arch, cpu, 'H', 0xD42, NA, NA, "TaiShan v120",          UARCH_TAISHAN_V120, CPU_VENDOR_HUAWEI) // Kiring 9000S Small Cores (https://github.com/Dr-Noob/cpufetch/issues/259)
 
   CHECK_UARCH(arch, cpu, 'N', 0x000, NA, NA, "Denver",                UARCH_DENVER,       CPU_VENDOR_NVIDIA)
   CHECK_UARCH(arch, cpu, 'N', 0x003, NA, NA, "Denver2",               UARCH_DENVER2,      CPU_VENDOR_NVIDIA)
@@ -291,7 +294,10 @@ int get_vpus_width(struct cpuInfo* cpu) {
     case UARCH_NEOVERSE_V1:
       return 256;
     default:
-      if(cpu->feat->NEON) {
+      if (cpu->feat->SVE && cpu->feat->cntb > 0) {
+        return cpu->feat->cntb * 8;
+      }
+      else if (cpu->feat->NEON) {
         if(is_ARMv8_or_newer(cpu)) {
           return 128;
         }
@@ -325,6 +331,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
     case UARCH_ICESTORM:    // [https://dougallj.github.io/applecpu/icestorm-simd.html]
     case UARCH_BLIZZARD:    // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
     case UARCH_TAISHAN_V110:// [https://www-file.huawei.com/-/media/corp2020/pdf/publications/huawei-research/2022/huawei-research-issue1-en.pdf]: "128-bit x 2 for single precision"
+    case UARCH_TAISHAN_V120:// Not confirmed, asssuming same as v110
     case UARCH_TAISHAN_V200:// Not confirmed, asssuming same as v110
     case UARCH_CORTEX_A57:  // [https://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/5]
     case UARCH_CORTEX_A72:  // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]

src/arm/uarch.h

@@ -83,7 +83,9 @@ enum {
   UARCH_BRAHMA_B15,
   UARCH_BRAHMA_B53,
   UARCH_XGENE,        // Applied Micro X-Gene.
+  // HUAWEI
   UARCH_TAISHAN_V110, // HiSilicon TaiShan v110
+  UARCH_TAISHAN_V120, // HiSilicon TaiShan v120
   UARCH_TAISHAN_V200, // HiSilicon TaiShan v200
   // PHYTIUM
   UARCH_XIAOMI,       // Not to be confused with Xiaomi Inc

src/common/ascii.h

@@ -394,6 +394,25 @@ $C2##   ##  ##   ##  ##  ##   ##  ##   #: :#    \
 $C2##   ##   ## ##   ##  ##   ##  ##  #######   \
 $C2##   ##    ###    ##  ######   ## ##     ##  "
 
+#define ASCII_AMPERE \
+"$C1                                                  \
+$C1                                                  \
+$C1                             ##                   \
+$C1                            ####                  \
+$C1                           ### ##                 \
+$C1                          ###   ###               \
+$C1                         ###     ###              \
+$C1                        ###        ###            \
+$C1                       ##           ###           \
+$C1                 #######   ###       ###          \
+$C1            ######  ##        ######   ###        \
+$C1        ####      ###              ########       \
+$C1      ####       ###                    ####      \
+$C1    ###         ###                       ####    \
+$C1  ##           ###                          ###   \
+$C1                                                  \
+$C1                                                  "
+
 // --------------------- LONG LOGOS ------------------------- //
 #define ASCII_AMD_L \
 "$C1                                                              \
@@ -569,6 +588,7 @@ asciiL logo_sifive      = { ASCII_SIFIVE,      48, 19, true,  {C_BG_WHITE, C_BG_
 asciiL logo_starfive    = { ASCII_STARFIVE,    33, 17, false, {C_FG_WHITE},                                   {C_FG_WHITE,   C_FG_BLUE}    };
 asciiL logo_sipeed      = { ASCII_SIPEED,      41, 16, true,  {C_BG_RED, C_BG_WHITE},                         {C_FG_RED,     C_FG_WHITE}   };
 asciiL logo_nvidia      = { ASCII_NVIDIA,      45, 19, false, {C_FG_GREEN, C_FG_WHITE},                       {C_FG_WHITE,   C_FG_GREEN}   };
+asciiL logo_ampere      = { ASCII_AMPERE,      50, 17, false, {C_FG_RED},                                     {C_FG_WHITE,   C_FG_RED}     };
 
 // Long variants          | ----------------------------------------------------------------------------------------------------------------|
 asciiL logo_amd_l       = { ASCII_AMD_L,       62, 19, true,  {C_BG_WHITE, C_BG_GREEN},                       {C_FG_WHITE, C_FG_GREEN}     };

src/common/cpu.h

@@ -45,9 +45,8 @@ enum {
 };
 
 enum {
-  CORE_TYPE_PERFORMANCE,
   CORE_TYPE_EFFICIENCY,
-  CORE_TYPE_LP_EFFICIENCY,
+  CORE_TYPE_PERFORMANCE,
   CORE_TYPE_UNKNOWN
 };
 
@@ -125,6 +124,9 @@ struct features {
   bool SHA1;
   bool SHA2;
   bool CRC32;
+  bool SVE;
+  bool SVE2;
+  uint64_t cntb;
 #endif  
 };
 

src/common/pci.c

@@ -14,14 +14,6 @@
 #define PCI_PATH "/sys/bus/pci/devices/"
 #define MAX_LENGTH_PCI_DIR_NAME 1024
 
-/*
- * doc: https://wiki.osdev.org/PCI#Class_Codes
- *      https://pci-ids.ucw.cz/read/PC
- */
-#define PCI_VENDOR_ID_AMD    0x1002
-#define CLASS_VGA_CONTROLLER 0x0300
-#define CLASS_3D_CONTROLLER  0x0302
-
 // Return a list of PCI devices containing only
 // the sysfs path
 struct pci_devices * get_pci_paths(void) {
@@ -126,43 +118,6 @@ void populate_pci_devices(struct pci_devices * pci) {
   }
 }
 
-// Right now, we are interested in PCI devices which
-// vendor is NVIDIA (to be extended in the future).
-// Should we also restrict to VGA controllers only?
-bool pci_device_is_useful(struct pci_device* dev) {
-  return dev->vendor_id == PCI_VENDOR_NVIDIA;
-}
-
-// Filter the input list in order to get only those PCI devices which 
-// we are interested in (decided by pci_device_is_useful)
-// and return the filtered result.
-struct pci_devices * filter_pci_devices(struct pci_devices * pci) {
-  int * devices_to_get = emalloc(sizeof(int) * pci->num_devices);
-  int dev_ptr = 0;
-
-  for (int i=0; i < pci->num_devices; i++) {
-    if (pci_device_is_useful(pci->devices[i])) {
-      devices_to_get[dev_ptr] = i;
-      dev_ptr++;
-    }
-  }
-
-  struct pci_devices * pci_filtered = emalloc(sizeof(struct pci_devices));
-  pci_filtered->num_devices = dev_ptr;
-
-  if (pci_filtered->num_devices == 0) {
-    pci_filtered->devices = NULL;
-  }
-  else {
-    pci_filtered->devices = emalloc(sizeof(struct pci_device) * pci_filtered->num_devices);  
-
-    for (int i=0; i < pci_filtered->num_devices; i++)
-      pci_filtered->devices[i] = pci->devices[devices_to_get[i]];
-  }
-
-  return pci_filtered;
-}
-
 // Return a list of PCI devices that could be used to infer the SoC.
 // The criteria to determine which devices are suitable for this task
 // is decided in filter_pci_devices.
@@ -174,5 +129,5 @@ struct pci_devices * get_pci_devices(void) {
 
   populate_pci_devices(pci);  
 
-  return filter_pci_devices(pci);
+  return pci;
 }

src/common/pci.h

@@ -2,7 +2,10 @@
 #define __PCI__
 
 #define PCI_VENDOR_NVIDIA   0x10de
+#define PCI_VENDOR_AMPERE   0x1def
+
 #define PCI_DEVICE_TEGRA_X1 0x0faf
+#define PCI_DEVICE_ALTRA    0xe100
 
 struct pci_device {
   char * path;

src/common/printer.c

@@ -389,6 +389,8 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
     art->art = &logo_allwinner;
   else if(art->vendor == SOC_VENDOR_ROCKCHIP)
     art->art = &logo_rockchip;
+  else if(art->vendor == SOC_VENDOR_AMPERE)
+    art->art = &logo_ampere;
   else if(art->vendor == SOC_VENDOR_NVIDIA)
     art->art = choose_ascii_art_aux(&logo_nvidia_l, &logo_nvidia, term, lf);
   else {
@@ -614,9 +616,8 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     }
 
     if(hybrid_architecture) {
-      if (ptr->core_type == CORE_TYPE_PERFORMANCE) sprintf(cpu_num, "P-cores:");
+      if(ptr->core_type == CORE_TYPE_EFFICIENCY) sprintf(cpu_num, "E-cores:");
-      else if (ptr->core_type == CORE_TYPE_EFFICIENCY) sprintf(cpu_num, "E-cores:");
+      else if(ptr->core_type == CORE_TYPE_PERFORMANCE) sprintf(cpu_num, "P-cores:");
-      else if (ptr->core_type == CORE_TYPE_LP_EFFICIENCY) sprintf(cpu_num, "LP-E-cores:");
       else printBug("Found invalid core type!\n");
 
       setAttribute(art, ATTRIBUTE_CPU_NUM, cpu_num);
@@ -635,10 +636,11 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     }
 
     // Show the most modern vector instructions.
-    // If AVX is supported show it, otherwise show SSE
     if (strcmp(avx, "No") == 0) {
+      if (strcmp(sse, "No") != 0) {
         setAttribute(art, ATTRIBUTE_SSE, sse);
       }
+    }
     else {
       setAttribute(art, ATTRIBUTE_AVX, avx);
       setAttribute(art, ATTRIBUTE_FMA, fma);

src/common/soc.c

@@ -21,6 +21,7 @@ static char* soc_trademark_string[] = {
   [SOC_VENDOR_ROCKCHIP]   = "Rockchip ",
   [SOC_VENDOR_GOOGLE]     = "Google ",
   [SOC_VENDOR_NVIDIA]     = "NVIDIA ",
+  [SOC_VENDOR_AMPERE]     = "Ampere ",
   // RISC-V
   [SOC_VENDOR_SIFIVE]     = "SiFive ",
   [SOC_VENDOR_STARFIVE]   = "StarFive ",

src/common/soc.h

@@ -25,6 +25,7 @@ enum {
   SOC_VENDOR_ROCKCHIP,
   SOC_VENDOR_GOOGLE,
   SOC_VENDOR_NVIDIA,
+  SOC_VENDOR_AMPERE,
   // RISC-V
   SOC_VENDOR_SIFIVE,
   SOC_VENDOR_STARFIVE,

src/x86/apic.c

@@ -91,7 +91,6 @@ int get_total_cores_module(int total_cores, int module) {
 
   while(!end) {
     if(!bind_to_cpu(i)) {
-      printBug("get_total_cores_module: Cannot bind to core %d", i);
       return -1;
     }
     uint32_t eax = 0x0000001A;
@@ -100,17 +99,6 @@ int get_total_cores_module(int total_cores, int module) {
     uint32_t edx = 0;
     cpuid(&eax, &ebx, &ecx, &edx);
     int32_t core_type = eax >> 24 & 0xFF;
-
-    // Here we artificially create a new core type for
-    // LP-E cores. In case the core has no L3 (on a hybrid)
-    // architecture, then we now it's an LP-E core.
-    eax = 0x4;
-    ebx = 0;
-    ecx = 0x3;
-    edx = 0;
-    cpuid(&eax, &ebx, &ecx, &edx);
-    core_type += eax == 0;
-
     bool found = false;
 
     for(int j=0; j < total_modules && !found; j++) {

src/x86/cpuid.c

@@ -137,31 +137,39 @@ bool abbreviate_intel_cpu_name(char** name) {
   char* new_name_ptr = new_name;
   char* aux_ptr = NULL;
 
-  // 1. Find "Intel(R)"
+  // 1. Remove "(R)"
   old_name_ptr = strstr(old_name_ptr, "Intel(R)");
   if(old_name_ptr == NULL) return false;
+  strcpy(new_name_ptr, "Intel");
+  new_name_ptr += strlen("Intel");
+  old_name_ptr += strlen("Intel(R)");
 
-  // 2. Search for "@"
+  // 2. Remove "(R)" or "(TM)"
+  aux_ptr = strstr(old_name_ptr, "(");
+  if(aux_ptr == NULL) return false;
+  strncpy(new_name_ptr, old_name_ptr, aux_ptr-old_name_ptr);
+
+  new_name_ptr += aux_ptr-old_name_ptr;
+  strcpy(new_name_ptr, " ");
+  new_name_ptr++;
+  old_name_ptr = strstr(aux_ptr, ")");
+  if(old_name_ptr == NULL) return false;
+  old_name_ptr++;
+  while(*old_name_ptr == ' ') old_name_ptr++;
+
+  // 3. Copy the CPU name
   aux_ptr = strstr(old_name_ptr, "@");
-  if(aux_ptr == NULL) {
+  if(aux_ptr == NULL) return false;
-    // New CPUs, copy end ptr is end of string
-    aux_ptr = old_name + strlen(old_name);
-    strncpy(new_name_ptr, old_name_ptr, (aux_ptr)-old_name_ptr);
-  }
-  else {
-    // Copy end ptr is "@"
   strncpy(new_name_ptr, old_name_ptr, (aux_ptr-1)-old_name_ptr);
-  }
 
-  // 3. Remove dummy strings in Intel CPU names
+  // 4. Remove dummy strings in Intel CPU names
-  strremove(new_name, "(R)");
-  strremove(new_name, "(TM)");
   strremove(new_name, " CPU");
   strremove(new_name, " Dual");
   strremove(new_name, " 0");
 
   free(old_name);
   *name = new_name;
+
   return true;
 }
 
@@ -389,17 +397,6 @@ bool set_cpu_module(int m, int total_modules, int32_t* first_core) {
       uint32_t edx = 0;
       cpuid(&eax, &ebx, &ecx, &edx);
       int32_t core_type = eax >> 24 & 0xFF;
-
-      // Here we artificially create a new core type for
-      // LP-E cores. In case the core has no L3 (on a hybrid)
-      // architecture, then we now it's an LP-E core.
-      eax = 0x4;
-      ebx = 0;
-      ecx = 0x3;
-      edx = 0;
-      cpuid(&eax, &ebx, &ecx, &edx);
-      core_type += eax == 0;
-
       bool found = false;
 
       for(int j=0; j < total_modules && !found; j++) {
@@ -426,19 +423,13 @@ bool set_cpu_module(int m, int total_modules, int32_t* first_core) {
     #endif
   }
   else {
-    // This is a non-hybrid architecture
+    // This is a normal architecture
     *first_core = 0;
   }
 
   return true;
 }
 
-// Difference between E and LP-E cores:
-// According to Intel Core Ultra Processor Datasheet Volume 1 of 2
-// (https://www.intel.com/content/www/us/en/content-details/792044/intel-core-ultra-processor-datasheet-volume-1-of-2.html),
-// LP-E cores do not have L3 cache. This seems to be the only way of differentiating them.
-// - https://community.intel.com/t5/Processors/Detecting-LP-E-Cores-on-Meteor-Lake-in-software/m-p/1584555/highlight/true#M70732
-// - https://x.com/InstLatX64/status/1741416428538941718
 int32_t get_core_type(void) {
   uint32_t eax = 0x0000001A;
   uint32_t ebx = 0;
@@ -449,26 +440,8 @@ int32_t get_core_type(void) {
   cpuid(&eax, &ebx, &ecx, &edx);
 
   int32_t type = eax >> 24 & 0xFF;
-  if (type == 0x40) return CORE_TYPE_PERFORMANCE;
+  if(type == 0x20) return CORE_TYPE_EFFICIENCY;
-  else if (type == 0x20) {
+  else if(type == 0x40) return CORE_TYPE_PERFORMANCE;
-    // get_core_type is only called iff hybrid_flag is true, which can only
-    // happen if CPUID maxLevel >= 0x7 so we can assume the CPU supports
-    // CPUID leaf 0x4
-    eax = 0x4;
-    ebx = 0;
-    ecx = 0x3;
-    edx = 0;
-
-    cpuid(&eax, &ebx, &ecx, &edx);
-
-    if (eax == 0) {
-      // No L3 access, this is LP-E
-      return CORE_TYPE_LP_EFFICIENCY;
-    }
-    else {
-      return CORE_TYPE_EFFICIENCY;
-    }
-  }
   else {
     printErr("Found invalid core type: 0x%.8X\n", type);
     return CORE_TYPE_UNKNOWN;
@@ -483,6 +456,7 @@ struct cpuInfo* get_cpu_info(void) {
   cpu->cach = NULL;
   cpu->feat = NULL;
 
+  cpu->num_cpus = 1;
   uint32_t eax = 0;
   uint32_t ebx = 0;
   uint32_t ecx = 0;
@@ -540,13 +514,7 @@ struct cpuInfo* get_cpu_info(void) {
     cpu->hybrid_flag = (edx >> 15) & 0x1;
   }
 
-  if(cpu->hybrid_flag) {
+  if(cpu->hybrid_flag) cpu->num_cpus = 2;
-    struct uarch* tmp = get_cpu_uarch(cpu);
-    cpu->num_cpus = get_hybrid_num_cpus(tmp);
-  }
-  else {
-    cpu->num_cpus = 1;
-  }
 
   struct cpuInfo* ptr = cpu;
   for(uint32_t i=0; i < cpu->num_cpus; i++) {
@@ -561,9 +529,8 @@ struct cpuInfo* get_cpu_info(void) {
       ptr->topo = NULL;
       ptr->cach = NULL;
       ptr->feat = NULL;
-      // We assume that this core has the
+      // We assume that this cores have the
-      // same cpuid capabilities as the core in the
+      // same cpuid capabilities
-      // first module
       ptr->cpu_vendor = cpu->cpu_vendor;
       ptr->maxLevels = cpu->maxLevels;
       ptr->maxExtendedLevels = cpu->maxExtendedLevels;
@@ -733,8 +700,6 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
   if(cpu->hybrid_flag) {
     #ifdef __linux__
       topo->total_cores_module = get_total_cores_module(topo->total_cores, module);
-      printBug("get_total_cores_module: Failed to get number of cores in module");
-      return NULL;
     #else
       UNUSED(module);
       topo->total_cores_module = topo->total_cores;
@@ -744,9 +709,9 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
     topo->total_cores_module = topo->total_cores;
   }
 
+  bool toporet = false;
   switch(cpu->cpu_vendor) {
     case CPU_VENDOR_INTEL:
-      bool toporet = false;
       if (cpu->maxLevels >= 0x00000004) {
         toporet = get_topology_from_apic(cpu, topo);
       }
@@ -785,10 +750,15 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
         }
       }
       else {
+        #ifdef __linux__
+          printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X), using udev...", 0x80000008, cpu->maxExtendedLevels);
+          get_topology_from_udev(topo);
+        #else
           printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000008, cpu->maxExtendedLevels);
           topo->physical_cores = 1;
           topo->logical_cores = 1;
           topo->smt_supported = 1;
+        #endif
       }
 
       if (cpu->maxLevels >= 0x00000001) {
@@ -1131,8 +1101,14 @@ char* get_str_sse(struct cpuInfo* cpu) {
       last+=SSE4_2_sl;
   }
 
+  if (last == 0) {
+    snprintf(string, 2+1, "No");
+  }
+  else {
     //Purge last comma
     string[last-1] = '\0';
+  }
+
   return string;
 }
 

src/x86/uarch.c

@@ -94,7 +94,6 @@ enum {
   UARCH_TIGER_LAKE,
   UARCH_ALDER_LAKE,
   UARCH_RAPTOR_LAKE,
-  UARCH_METEOR_LAKE,
   // AMD //
   UARCH_AM486,
   UARCH_AM5X86,
@@ -249,7 +248,6 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 0,  6, 10,  5, NA, "Comet Lake",        UARCH_COMET_LAKE,       14) // wikichip
   CHECK_UARCH(arch, 0,  6, 10,  6, NA, "Comet Lake",        UARCH_COMET_LAKE,       14) // instlatx64.atw.hu (i7-10710U)
   CHECK_UARCH(arch, 0,  6, 10,  7, NA, "Rocket Lake",       UARCH_ROCKET_LAKE,      14) // instlatx64.atw.hu (i7-11700K)
-  CHECK_UARCH(arch, 0,  6, 10, 10, NA, "Meteor Lake",       UARCH_METEOR_LAKE,       7) // instlatx64.atw.hu (Ultra 7 155H)
   CHECK_UARCH(arch, 0,  6, 11,  7, NA, "Raptor Lake",       UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i5-13600K)
   CHECK_UARCH(arch, 0,  6, 11, 10, NA, "Raptor Lake",       UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i7-1370P)
   CHECK_UARCH(arch, 0,  6, 11, 14, NA, "Alder Lake",        UARCH_ALDER_LAKE,       10) // instlatx64.atw.hu (Alder Lake-N)
@@ -538,7 +536,6 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
       case UARCH_TIGER_LAKE:
       case UARCH_ALDER_LAKE:
       case UARCH_RAPTOR_LAKE:
-      case UARCH_METEOR_LAKE:
 
       // AMD
       case UARCH_ZEN2:
@@ -552,11 +549,6 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
   }
 }
 
-uint32_t get_hybrid_num_cpus(struct uarch* arch) {
-  if (arch->uarch == UARCH_METEOR_LAKE) return 3;
-  else return 2;
-}
-
 bool choose_new_intel_logo_uarch(struct cpuInfo* cpu) {
   switch(cpu->arch->uarch) {
     case UARCH_ALDER_LAKE:

src/x86/uarch.h

@@ -12,7 +12,6 @@ char* infer_cpu_name_from_uarch(struct uarch* arch);
 bool vpus_are_AVX512(struct cpuInfo* cpu);
 bool is_knights_landing(struct cpuInfo* cpu);
 int get_number_of_vpus(struct cpuInfo* cpu);
-uint32_t get_hybrid_num_cpus(struct uarch* arch);
 bool choose_new_intel_logo_uarch(struct cpuInfo* cpu);
 char* get_str_uarch(struct cpuInfo* cpu);
 char* get_str_process(struct cpuInfo* cpu);