Quick test

Makefile

@@ -38,10 +38,16 @@ ifneq ($(OS),Windows_NT)
 		CFLAGS += -DARCH_PPC -std=gnu99 -fstack-protector-all -Wno-language-extension-token
 	else ifeq ($(arch), $(filter $(arch), arm aarch64_be aarch64 arm64 armv8b armv8l armv7l armv6l))
 		SRC_DIR=src/arm/
-		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_COMMON)pci.c $(SRC_DIR)udev.c
+		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_COMMON)pci.c $(SRC_DIR)udev.c sve.o
 		HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h  $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_COMMON)pci.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
 		CFLAGS += -DARCH_ARM -Wno-unused-parameter -std=c99 -fstack-protector-all
 
+		# Check if the compiler supports -march=armv8-a+sve. We will use it (if supported) to compile SVE detection code later
+		is_sve_flag_supported := $(shell $(CC) -march=armv8-a+sve -c $(SRC_DIR)sve.c -o sve_test.o 2> /dev/null && echo 'yes'; rm -f sve_test.o)
+		ifeq ($(is_sve_flag_supported), yes)
+			SVE_FLAGS += -march=armv8-a+sve
+		endif
+
 		ifeq ($(os), Darwin)
 			SOURCE += $(SRC_COMMON)sysctl.c
 			HEADERS += $(SRC_COMMON)sysctl.h
@@ -91,6 +97,9 @@ freq_avx.o: Makefile $(SRC_DIR)freq/freq_avx.c $(SRC_DIR)freq/freq_avx.h $(SRC_D
 freq_avx512.o: Makefile $(SRC_DIR)freq/freq_avx512.c $(SRC_DIR)freq/freq_avx512.h $(SRC_DIR)freq/freq.h
 	$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -mavx512f -pthread $(SRC_DIR)freq/freq_avx512.c -o $@
 
+sve.o: Makefile $(SRC_DIR)sve.c $(SRC_DIR)sve.h
+	$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SVE_FLAGS) -c $(SRC_DIR)sve.c -o $@
+
 $(OUTPUT): Makefile $(SOURCE) $(HEADERS)
 ifeq ($(GIT_VERSION),"")
 	$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SOURCE) -o $(OUTPUT)

src/arm/midr.c

@@ -19,6 +19,7 @@
 #include "udev.h"
 #include "midr.h"
 #include "uarch.h"
+#include "sve.h"
 
 bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
   return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
@@ -168,6 +169,15 @@ struct features* get_features_info(void) {
     feat->SHA1 = hwcaps & HWCAP_SHA1;
     feat->SHA2 = hwcaps & HWCAP_SHA2;
     feat->NEON = hwcaps & HWCAP_ASIMD;
+    feat->SVE = hwcaps & HWCAP_SVE;
+
+    hwcaps = getauxval(AT_HWCAP2);
+    if (errno == ENOENT) {
+      printWarn("Unable to retrieve AT_HWCAP2 using getauxval");
+    }
+    else {
+      feat->SVE2 = hwcaps & HWCAP2_SVE2;
+    }
   }
 #else
   else {
@@ -183,6 +193,8 @@ struct features* get_features_info(void) {
     feat->CRC32 = hwcaps & HWCAP2_CRC32;
     feat->SHA1 = hwcaps & HWCAP2_SHA1;
     feat->SHA2 = hwcaps & HWCAP2_SHA2;
+    feat->SVE = false;
+    feat->SVE2 = false;
   }
 #endif // ifdef __aarch64__
 #elif defined __APPLE__ || __MACH__
@@ -192,8 +204,14 @@ struct features* get_features_info(void) {
   feat->SHA1 = true;
   feat->SHA2 = true;
   feat->NEON = true;
+  feat->SVE = false;
+  feat->SVE2 = false;
 #endif  // ifdef __linux__
 
+  if (feat->SVE || feat->SVE2) {
+    feat->cntb = sve_cntb();
+  }
+
   return feat;
 }
 
@@ -413,6 +431,8 @@ struct cpuInfo* get_cpu_info(void) {
   struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
   init_cpu_info(cpu);
 
+  test_thread_siblings_list();
+
   #ifdef __linux__
     return get_cpu_info_linux(cpu);
   #elif defined __APPLE__ || __MACH__
@@ -430,7 +450,7 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_soc
 
 char* get_str_features(struct cpuInfo* cpu) {
   struct features* feat = cpu->feat;
-  uint32_t max_len = strlen("NEON,SHA1,SHA2,AES,CRC32,") + 1;
+  uint32_t max_len = strlen("NEON,SHA1,SHA2,AES,CRC32,SVE,SVE2") + 1;
   uint32_t len = 0;
   char* string = ecalloc(max_len, sizeof(char));
 
@@ -438,6 +458,14 @@ char* get_str_features(struct cpuInfo* cpu) {
     strcat(string, "NEON,");
     len += 5;
   }
+  if(feat->SVE) {
+    strcat(string, "SVE,");
+    len += 4;
+  }
+  if(feat->SVE2) {
+    strcat(string, "SVE2,");
+    len += 5;
+  }
   if(feat->SHA1) {
     strcat(string, "SHA1,");
     len += 5;

src/arm/soc.c

@@ -167,11 +167,13 @@ bool match_google(char* soc_name, struct system_on_chip* soc) {
 
 // https://www.techinsights.com/
 // https://datasheetspdf.com/pdf-file/1316605/HiSilicon/Hi3660/1
+// https://github.com/Dr-Noob/cpufetch/issues/259
 bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
   char* tmp;
 
-  if((tmp = strstr(soc_name, "hi")) == NULL)
-    return false;
+  if((tmp = strstr(soc_name, "hi")) != NULL);
+  else if((tmp = strstr(soc_name, "kirin")) != NULL);
+  else return false;
 
   soc->soc_vendor = SOC_VENDOR_KIRIN;
 
@@ -204,6 +206,7 @@ bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "hi3680",     "980",   SOC_HISILICON_3680, soc,  7)
   //SOC_EQ(tmp, "?",        "985",   SOC_KIRIN, soc,  7)
   SOC_EQ(tmp, "hi3690",     "990",   SOC_HISILICON_3690, soc,  7)
+  SOC_EQ(tmp, "kirin9000s", "9000s", SOC_HISILICON_9000S,soc,  7)
   SOC_END
 }
 

src/arm/socs.h

@@ -29,6 +29,7 @@ enum {
   SOC_HISILICON_3670,
   SOC_HISILICON_3680,
   SOC_HISILICON_3690,
+  SOC_HISILICON_9000S,
   // Kunpeng //
   SOC_KUNPENG_920,
   SOC_KUNPENG_930,
@@ -377,7 +378,7 @@ enum {
 
 inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
   if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_2712) return SOC_VENDOR_BROADCOM;
-  else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_3690) return SOC_VENDOR_KIRIN;
+  else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_9000S) return SOC_VENDOR_KIRIN;
   else if(soc >= SOC_KUNPENG_920 && soc <= SOC_KUNPENG_930) return SOC_VENDOR_KUNPENG;
   else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
   else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;

src/arm/sve.c

@@ -0,0 +1,16 @@
+#include <stdint.h>
+#include "../common/global.h"
+
+// https://learn.arm.com/learning-paths/servers-and-cloud-computing/sve/sve_basics/#:~:text=Using%20a%20text%20editor%20of%20your%20choice%2C%20copy,svcntb%28%29%29%3B%20%7D%20This%20program%20prints%20the%20vector%20length
+uint64_t sve_cntb(void) {
+  #ifdef __ARM_FEATURE_SVE
+    uint64_t x0 = 0;
+    __asm volatile("cntb %0"
+         : "=r"(x0));
+    printf("cntb=%ld\n", x0);
+    return x0;
+  #else
+    printWarn("sve_cntb: SVE not enabled by the compiler");
+    return 0;
+  #endif
+}

src/arm/sve.h

@@ -0,0 +1,6 @@
+#ifndef __SVE_DETECTION__
+#define __SVE_DETECTION__
+
+uint64_t sve_cntb(void);
+
+#endif

src/arm/uarch.c

@@ -75,6 +75,7 @@ static const ISA isas_uarch[] = {
   [UARCH_THUNDERX]     = ISA_ARMv8_A,
   [UARCH_THUNDERX2]    = ISA_ARMv8_1_A,
   [UARCH_TAISHAN_V110] = ISA_ARMv8_2_A,
+  [UARCH_TAISHAN_V120] = ISA_ARMv8_2_A, // Not confirmed
   [UARCH_TAISHAN_V200] = ISA_ARMv8_2_A, // Not confirmed
   [UARCH_DENVER]       = ISA_ARMv8_A,
   [UARCH_DENVER2]      = ISA_ARMv8_A,
@@ -202,8 +203,10 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   CHECK_UARCH(arch, cpu, 'C', 0x0AF, NA, NA, "ThunderX2 99XX",        UARCH_THUNDERX2,    CPU_VENDOR_CAVIUM)
 
   CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110",          UARCH_TAISHAN_V110, CPU_VENDOR_HUAWEI) // Kunpeng 920 series
+  CHECK_UARCH(arch, cpu, 'H', 0xD02,  2,  2, "TaiShan v120",          UARCH_TAISHAN_V120, CPU_VENDOR_HUAWEI) // Kiring 9000S Big cores (https://github.com/Dr-Noob/cpufetch/issues/259)
   CHECK_UARCH(arch, cpu, 'H', 0xD02, NA, NA, "TaiShan v200",          UARCH_TAISHAN_V200, CPU_VENDOR_HUAWEI) // Kunpeng 930 series (found in openeuler: https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/XQCV7NX2UKRIUWUFKRF4PO3QENCOUFR3)
   CHECK_UARCH(arch, cpu, 'H', 0xD40, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)    // Kirin 980 Big/Medium cores -> Cortex-A76
+  CHECK_UARCH(arch, cpu, 'H', 0xD42, NA, NA, "TaiShan v120",          UARCH_TAISHAN_V120, CPU_VENDOR_HUAWEI) // Kiring 9000S Small Cores (https://github.com/Dr-Noob/cpufetch/issues/259)
 
   CHECK_UARCH(arch, cpu, 'N', 0x000, NA, NA, "Denver",                UARCH_DENVER,       CPU_VENDOR_NVIDIA)
   CHECK_UARCH(arch, cpu, 'N', 0x003, NA, NA, "Denver2",               UARCH_DENVER2,      CPU_VENDOR_NVIDIA)
@@ -291,7 +294,10 @@ int get_vpus_width(struct cpuInfo* cpu) {
     case UARCH_NEOVERSE_V1:
       return 256;
     default:
-      if(cpu->feat->NEON) {
+      if (cpu->feat->SVE && cpu->feat->cntb > 0) {
+        return cpu->feat->cntb * 8;
+      }
+      else if (cpu->feat->NEON) {
         if(is_ARMv8_or_newer(cpu)) {
           return 128;
         }
@@ -325,6 +331,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
     case UARCH_ICESTORM:    // [https://dougallj.github.io/applecpu/icestorm-simd.html]
     case UARCH_BLIZZARD:    // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
     case UARCH_TAISHAN_V110:// [https://www-file.huawei.com/-/media/corp2020/pdf/publications/huawei-research/2022/huawei-research-issue1-en.pdf]: "128-bit x 2 for single precision"
+    case UARCH_TAISHAN_V120:// Not confirmed, asssuming same as v110
     case UARCH_TAISHAN_V200:// Not confirmed, asssuming same as v110
     case UARCH_CORTEX_A57:  // [https://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/5]
     case UARCH_CORTEX_A72:  // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]

src/arm/uarch.h

@@ -83,7 +83,9 @@ enum {
   UARCH_BRAHMA_B15,
   UARCH_BRAHMA_B53,
   UARCH_XGENE,        // Applied Micro X-Gene.
+  // HUAWEI
   UARCH_TAISHAN_V110, // HiSilicon TaiShan v110
+  UARCH_TAISHAN_V120, // HiSilicon TaiShan v120
   UARCH_TAISHAN_V200, // HiSilicon TaiShan v200
   // PHYTIUM
   UARCH_XIAOMI,       // Not to be confused with Xiaomi Inc

src/common/cpu.h

@@ -45,9 +45,8 @@ enum {
 };
 
 enum {
-  CORE_TYPE_PERFORMANCE,
   CORE_TYPE_EFFICIENCY,
-  CORE_TYPE_LP_EFFICIENCY,
+  CORE_TYPE_PERFORMANCE,
   CORE_TYPE_UNKNOWN
 };
 
@@ -125,6 +124,9 @@ struct features {
   bool SHA1;
   bool SHA2;
   bool CRC32;
+  bool SVE;
+  bool SVE2;
+  uint32_t cntb;
 #endif  
 };
 

src/common/printer.c

@@ -614,9 +614,8 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     }
 
     if(hybrid_architecture) {
-      if (ptr->core_type == CORE_TYPE_PERFORMANCE) sprintf(cpu_num, "P-cores:");
-      else if (ptr->core_type == CORE_TYPE_EFFICIENCY) sprintf(cpu_num, "E-cores:");
-      else if (ptr->core_type == CORE_TYPE_LP_EFFICIENCY) sprintf(cpu_num, "LP-E-cores:");
+      if(ptr->core_type == CORE_TYPE_EFFICIENCY) sprintf(cpu_num, "E-cores:");
+      else if(ptr->core_type == CORE_TYPE_PERFORMANCE) sprintf(cpu_num, "P-cores:");
       else printBug("Found invalid core type!\n");
 
       setAttribute(art, ATTRIBUTE_CPU_NUM, cpu_num);

src/common/udev.c

@@ -315,6 +315,24 @@ int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level) {
   return ret;
 }
 
+// Just to check what is going on with missing thread_siblings_list
+void test_thread_siblings_list(void) {
+  int num_cores = 12;
+  int filelen;
+  char* buf = NULL;
+
+  for(int i=0; i < num_cores; i++) {
+    char* path = ecalloc(500, sizeof(char));
+    sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", i);
+
+    if((buf = read_file(path, &filelen)) == NULL) {
+      printf("Could not open '%s'", path);      
+    }
+
+    printf("%s: %s\n", path, buf);
+  }
+}
+
 int get_num_sockets_package_cpus(struct topology* topo) {
   // Get number of sockets using
   // /sys/devices/system/cpu/cpu*/topology/package_cpus

src/common/udev.h

@@ -43,5 +43,6 @@ int get_num_sockets_package_cpus(struct topology* topo);
 int get_ncores_from_cpuinfo(void);
 char* get_field_from_cpuinfo(char* CPUINFO_FIELD);
 bool is_devtree_compatible(char* str);
+void test_thread_siblings_list(void);
 
 #endif

src/x86/apic.c

@@ -91,7 +91,6 @@ int get_total_cores_module(int total_cores, int module) {
 
   while(!end) {
     if(!bind_to_cpu(i)) {
-      printBug("get_total_cores_module: Cannot bind to core %d", i);
       return -1;
     }
     uint32_t eax = 0x0000001A;
@@ -100,17 +99,6 @@ int get_total_cores_module(int total_cores, int module) {
     uint32_t edx = 0;
     cpuid(&eax, &ebx, &ecx, &edx);
     int32_t core_type = eax >> 24 & 0xFF;
-
-    // Here we artificially create a new core type for
-    // LP-E cores. In case the core has no L3 (on a hybrid)
-    // architecture, then we now it's an LP-E core.
-    eax = 0x4;
-    ebx = 0;
-    ecx = 0x3;
-    edx = 0;
-    cpuid(&eax, &ebx, &ecx, &edx);
-    core_type += eax == 0;
-
     bool found = false;
 
     for(int j=0; j < total_modules && !found; j++) {

src/x86/cpuid.c

@@ -137,31 +137,39 @@ bool abbreviate_intel_cpu_name(char** name) {
   char* new_name_ptr = new_name;
   char* aux_ptr = NULL;
 
-  // 1. Find "Intel(R)"
+  // 1. Remove "(R)"
   old_name_ptr = strstr(old_name_ptr, "Intel(R)");
   if(old_name_ptr == NULL) return false;
+  strcpy(new_name_ptr, "Intel");
+  new_name_ptr += strlen("Intel");
+  old_name_ptr += strlen("Intel(R)");
 
-  // 2. Search for "@"
+  // 2. Remove "(R)" or "(TM)"
+  aux_ptr = strstr(old_name_ptr, "(");
+  if(aux_ptr == NULL) return false;
+  strncpy(new_name_ptr, old_name_ptr, aux_ptr-old_name_ptr);
+
+  new_name_ptr += aux_ptr-old_name_ptr;
+  strcpy(new_name_ptr, " ");
+  new_name_ptr++;
+  old_name_ptr = strstr(aux_ptr, ")");
+  if(old_name_ptr == NULL) return false;
+  old_name_ptr++;
+  while(*old_name_ptr == ' ') old_name_ptr++;
+
+  // 3. Copy the CPU name
   aux_ptr = strstr(old_name_ptr, "@");
-  if(aux_ptr == NULL) {
-    // New CPUs, copy end ptr is end of string
-    aux_ptr = old_name + strlen(old_name);
-    strncpy(new_name_ptr, old_name_ptr, (aux_ptr)-old_name_ptr);
-  }
-  else {
-    // Copy end ptr is "@"
-    strncpy(new_name_ptr, old_name_ptr, (aux_ptr-1)-old_name_ptr);
-  }
+  if(aux_ptr == NULL) return false;
+  strncpy(new_name_ptr, old_name_ptr, (aux_ptr-1)-old_name_ptr);
 
-  // 3. Remove dummy strings in Intel CPU names
-  strremove(new_name, "(R)");
-  strremove(new_name, "(TM)");
+  // 4. Remove dummy strings in Intel CPU names
   strremove(new_name, " CPU");
   strremove(new_name, " Dual");
   strremove(new_name, " 0");
 
   free(old_name);
   *name = new_name;
+
   return true;
 }
 
@@ -389,17 +397,6 @@ bool set_cpu_module(int m, int total_modules, int32_t* first_core) {
       uint32_t edx = 0;
       cpuid(&eax, &ebx, &ecx, &edx);
       int32_t core_type = eax >> 24 & 0xFF;
-
-      // Here we artificially create a new core type for
-      // LP-E cores. In case the core has no L3 (on a hybrid)
-      // architecture, then we now it's an LP-E core.
-      eax = 0x4;
-      ebx = 0;
-      ecx = 0x3;
-      edx = 0;
-      cpuid(&eax, &ebx, &ecx, &edx);
-      core_type += eax == 0;
-
       bool found = false;
 
       for(int j=0; j < total_modules && !found; j++) {
@@ -426,19 +423,13 @@ bool set_cpu_module(int m, int total_modules, int32_t* first_core) {
     #endif
   }
   else {
-    // This is a non-hybrid architecture
+    // This is a normal architecture
     *first_core = 0;
   }
 
   return true;
 }
 
-// Difference between E and LP-E cores:
-// According to Intel Core Ultra Processor Datasheet Volume 1 of 2
-// (https://www.intel.com/content/www/us/en/content-details/792044/intel-core-ultra-processor-datasheet-volume-1-of-2.html),
-// LP-E cores do not have L3 cache. This seems to be the only way of differentiating them.
-// - https://community.intel.com/t5/Processors/Detecting-LP-E-Cores-on-Meteor-Lake-in-software/m-p/1584555/highlight/true#M70732
-// - https://x.com/InstLatX64/status/1741416428538941718
 int32_t get_core_type(void) {
   uint32_t eax = 0x0000001A;
   uint32_t ebx = 0;
@@ -449,26 +440,8 @@ int32_t get_core_type(void) {
   cpuid(&eax, &ebx, &ecx, &edx);
 
   int32_t type = eax >> 24 & 0xFF;
-  if (type == 0x40) return CORE_TYPE_PERFORMANCE;
-  else if (type == 0x20) {
-    // get_core_type is only called iff hybrid_flag is true, which can only
-    // happen if CPUID maxLevel >= 0x7 so we can assume the CPU supports
-    // CPUID leaf 0x4
-    eax = 0x4;
-    ebx = 0;
-    ecx = 0x3;
-    edx = 0;
-
-    cpuid(&eax, &ebx, &ecx, &edx);
-
-    if (eax == 0) {
-      // No L3 access, this is LP-E
-      return CORE_TYPE_LP_EFFICIENCY;
-    }
-    else {
-      return CORE_TYPE_EFFICIENCY;
-    }
-  }
+  if(type == 0x20) return CORE_TYPE_EFFICIENCY;
+  else if(type == 0x40) return CORE_TYPE_PERFORMANCE;
   else {
     printErr("Found invalid core type: 0x%.8X\n", type);
     return CORE_TYPE_UNKNOWN;
@@ -483,6 +456,7 @@ struct cpuInfo* get_cpu_info(void) {
   cpu->cach = NULL;
   cpu->feat = NULL;
 
+  cpu->num_cpus = 1;
   uint32_t eax = 0;
   uint32_t ebx = 0;
   uint32_t ecx = 0;
@@ -540,13 +514,7 @@ struct cpuInfo* get_cpu_info(void) {
     cpu->hybrid_flag = (edx >> 15) & 0x1;
   }
 
-  if(cpu->hybrid_flag) {
-    struct uarch* tmp = get_cpu_uarch(cpu);
-    cpu->num_cpus = get_hybrid_num_cpus(tmp);
-  }
-  else {
-    cpu->num_cpus = 1;
-  }
+  if(cpu->hybrid_flag) cpu->num_cpus = 2;
 
   struct cpuInfo* ptr = cpu;
   for(uint32_t i=0; i < cpu->num_cpus; i++) {
@@ -561,9 +529,8 @@ struct cpuInfo* get_cpu_info(void) {
       ptr->topo = NULL;
       ptr->cach = NULL;
       ptr->feat = NULL;
-      // We assume that this core has the
-      // same cpuid capabilities as the core in the
-      // first module
+      // We assume that this cores have the
+      // same cpuid capabilities
       ptr->cpu_vendor = cpu->cpu_vendor;
       ptr->maxLevels = cpu->maxLevels;
       ptr->maxExtendedLevels = cpu->maxExtendedLevels;
@@ -733,8 +700,6 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
   if(cpu->hybrid_flag) {
     #ifdef __linux__
       topo->total_cores_module = get_total_cores_module(topo->total_cores, module);
-      printBug("get_total_cores_module: Failed to get number of cores in module");
-      return NULL;
     #else
       UNUSED(module);
       topo->total_cores_module = topo->total_cores;

src/x86/uarch.c

@@ -94,7 +94,6 @@ enum {
   UARCH_TIGER_LAKE,
   UARCH_ALDER_LAKE,
   UARCH_RAPTOR_LAKE,
-  UARCH_METEOR_LAKE,
   // AMD //
   UARCH_AM486,
   UARCH_AM5X86,
@@ -249,7 +248,6 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 0,  6, 10,  5, NA, "Comet Lake",        UARCH_COMET_LAKE,       14) // wikichip
   CHECK_UARCH(arch, 0,  6, 10,  6, NA, "Comet Lake",        UARCH_COMET_LAKE,       14) // instlatx64.atw.hu (i7-10710U)
   CHECK_UARCH(arch, 0,  6, 10,  7, NA, "Rocket Lake",       UARCH_ROCKET_LAKE,      14) // instlatx64.atw.hu (i7-11700K)
-  CHECK_UARCH(arch, 0,  6, 10, 10, NA, "Meteor Lake",       UARCH_METEOR_LAKE,       7) // instlatx64.atw.hu (Ultra 7 155H)
   CHECK_UARCH(arch, 0,  6, 11,  7, NA, "Raptor Lake",       UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i5-13600K)
   CHECK_UARCH(arch, 0,  6, 11, 10, NA, "Raptor Lake",       UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i7-1370P)
   CHECK_UARCH(arch, 0,  6, 11, 14, NA, "Alder Lake",        UARCH_ALDER_LAKE,       10) // instlatx64.atw.hu (Alder Lake-N)
@@ -538,7 +536,6 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
       case UARCH_TIGER_LAKE:
       case UARCH_ALDER_LAKE:
       case UARCH_RAPTOR_LAKE:
-      case UARCH_METEOR_LAKE:
 
       // AMD
       case UARCH_ZEN2:
@@ -552,11 +549,6 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
   }
 }
 
-uint32_t get_hybrid_num_cpus(struct uarch* arch) {
-  if (arch->uarch == UARCH_METEOR_LAKE) return 3;
-  else return 2;
-}
-
 bool choose_new_intel_logo_uarch(struct cpuInfo* cpu) {
   switch(cpu->arch->uarch) {
     case UARCH_ALDER_LAKE:

src/x86/uarch.h

@@ -12,7 +12,6 @@ char* infer_cpu_name_from_uarch(struct uarch* arch);
 bool vpus_are_AVX512(struct cpuInfo* cpu);
 bool is_knights_landing(struct cpuInfo* cpu);
 int get_number_of_vpus(struct cpuInfo* cpu);
-uint32_t get_hybrid_num_cpus(struct uarch* arch);
 bool choose_new_intel_logo_uarch(struct cpuInfo* cpu);
 char* get_str_uarch(struct cpuInfo* cpu);
 char* get_str_process(struct cpuInfo* cpu);