[v1.04][ARM] Experimental topology detection for Apple SoCs

Makefile

@@ -1,7 +1,7 @@
 CC ?= gcc
 
 CFLAGS+=-Wall -Wextra -pedantic
-SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith
+SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-prototypes
 
 PREFIX ?= /usr
 
@@ -32,8 +32,8 @@ ifneq ($(OS),Windows_NT)
 		CFLAGS += -DARCH_PPC -std=gnu99 -fstack-protector-all -Wno-language-extension-token
 	else ifeq ($(arch), $(filter $(arch), arm aarch64_be aarch64 arm64 armv8b armv8l armv7l armv6l))
 		SRC_DIR=src/arm/
-		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
-		HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h  $(SRC_DIR)soc.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
+		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
+		HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h  $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
 		CFLAGS += -DARCH_ARM -Wno-unused-parameter -std=c99 -fstack-protector-all
 
 		os := $(shell uname -s)
@@ -43,8 +43,8 @@ ifneq ($(OS),Windows_NT)
 		endif
         else ifeq ($(arch), $(filter $(arch), riscv64 riscv32))
                 SRC_DIR=src/riscv/
-                SOURCE += $(COMMON_SRC) $(SRC_DIR)riscv.c $(SRC_DIR)uarch.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
-                HEADERS += $(COMMON_SRC) $(SRC_DIR)riscv.h $(SRC_DIR)uarch.h $(SRC_DIR)soc.h $(SRC_DIR)udev.h $(SRC_DIR)socs.h
+                SOURCE += $(COMMON_SRC) $(SRC_DIR)riscv.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
+                HEADERS += $(COMMON_HDR) $(SRC_DIR)riscv.h $(SRC_DIR)uarch.h $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_DIR)udev.h $(SRC_DIR)socs.h
                 CFLAGS += -DARCH_RISCV -Wno-unused-parameter -std=c99 -fstack-protector-all
 	else
 		# Error lines should not be tabulated because Makefile complains about it

README.md

@@ -50,6 +50,8 @@ cpufetch is a command-line tool written in C that displays the CPU information i
   - [4.2 Specifying the colors in RGB format](#42-specifying-the-colors-in-rgb-format)
 - [5. Implementation](#5-implementation)
 - [6. Bugs or improvements](#6-bugs-or-improvements)
+  - [6.1 Unknown microarchitecture error](#61-unknown-microarchitecture-error)
+  - [6.2 Other situations](#62-other-situations)
 - [7. Acknowledgements](#7-acknowledgements)
 - [8. cpufetch for GPUs (gpufetch)](#8-cpufetch-for-gpus-gpufetch)
 
@@ -57,17 +59,17 @@ cpufetch is a command-line tool written in C that displays the CPU information i
 
 ## 1. Support
 
-| OS          | x86_64 / x86       | ARM                | PowerPC            |
-|:-----------:|:------------------:|:------------------:|:------------------:|
-| GNU / Linux | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| Windows     | :heavy_check_mark: | :x:                | :x:                |
-| Android     | :heavy_check_mark: | :heavy_check_mark: | :x:                |
-| macOS       | :heavy_check_mark: | :heavy_check_mark: | :x:                |
-| FreeBSD     | :heavy_check_mark: | :x:                | :x:                |
+| OS          | x86_64 / x86       | ARM                | RISC-V             | PowerPC            |
+|:-----------:|:------------------:|:------------------:|:------------------:|:------------------:|
+| GNU / Linux | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| Windows     | :heavy_check_mark: | :x:                | :x:                | :x:                |
+| Android     | :heavy_check_mark: | :heavy_check_mark: | :x:                | :x:                |
+| macOS       | :heavy_check_mark: | :heavy_check_mark: | :x:                | :heavy_check_mark: |
+| FreeBSD     | :heavy_check_mark: | :x:                | :x:                | :x:                |
 
 **NOTES:**
 - Colors will be used in Windows only if the terminal supports it.
-- Support in macOS ARM is limited to Apple M1 only
+- Support in macOS ARM is limited to Apple chips only
 
 ## 2. Installation
 ### 2.1 Installing from a package
@@ -147,15 +149,31 @@ By default, `cpufetch` will print the CPU logo with the system colorscheme. Howe
 See [cpufetch programming documentation](https://github.com/Dr-Noob/cpufetch/tree/master/doc).
 
 ## 6. Bugs or improvements
+### 6.1 Unknown microarchitecture error
+If you get the `Unknown microarchitecture detected` error when running cpufetch, it might be caused by two possible reasons:
+
+1. You are running an old release of cpufetch (most likely)
+2. Your microarchitecture is not yet supported
+
+Download and compile the latest version (see https://github.com/Dr-Noob/cpufetch#22-building-from-source for instructions)
+and verify if the error persists.
+
+* __If the error dissapears__: It means that this is the first situation. In this case, just use the
+latest version of cpufetch which already has support for your hardware.
+* __If the error does not dissapear__: It means that this is the
+second situation. In this case, please create a new issue with the error message and the output of 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues
+
+### 6.2 Other situations
 See [cpufetch contributing guidelines](https://github.com/Dr-Noob/cpufetch/blob/master/CONTRIBUTING.md).
 
 ## 7. Acknowledgements
 Thanks to the fellow contributors and interested people in the project. Special thanks to:
 - [Gonzalocl](https://github.com/Gonzalocl) and [OdnetninI](https://github.com/OdnetninI): Tested cpufetch in the earlier versions of the project in many different CPUs.
 - [Kyngo](https://github.com/Kyngo): Tested cpufetch in the Apple M1 CPU.
-- [avollmerhaus](https://github.com/avollmerhaus): Gave me ssh acess to a PowerPC machine, allowing me to develop the PowerPC port.
+- [avollmerhaus](https://github.com/avollmerhaus): Helped with PowerPC port giving ssh access to a PowerPC machine.
 - [bbonev](https://github.com/bbonev) and [stephan-cr](https://github.com/stephan-cr): Reviewed the source code.
-- [mdoksa76](https://github.com/mdoksa76) and [exkc](https://github.com/exkc): Excellent ideas and impeccable feedback for supporting Allwinner SoCs.
+- [mdoksa76](https://github.com/mdoksa76) and [exkc](https://github.com/exkc): Excellent ideas and feedback for supporting Allwinner SoCs.
+- [Sakura286](https://github.com/Sakura286), [exkc](https://github.com/exkc) and [Patola](https://github.com/Patola): Helped with RISC-V port with ssh access, ideas, testing, etc.
 
 ## 8. cpufetch for GPUs (gpufetch)
 See [gpufetch](https://github.com/Dr-Noob/gpufetch) project!

src/arm/midr.c

@@ -13,10 +13,10 @@
 #endif
 
 #include "../common/global.h"
+#include "../common/soc.h"
 #include "udev.h"
 #include "midr.h"
 #include "uarch.h"
-#include "soc.h"
 
 bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
   return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
@@ -80,26 +80,21 @@ int64_t get_peak_performance(struct cpuInfo* cpu) {
     }
   }
 
-  int64_t flops = 0;
+  int64_t total_flops = 0;
   ptr = cpu;
 
-  if(cpu->soc->soc_vendor == SOC_VENDOR_APPLE) {
-    // Special case for M1/M2
-    // First we find the E cores, then the P
-    // M1 have 2 (E cores) or 4 (P cores) FMA units
-    // Source: https://dougallj.github.io/applecpu/firestorm-simd.html
-    flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000) * 2 * 4 * 2;
-    ptr = ptr->next_cpu;
-    flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000) * 2 * 4 * 4;
-  }
-  else {
   for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
-      flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000);
-    }
-    if(cpu->feat->NEON) flops = flops * 4;
+    int vpus = get_number_of_vpus(ptr);
+    int vpus_width = get_vpus_width(ptr);
+    bool has_fma = has_fma_support(ptr);
+
+    int64_t flops = ptr->topo->total_cores * get_freq(ptr->freq) * 1000000 * vpus * (vpus_width/32);
+    if(has_fma) flops = flops * 2;
+
+    total_flops += flops;
   }
 
-  return flops;
+  return total_flops;
 }
 
 uint32_t fill_ids_from_midr(uint32_t* midr_array, int32_t* freq_array, uint32_t* ids_array, int len) {
@@ -294,7 +289,7 @@ void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint
   bli->feat = get_features_info();
   bli->topo = malloc(sizeof(struct topology));
   bli->topo->cach = bli->cach;
-  bli->topo->total_cores = pcores;
+  bli->topo->total_cores = ecores;
   bli->freq = malloc(sizeof(struct frequency));
   bli->freq->base = UNKNOWN_DATA;
   bli->freq->max = 2800;
@@ -310,7 +305,7 @@ void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint
   ava->feat = get_features_info();
   ava->topo = malloc(sizeof(struct topology));
   ava->topo->cach = ava->cach;
-  ava->topo->total_cores = ecores;
+  ava->topo->total_cores = pcores;
   ava->freq = malloc(sizeof(struct frequency));
   ava->freq->base = UNKNOWN_DATA;
   ava->freq->max = 3500;
@@ -319,46 +314,78 @@ void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint
   ava->next_cpu = NULL;
 }
 
-struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
-  uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
+void fill_cpu_info_everest_sawtooth(struct cpuInfo* cpu, uint32_t pcores, uint32_t ecores) {
+  // 1. Fill SAWTOOTH
+  struct cpuInfo* saw = cpu;
 
+  saw->midr = MIDR_APPLE_M3_SAWTOOTH;
+  saw->arch = get_uarch_from_midr(saw->midr, saw);
+  saw->cach = get_cache_info(saw);
+  saw->feat = get_features_info();
+  saw->topo = malloc(sizeof(struct topology));
+  saw->topo->cach = saw->cach;
+  saw->topo->total_cores = ecores;
+  saw->freq = malloc(sizeof(struct frequency));
+  saw->freq->base = UNKNOWN_DATA;
+  saw->freq->max = 2750;
+  saw->hv = malloc(sizeof(struct hypervisor));
+  saw->hv->present = false;
+  saw->next_cpu = malloc(sizeof(struct cpuInfo));
+
+  // 2. Fill EVEREST
+  struct cpuInfo* eve = saw->next_cpu;
+  eve->midr = MIDR_APPLE_M3_EVEREST;
+  eve->arch = get_uarch_from_midr(eve->midr, eve);
+  eve->cach = get_cache_info(eve);
+  eve->feat = get_features_info();
+  eve->topo = malloc(sizeof(struct topology));
+  eve->topo->cach = eve->cach;
+  eve->topo->total_cores = pcores;
+  eve->freq = malloc(sizeof(struct frequency));
+  eve->freq->base = UNKNOWN_DATA;
+  eve->freq->max = 4050;
+  eve->hv = malloc(sizeof(struct hypervisor));
+  eve->hv->present = false;
+  eve->next_cpu = NULL;
+}
+
+struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
+  // https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_system_capabilities
+  uint32_t nperflevels = get_sys_info_by_name("hw.nperflevels");
+
+  if((cpu->num_cpus = nperflevels) != 2) {
+    printBug("Expected to find SoC with 2 perf levels, found: %d", cpu->num_cpus);
+    return NULL;
+  }
+
+  uint32_t pcores = get_sys_info_by_name("hw.perflevel0.physicalcpu");
+  uint32_t ecores = get_sys_info_by_name("hw.perflevel1.physicalcpu");
+  if(ecores <= 0) {
+    printBug("Expected to find a numer of ecores > 0, found: %d", ecores);
+    return NULL;
+  }
+  if(pcores <= 0) {
+    printBug("Expected to find a numer of pcores > 0, found: %d", pcores);
+    return NULL;
+  }
+
+  uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
   // Manually fill the cpuInfo assuming that
-  // the CPU is an Apple M1/M2
+  // the CPU is an Apple SoC
   if(cpu_family == CPUFAMILY_ARM_FIRESTORM_ICESTORM) {
-    cpu->num_cpus = 2;
-    // Now detect the M1 version
-    uint32_t cpu_subfamily = get_sys_info_by_name("hw.cpusubfamily");
-    if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
-      // Apple M1
-      fill_cpu_info_firestorm_icestorm(cpu, 4, 4);
-    }
-    else if(cpu_subfamily == CPUSUBFAMILY_ARM_HS || cpu_subfamily == CPUSUBFAMILY_ARM_HC_HD) {
-      // Apple M1 Pro/Max/Ultra. Detect number of cores
-      uint32_t physicalcpu = get_sys_info_by_name("hw.physicalcpu");
-      if(physicalcpu == 20) {
-        // M1 Ultra
-        fill_cpu_info_firestorm_icestorm(cpu, 16, 4);
-      }
-      else if(physicalcpu == 8 || physicalcpu == 10) {
-        // M1 Pro/Max
-        fill_cpu_info_firestorm_icestorm(cpu, physicalcpu-2, 2);
-      }
-      else {
-        printBug("Found invalid physical cpu number: %d", physicalcpu);
-        return NULL;
-      }
-    }
-    else {
-      printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
-      return NULL;
-    }
+    fill_cpu_info_firestorm_icestorm(cpu, pcores, ecores);
     cpu->soc = get_soc();
     cpu->peak_performance = get_peak_performance(cpu);
   }
   else if(cpu_family == CPUFAMILY_ARM_AVALANCHE_BLIZZARD) {
-    // Just the "normal" M2 exists for now
-    cpu->num_cpus = 2;
-    fill_cpu_info_avalanche_blizzard(cpu, 4, 4);
+    fill_cpu_info_avalanche_blizzard(cpu, pcores, ecores);
+    cpu->soc = get_soc();
+    cpu->peak_performance = get_peak_performance(cpu);
+  }
+  else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
+          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
+          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
+    fill_cpu_info_everest_sawtooth(cpu, pcores, ecores);
     cpu->soc = get_soc();
     cpu->peak_performance = get_peak_performance(cpu);
   }
@@ -448,6 +475,12 @@ void print_debug(struct cpuInfo* cpu) {
       printf("%ld MHz\n", freq);
     }
   }
+
+  #if defined(__APPLE__) || defined(__MACH__)
+    printf("hw.cpufamily: 0x%.8X\n", get_sys_info_by_name("hw.cpufamily"));
+    printf("hw.cpusubfamily: 0x%.8X\n", get_sys_info_by_name("hw.cpusubfamily"));
+    printf("hw.physicalcpu: %d\n", get_sys_info_by_name("hw.physicalcpu"));
+  #endif
 }
 
 void free_topo_struct(struct topology* topo) {

src/arm/soc.c

@@ -12,51 +12,18 @@
   #include "sysctl.h"
 #endif
 
+#define NA -1
 #define min(a,b) (((a)<(b))?(a):(b))
 #define ARRAY_SIZE(arr)     (sizeof(arr) / sizeof((arr)[0]))
 
-static char* soc_trademark_string[] = {
-  [SOC_VENDOR_SNAPDRAGON] = "Snapdragon ",
-  [SOC_VENDOR_MEDIATEK]   = "MediaTek ",
-  [SOC_VENDOR_EXYNOS]     = "Exynos ",
-  [SOC_VENDOR_KIRIN]      = "Kirin ",
-  [SOC_VENDOR_BROADCOM]   = "Broadcom BCM",
-  [SOC_VENDOR_APPLE]      = "Apple ",
-  [SOC_VENDOR_ALLWINNER]  = "Allwinner ",
-  [SOC_VENDOR_ROCKCHIP]   = "Rockchip ",
-};
-
 static char* soc_rpi_string[] = {
   "BCM2835",
   "BCM2836",
   "BCM2837",
-  "BCM2711"
+  "BCM2711",
+  "BCM2712"
 };
 
-void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process) {
-  soc->soc_model = soc_model;
-  soc->soc_vendor = get_soc_vendor_from_soc(soc_model);
-  soc->process = process;
-  int len = strlen(soc_name) + strlen(soc_trademark_string[soc->soc_vendor]) + 1;
-  soc->soc_name = emalloc(sizeof(char) * len);
-  memset(soc->soc_name, 0, sizeof(char) * len);
-  sprintf(soc->soc_name, "%s%s", soc_trademark_string[soc->soc_vendor], soc_name);
-}
-
-bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
-  int len1 = strlen(raw_name);
-  int len2 = strlen(expected_name);
-  int len = min(len1, len2);
-
-  if(strncmp(raw_name, expected_name, len) != 0) {
-    return false;
-  }
-  else {
-    fill_soc(soc, soc_name, soc_model, process);
-    return true;
-  }
-}
-
 char* toupperstr(char* str) {
   int len = strlen(str) + 1;
   char* ret = emalloc(sizeof(char) * len);
@@ -123,11 +90,7 @@ bool get_sunxisoc_from_sid(struct system_on_chip* soc, char* raw_name, uint32_t
   return false;
 }
 
-#define SOC_START if (false) {}
-#define SOC_EQ(raw_name, expected_name, soc_name, soc_model, soc, process) \
-   else if (match_soc(soc, raw_name, expected_name, soc_name, soc_model, process)) return true;
-#define SOC_END else { return false; }
-// Exynos special define
+// Exynos special define (not included in src/common/soc.h)
 #define SOC_EXY_EQ(raw_name, tmpsoc, soc_name, soc_model, soc, process)             \
    sprintf(tmpsoc, "exynos%s", soc_name);                                           \
    if (match_soc(soc, raw_name, tmpsoc, soc_name, soc_model, process)) return true; \
@@ -150,7 +113,6 @@ bool match_broadcom(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "BCM2836",              "2836",              SOC_BCM_2836,   soc, 40)
   SOC_EQ(tmp, "BCM2837",              "2837",              SOC_BCM_2837,   soc, 40)
   SOC_EQ(tmp, "BCM2837B0",            "2837B0",            SOC_BCM_2837B0, soc, 40)
-  SOC_EQ(tmp, "BCM2711",              "2711",              SOC_BCM_2711,   soc, 28)
   SOC_EQ(tmp, "BCM21553",             "21553",             SOC_BCM_21553,  soc, 65)
   SOC_EQ(tmp, "BCM21553-Thunderbird", "21553 Thunderbird", SOC_BCM_21553T, soc, 65)
   SOC_EQ(tmp, "BCM21663",             "21663",             SOC_BCM_21663,  soc, 40)
@@ -160,6 +122,24 @@ bool match_broadcom(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "BCM28145",             "28145",             SOC_BCM_28145,  soc, 40)
   SOC_EQ(tmp, "BCM2157",              "2157",              SOC_BCM_2157,   soc, 65)
   SOC_EQ(tmp, "BCM21654",             "21654",             SOC_BCM_21654,  soc, 40)
+  SOC_EQ(tmp, "BCM2711",              "2711",              SOC_BCM_2711,   soc, 28)
+  SOC_EQ(tmp, "BCM2712",              "2712",              SOC_BCM_2712,   soc, 16)
+  SOC_END
+}
+
+// https://en.wikipedia.org/wiki/Google_Tensor
+bool match_google(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+
+  if((tmp = strstr(soc_name, "gs")) == NULL)
+    return false;
+
+  soc->soc_vendor = SOC_VENDOR_GOOGLE;
+
+  SOC_START
+  SOC_EQ(tmp, "gs101", "Tensor",    SOC_GOOGLE_TENSOR,    soc, 5)
+  SOC_EQ(tmp, "gs201", "Tensor G2", SOC_GOOGLE_TENSOR_G2, soc, 5)
+  SOC_EQ(tmp, "gs301", "Tensor G3", SOC_GOOGLE_TENSOR_G3, soc, 4)
   SOC_END
 }
 
@@ -261,6 +241,10 @@ bool match_exynos(char* soc_name, struct system_on_chip* soc) {
   SOC_END
 }
 
+// https://www.phonemore.com/processors/mediatek/
+// https://phonedb.net/
+// https://en.wikipedia.org/wiki/List_of_MediaTek_systems_on_chips
+// https://wikimovel.com/index.php/MediaTek
 bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
   char* tmp;
   char* soc_name_upper = toupperstr(soc_name);
@@ -272,25 +256,38 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
 
   SOC_START
   // Dimensity //
+  SOC_EQ(tmp, "MT6893Z",  "Dimensity 1300",  SOC_MTK_MT6893Z,  soc, 6)
   SOC_EQ(tmp, "MT6893",   "Dimensity 1200",  SOC_MTK_MT6893,   soc, 6)
   SOC_EQ(tmp, "MT6891",   "Dimensity 1100",  SOC_MTK_MT6891,   soc, 6)
+  //SOC_EQ(tmp, "MT6877V",  "Dimensity 1080",  SOC_MTK_MT6877V   soc, 7) // There is a clash between this and another chip
+  SOC_EQ(tmp, "MT6879",   "Dimensity 1050",  SOC_MTK_MT6879,   soc, 6)
   SOC_EQ(tmp, "MT6889",   "Dimensity 1000",  SOC_MTK_MT6889,   soc, 7)
   SOC_EQ(tmp, "MT6885Z",  "Dimensity 1000L", SOC_MTK_MT6885Z,  soc, 7)
-  //SOC_EQ(tmp, "?",      "Dimensity 700",   SOC_MTK_,         soc, 7)
+  SOC_EQ(tmp, "MT6889Z",  "Dimensity 1000+", SOC_MTK_MT6889Z,  soc, 7)
+  SOC_EQ(tmp, "MT6883Z",  "Dimensity 1000C", SOC_MTK_MT6883Z,  soc, 7)
+  SOC_EQ(tmp, "MT6833",   "Dimensity 700",   SOC_MTK_MT6833,   soc, 7)
   SOC_EQ(tmp, "MT6853",   "Dimensity 720",   SOC_MTK_MT6853,   soc, 7)
   SOC_EQ(tmp, "MT6873",   "Dimensity 800",   SOC_MTK_MT6873,   soc, 7)
+  SOC_EQ(tmp, "MT6853V",  "Dimensity 800U",  SOC_MTK_MT6853V,  soc, 7)
+  SOC_EQ(tmp, "MT6833",   "Dimensity 810",   SOC_MTK_MT6833,   soc, 6)
   SOC_EQ(tmp, "MT6875",   "Dimensity 820",   SOC_MTK_MT6875,   soc, 7)
   // Helio //
   SOC_EQ(tmp, "MT6761D",  "Helio A20",       SOC_MTK_MT6761D,  soc, 12)
   SOC_EQ(tmp, "MT6761",   "Helio A22",       SOC_MTK_MT6761,   soc, 12)
   SOC_EQ(tmp, "MT6762D",  "Helio A25",       SOC_MTK_MT6762D,  soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G25",       SOC_MTK_,         soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G35",       SOC_MTK_,         soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G70",       SOC_MTK_,         soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G80",       SOC_MTK_,         soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G90",       SOC_MTK_,         soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G90T",      SOC_MTK_,         soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio G95",       SOC_MTK_,         soc, 12)
+  SOC_EQ(tmp, "MT6762G",  "Helio G25",       SOC_MTK_MT6762G,  soc, 12)
+  SOC_EQ(tmp, "MT6765G",  "Helio G35",       SOC_MTK_MT6765G,  soc, 12)
+  //SOC_EQ(tmp, "???",    "Helio G36",       SOC_MTK_MT6765G,  soc,  ?)
+  SOC_EQ(tmp, "MT6765H",  "Helio G37",       SOC_MTK_MT6765H,  soc, 12)
+  SOC_EQ(tmp, "MT6769V",  "Helio G70",       SOC_MTK_MT6769V,  soc, 12)
+  SOC_EQ(tmp, "MT6769T",  "Helio G80",       SOC_MTK_MT6769T,  soc, 12)
+  SOC_EQ(tmp, "MT6769Z",  "Helio G85",       SOC_MTK_MT6769Z,  soc, 12)
+  SOC_EQ(tmp, "MT6769H",  "Helio G88",       SOC_MTK_MT6769H,  soc, 12)
+  //SOC_EQ(tmp, "MT6785V/CD", "Helio G90",   SOC_MTK_MT6785V_CD, soc, 12) // How to distingish between this and G95?
+  SOC_EQ(tmp, "MT6785V/CC", "Helio G90T",    SOC_MTK_MT6785V_CC, soc, 12)
+  SOC_EQ(tmp, "MT6785V/CD", "Helio G95",     SOC_MTK_MT6785V_CD, soc, 12)
+  SOC_EQ(tmp, "MT6789",   "Helio G99",       SOC_MTK_MT6789,   soc,  6)
+  SOC_EQ(tmp, "MT8781V",  "Helio G99",       SOC_MTK_MT8781V,  soc,  6) // Same as MT6789
   SOC_EQ(tmp, "MT6755",   "Helio P10",       SOC_MTK_MT6755M,  soc, 28)
   SOC_EQ(tmp, "MT6755M",  "Helio P10 M",     SOC_MTK_MT6755M,  soc, 28)
   SOC_EQ(tmp, "MT6755T",  "Helio P15",       SOC_MTK_MT6755T,  soc, 28)
@@ -305,8 +302,8 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "MT6768",   "Helio P65",       SOC_MTK_MT6768,   soc, 12)
   SOC_EQ(tmp, "MT6771T",  "Helio P70",       SOC_MTK_MT6771,   soc, 12)
   SOC_EQ(tmp, "MT6771V",  "Helio P70",       SOC_MTK_MT6771,   soc, 12)
-  SOC_EQ(tmp, "MT6779",   "Helio P90",       SOC_MTK_MT6779,   soc, 12)
-  //SOC_EQ(tmp, "?",      "Helio P95",       SOC_MTK_,         soc, 12)
+  SOC_EQ(tmp, "MT6779V/CU", "Helio P90",     SOC_MTK_MT6779V_CU, soc, 12)
+  SOC_EQ(tmp, "MT6779V/CV", "Helio P95",     SOC_MTK_MT6779V_CV, soc, 12)
   SOC_EQ(tmp, "MT6795",   "Helio X10",       SOC_MTK_MT6795,   soc, 28)
   SOC_EQ(tmp, "MT6795T",  "Helio X10 T",     SOC_MTK_MT6795,   soc, 28)
   SOC_EQ(tmp, "MT6797",   "Helio X20",       SOC_MTK_MT6797,   soc, 20)
@@ -315,7 +312,31 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "MT6797T",  "Helio X25",       SOC_MTK_MT6797T,  soc, 20)
   SOC_EQ(tmp, "MT6797X",  "Helio X27",       SOC_MTK_MT6797X,  soc, 20)
   SOC_EQ(tmp, "MT6799",   "Helio X30",       SOC_MTK_MT6799,   soc, 10)
+  // Pentonic
+  SOC_EQ(tmp, "MT9618",   "Pentonic  700",   SOC_MTK_MT9618,   soc,  7)
+  SOC_EQ(tmp, "MT9653",   "Pentonic  700",   SOC_MTK_MT9653,   soc,  7)
+  SOC_EQ(tmp, "MT9689",   "Pentonic  700",   SOC_MTK_MT9689,   soc,  7) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT9972",   "Pentonic 1000",   SOC_MTK_MT9972,   soc,  7) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT9902",   "Pentonic 2000",   SOC_MTK_MT9902,   soc,  7)
+  SOC_EQ(tmp, "MT9982",   "Pentonic 2000",   SOC_MTK_MT9982,   soc,  7)
   // MT XXXX //
+  SOC_EQ(tmp, "MT5327",   "MT5327",          SOC_MTK_MT5327,   soc, NA)
+  SOC_EQ(tmp, "MT5329",   "MT5329",          SOC_MTK_MT5329,   soc, NA)
+  SOC_EQ(tmp, "MT5366",   "MT5366",          SOC_MTK_MT5366,   soc, NA)
+  SOC_EQ(tmp, "MT5389",   "MT5389",          SOC_MTK_MT5389,   soc, NA)
+  SOC_EQ(tmp, "MT5395",   "MT5395",          SOC_MTK_MT5395,   soc, NA)
+  SOC_EQ(tmp, "MT5396",   "MT5396",          SOC_MTK_MT5396,   soc, NA)
+  SOC_EQ(tmp, "MT5398",   "MT5398",          SOC_MTK_MT5398,   soc, NA)
+  SOC_EQ(tmp, "MT5505",   "MT5505",          SOC_MTK_MT5505,   soc, NA)
+  SOC_EQ(tmp, "MT5561",   "MT5561",          SOC_MTK_MT5561,   soc, NA)
+  SOC_EQ(tmp, "MT5580",   "MT5580",          SOC_MTK_MT5580,   soc, NA)
+  SOC_EQ(tmp, "MT5582",   "MT5582",          SOC_MTK_MT5582,   soc, NA)
+  SOC_EQ(tmp, "MT5592",   "MT5592",          SOC_MTK_MT5592,   soc, NA)
+  SOC_EQ(tmp, "MT5595",   "MT5595",          SOC_MTK_MT5595,   soc, NA)
+  SOC_EQ(tmp, "MT5596",   "MT5596",          SOC_MTK_MT5596,   soc, 28) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT5597",   "MT5597",          SOC_MTK_MT5597,   soc, 28) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT5895",   "MT5895",          SOC_MTK_MT5895,   soc, 28) // Same as MT9950*
+  SOC_EQ(tmp, "MT5889",   "MT5889",          SOC_MTK_MT5889,   soc, 28) // Same as MT9615 (https://www.displayspecifications.com/en/model/97272c1f)
   SOC_EQ(tmp, "MT6515",   "MT6515",          SOC_MTK_MT6515,   soc, 40)
   SOC_EQ(tmp, "MT6516",   "MT6516",          SOC_MTK_MT6516,   soc, 65)
   SOC_EQ(tmp, "MT6517",   "MT6517",          SOC_MTK_MT6517,   soc, 40)
@@ -361,6 +382,19 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "MT8735",   "MT8735",          SOC_MTK_MT8735,   soc, 28)
   SOC_EQ(tmp, "MT8765B",  "MT8765B",         SOC_MTK_MT8765B,  soc, 28)
   SOC_EQ(tmp, "MT8783",   "MT8783",          SOC_MTK_MT8783,   soc, 28)
+  SOC_EQ(tmp, "MT9602",   "MT9602",          SOC_MTK_MT9602,   soc, 28) // Same as MT9675*
+  SOC_EQ(tmp, "MT9612",   "MT9612",          SOC_MTK_MT9612,   soc, 28) // Same as MT9685*
+  SOC_EQ(tmp, "MT9613",   "MT9613",          SOC_MTK_MT9613,   soc, 28) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT9615",   "MT9615",          SOC_MTK_MT9615,   soc, 28) // https://gadgetversus.com/processor/mediatek-mt9615-specs/
+  SOC_EQ(tmp, "MT9632",   "MT9632",          SOC_MTK_MT9632,   soc, 28) // Same as MT9675*
+  SOC_EQ(tmp, "MT9638",   "MT9638",          SOC_MTK_MT9638,   soc, 28) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT9652",   "MT9652",          SOC_MTK_MT9652,   soc, 28) // Same as MT9613*
+  SOC_EQ(tmp, "MT9675",   "MT9675",          SOC_MTK_MT9675,   soc, 28) // !! Assumption only, needs confirmation
+  SOC_EQ(tmp, "MT9685",   "MT9685",          SOC_MTK_MT9685,   soc, 28) // https://gadgetversus.com/processor/mediatek-mt9685-specs/
+  SOC_EQ(tmp, "MT9950",   "MT9950",          SOC_MTK_MT9950,   soc, 28) // https://gadgetversus.com/processor/mediatek-mt9950-specs/
+  SOC_EQ(tmp, "MT9686",   "MT9686",          SOC_MTK_MT9686,   soc, 28) // Same as MT9613*
+  // (*) Many SoCs are reported with different names but they are the same chip.
+  // Source: https://en.wikipedia.org/wiki/List_of_MediaTek_systems_on_chips#Digital_television_SoCs
   SOC_END
 }
 
@@ -574,6 +608,21 @@ bool match_special(char* soc_name, struct system_on_chip* soc) {
     return true;
   }
 
+  // Google Pixel 6
+  // https://github.com/Dr-Noob/cpufetch/issues/134
+  if(strcmp(soc_name, "oriole") == 0) {
+    fill_soc(soc, "Tensor", SOC_GOOGLE_TENSOR, 5);
+    return true;
+  }
+
+  // Google Pixel 8
+  // https://github.com/Dr-Noob/cpufetch/issues/198
+  if(strcmp(soc_name, "husky") == 0 ||
+     strcmp(soc_name, "zuma") == 0) {
+    fill_soc(soc, "Tensor G3", SOC_GOOGLE_TENSOR_G3, 4);
+    return true;
+  }
+
   return false;
 }
 
@@ -598,6 +647,9 @@ struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
   if(match_allwinner(raw_name, soc))
     return soc;
 
+  if(match_google(raw_name, soc))
+    return soc;
+
   match_broadcom(raw_name, soc);
   return soc;
 }
@@ -657,11 +709,15 @@ struct system_on_chip* guess_soc_from_cpuinfo(struct system_on_chip* soc) {
   return soc;
 }
 
-char* get_rk_efuse() {
+char* get_rk_efuse(void) {
   int filelen;
   char* rk_soc = read_file(_PATH_RK_EFUSE0, &filelen);
   if(rk_soc == NULL) {
     printWarn("read_file: %s: %s", _PATH_RK_EFUSE0, strerror(errno));
+    rk_soc = read_file(_PATH_RK_OTP0, &filelen);
+    if(rk_soc == NULL) {
+      printWarn("read_file: %s: %s", _PATH_RK_OTP0, strerror(errno));
+    }
   }
   return rk_soc;
 }
@@ -678,6 +734,7 @@ bool get_rk_soc_from_efuse(struct system_on_chip* soc, char* efuse) {
   rkToSoC socFromRK[] = {
     // TODO: Add RK2XXX
     // RK3XXX
+    // Reverse order
     {0x2388, {SOC_ROCKCHIP_3288,  SOC_VENDOR_ROCKCHIP, 28, "RK3288",  NULL} },
     {0x2392, {SOC_ROCKCHIP_3229,  SOC_VENDOR_ROCKCHIP, 28, "RK3229",  NULL} }, // https://gadgetversus.com/processor/rockchip-rk3229-vs-rockchip-rk3128/
     {0x3380, {SOC_ROCKCHIP_3308,  SOC_VENDOR_ROCKCHIP, 28, "RK3308",  NULL} }, // https://en.t-firefly.com/product/rocrk3308cc?theme=pc
@@ -686,9 +743,12 @@ bool get_rk_soc_from_efuse(struct system_on_chip* soc, char* efuse) {
     {0x3382, {SOC_ROCKCHIP_3328,  SOC_VENDOR_ROCKCHIP, 28, "RK3328",  NULL} },
     {0x3386, {SOC_ROCKCHIP_3368,  SOC_VENDOR_ROCKCHIP, 28, "RK3368",  NULL} },
     {0x3399, {SOC_ROCKCHIP_3399,  SOC_VENDOR_ROCKCHIP, 28, "RK3399",  NULL} },
-    {0x5366, {SOC_ROCKCHIP_3566, SOC_VENDOR_ROCKCHIP, 22, "RK3566",  NULL} },
-    {0x5386, {SOC_ROCKCHIP_3568, SOC_VENDOR_ROCKCHIP, 22, "RK3568",  NULL} },
-    {0x5388, {SOC_ROCKCHIP_3588, SOC_VENDOR_ROCKCHIP,  8, "RK3588",  NULL} },
+    // Normal Order (https://github.com/Dr-Noob/cpufetch/issues/209)
+    {0x3528, {SOC_ROCKCHIP_3528,  SOC_VENDOR_ROCKCHIP, 28, "RK3528",  NULL} },
+    {0x3562, {SOC_ROCKCHIP_3562,  SOC_VENDOR_ROCKCHIP, 22, "RK3562",  NULL} },
+    {0x3566, {SOC_ROCKCHIP_3566,  SOC_VENDOR_ROCKCHIP, 22, "RK3566",  NULL} },
+    {0x3568, {SOC_ROCKCHIP_3568,  SOC_VENDOR_ROCKCHIP, 22, "RK3568",  NULL} },
+    {0x3588, {SOC_ROCKCHIP_3588,  SOC_VENDOR_ROCKCHIP,  8, "RK3588",  NULL} }, // No known way to distingish between S version: https://github.com/Dr-Noob/cpufetch/issues/188,209
     // Unknown
     {0x0000, {UNKNOWN,            SOC_VENDOR_UNKNOWN,   -1,       "", NULL} }
   };
@@ -732,7 +792,13 @@ int hex2int(char c) {
   return -1;
 }
 
-// https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md
+/*
+ * https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#raspberry-pi-revision-codes:
+ * NOTE: As of the 4.9 kernel, all Raspberry Pi computers report BCM2835, even those with BCM2836,
+ * BCM2837 and BCM2711 processors. You should not use this string to detect the processor. Decode the
+ * revision code using the information below.
+ * https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#new-style-revision-codes-in-use
+ */
 struct system_on_chip* guess_soc_raspbery_pi(struct system_on_chip* soc) {
   char* revision = get_revision_from_cpuinfo();
 
@@ -748,22 +814,19 @@ struct system_on_chip* guess_soc_raspbery_pi(struct system_on_chip* soc) {
 
   int arr_size = ARRAY_SIZE(soc_rpi_string);
   int pppp = hex2int(revision[2]);
-  if(pppp == -1) {
-    printErr("[RPi] Found invalid RPi PPPP code: %s", revision[2]);
+  if(pppp < 0) {
+    printBug("[RPi] Found invalid RPi PPPP code: %s", pppp);
     return soc;
   }
 
-  if(pppp > arr_size) {
-    printErr("[RPi] Found invalid RPi PPPP code: %d while max is %d", pppp, arr_size);
+  if(pppp > arr_size-1) {
+    printBug("[RPi] Found invalid RPi PPPP code: %d (max is %d)", pppp, arr_size-1);
     return soc;
   }
 
   char* soc_raw_name = soc_rpi_string[pppp];
-  /*int soc_len = strlen(soc_raw_name);
-  soc->raw_name = emalloc(sizeof(char) * (soc_len + 1));
-  strncpy(soc->raw_name, soc_raw_name, soc_len + 1);*/
-
   match_broadcom(soc_raw_name, soc);
+
   return soc;
 }
 
@@ -804,11 +867,46 @@ struct system_on_chip* guess_soc_apple(struct system_on_chip* soc) {
     if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
       fill_soc(soc, "M2", SOC_APPLE_M2, 5);
     }
+    else if(cpu_subfamily == CPUSUBFAMILY_ARM_HS) {
+      fill_soc(soc, "M2 Pro", SOC_APPLE_M2_PRO, 5);
+    }
+    else if(cpu_subfamily == CPUSUBFAMILY_ARM_HC_HD) {
+      // Could be M2 Max or M2 Ultra (2x M1 Max)
+      uint32_t physicalcpu = get_sys_info_by_name("hw.physicalcpu");
+      if(physicalcpu == 24) {
+        fill_soc(soc, "M2 Ultra", SOC_APPLE_M2_ULTRA, 5);
+      }
+      else if(physicalcpu == 12) {
+        fill_soc(soc, "M2 Max", SOC_APPLE_M2_MAX, 5);
+      }
+      else {
+        printBug("Found invalid physical cpu number: %d", physicalcpu);
+        soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+      }
+    }
     else {
       printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
       soc->soc_vendor = SOC_VENDOR_UNKNOWN;
     }
   }
+  else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
+          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
+          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
+    // Check M3 version
+    if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH) {
+      fill_soc(soc, "M3", SOC_APPLE_M3, 3);
+    }
+    else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO) {
+      fill_soc(soc, "M3 Pro", SOC_APPLE_M3_PRO, 3);
+    }
+    else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
+      fill_soc(soc, "M3 Max", SOC_APPLE_M3_MAX, 3);
+    }
+    else {
+      printBug("Found invalid cpu_family: 0x%.8X", cpu_family);
+      soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+    }
+  }
   else {
     printBug("Found invalid cpu_family: 0x%.8X", cpu_family);
     soc->soc_vendor = SOC_VENDOR_UNKNOWN;
@@ -829,7 +927,7 @@ struct system_on_chip* get_soc(void) {
   if(isRPi) {
     soc = guess_soc_raspbery_pi(soc);
     if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
-      printWarn("SoC detection failed using revision code");
+      printErr("[RPi] SoC detection failed using revision code, falling back to cpuinfo detection");
     }
     else {
       return soc;
@@ -838,19 +936,25 @@ struct system_on_chip* get_soc(void) {
 
   soc = guess_soc_from_cpuinfo(soc);
   if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
-    if(soc->raw_name != NULL)
+    if(soc->raw_name != NULL) {
       printWarn("SoC detection failed using /proc/cpuinfo: Found '%s' string", soc->raw_name);
-    else
+    }
+    else {
       printWarn("SoC detection failed using /proc/cpuinfo: No string found");
-    // If cpufinfo detection fails, try with nvmem
-    soc = guess_soc_from_nvmem(soc);
+    }
 #ifdef __ANDROID__
     soc = guess_soc_from_android(soc);
-    if(soc->raw_name == NULL)
+    if(soc->raw_name == NULL) {
       printWarn("SoC detection failed using Android: No string found");
-    else if(soc->soc_vendor == SOC_VENDOR_UNKNOWN)
+    }
+    else if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
       printWarn("SoC detection failed using Android: Found '%s' string", soc->raw_name);
+    }
 #endif // ifdef __ANDROID__
+    // If cpufinfo/Android (if available) detection fails, try with nvmem
+    if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+      soc = guess_soc_from_nvmem(soc);
+    }
   }
 #elif defined __APPLE__ || __MACH__
   soc = guess_soc_apple(soc);
@@ -871,28 +975,3 @@ struct system_on_chip* get_soc(void) {
 
   return soc;
 }
-
-char* get_soc_name(struct system_on_chip* soc) {
-  if(soc->soc_model == SOC_MODEL_UNKNOWN)
-    return soc->raw_name;
-  return soc->soc_name;
-}
-
-VENDOR get_soc_vendor(struct system_on_chip* soc) {
-  return soc->soc_vendor;
-}
-
-char* get_str_process(struct system_on_chip* soc) {
-  char* str;
-
-  if(soc->process == UNKNOWN) {
-    str = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
-    snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
-  }
-  else {
-    str = emalloc(sizeof(char) * 5);
-    memset(str, 0, sizeof(char) * 5);
-    snprintf(str, 5, "%dnm", soc->process);
-  }
-  return str;
-}

src/arm/soc.h

@@ -1,34 +1,10 @@
-#ifndef __SOC__
-#define __SOC__
+#ifndef __SOC_ARM__
+#define __SOC_ARM__
 
 #include "../common/cpu.h"
+#include "../common/soc.h"
 #include <stdint.h>
 
-typedef int32_t SOC;
-
-enum {
-  SOC_VENDOR_UNKNOWN,
-  SOC_VENDOR_SNAPDRAGON,
-  SOC_VENDOR_MEDIATEK,
-  SOC_VENDOR_EXYNOS,
-  SOC_VENDOR_KIRIN,
-  SOC_VENDOR_BROADCOM,
-  SOC_VENDOR_APPLE,
-  SOC_VENDOR_ALLWINNER,
-  SOC_VENDOR_ROCKCHIP
-};
-
-struct system_on_chip {
-  SOC soc_model;
-  VENDOR soc_vendor;
-  int32_t process;
-  char* soc_name;
-  char* raw_name;    
-};
-
 struct system_on_chip* get_soc(void);
-char* get_soc_name(struct system_on_chip* soc);
-VENDOR get_soc_vendor(struct system_on_chip* soc);
-char* get_str_process(struct system_on_chip* soc);
 
 #endif

src/arm/socs.h

@@ -10,7 +10,6 @@ enum {
   SOC_BCM_2836,
   SOC_BCM_2837,
   SOC_BCM_2837B0,
-  SOC_BCM_2711,
   SOC_BCM_21553,
   SOC_BCM_21553T,
   SOC_BCM_21663,
@@ -20,6 +19,8 @@ enum {
   SOC_BCM_28145,
   SOC_BCM_2157,
   SOC_BCM_21654,
+  SOC_BCM_2711,
+  SOC_BCM_2712,
   // Hisilicon //
   SOC_HISILICON_3620,
   SOC_HISILICON_3630,
@@ -63,39 +64,23 @@ enum {
   SOC_EXYNOS_980,
   SOC_EXYNOS_880,
   // Mediatek //
-  SOC_MTK_MT6893,
-  SOC_MTK_MT6891,
-  SOC_MTK_MT6889,
-  SOC_MTK_MT6885Z,
-  SOC_MTK_MT6853,
-  SOC_MTK_MT6873,
-  SOC_MTK_MT6875,
-  SOC_MTK_MT6761D,
-  SOC_MTK_MT6761,
-  SOC_MTK_MT6762D,
-  SOC_MTK_MT6755,
-  SOC_MTK_MT6755M,
-  SOC_MTK_MT6755T,
-  SOC_MTK_MT6757,
-  SOC_MTK_MT6762,
-  SOC_MTK_MT6763V,
-  SOC_MTK_MT6763T,
-  SOC_MTK_MT6757CD,
-  SOC_MTK_MT6758,
-  SOC_MTK_MT6765,
-  SOC_MTK_MT6771,
-  SOC_MTK_MT6768,
-  SOC_MTK_MT6771T,
-  SOC_MTK_MT6771V,
-  SOC_MTK_MT6779,
-  SOC_MTK_MT6795,
-  SOC_MTK_MT6795T,
-  SOC_MTK_MT6797,
-  SOC_MTK_MT6797M,
-  SOC_MTK_MT6797D,
-  SOC_MTK_MT6797T,
-  SOC_MTK_MT6797X,
-  SOC_MTK_MT6799,
+  SOC_MTK_MT5327,
+  SOC_MTK_MT5329,
+  SOC_MTK_MT5366,
+  SOC_MTK_MT5389,
+  SOC_MTK_MT5395,
+  SOC_MTK_MT5396,
+  SOC_MTK_MT5398,
+  SOC_MTK_MT5505,
+  SOC_MTK_MT5561,
+  SOC_MTK_MT5580,
+  SOC_MTK_MT5582,
+  SOC_MTK_MT5592,
+  SOC_MTK_MT5595,
+  SOC_MTK_MT5596,
+  SOC_MTK_MT5597,
+  SOC_MTK_MT5889,
+  SOC_MTK_MT5895,
   SOC_MTK_MT6515,
   SOC_MTK_MT6516,
   SOC_MTK_MT6517,
@@ -125,7 +110,51 @@ enum {
   SOC_MTK_MT6750T,
   SOC_MTK_MT6752,
   SOC_MTK_MT6753,
+  SOC_MTK_MT6755M,
+  SOC_MTK_MT6755T,
+  SOC_MTK_MT6757,
+  SOC_MTK_MT6757CD,
+  SOC_MTK_MT6758,
+  SOC_MTK_MT6761,
+  SOC_MTK_MT6761D,
+  SOC_MTK_MT6762,
+  SOC_MTK_MT6762D,
+  SOC_MTK_MT6762G,
+  SOC_MTK_MT6763T,
+  SOC_MTK_MT6763V,
+  SOC_MTK_MT6765,
+  SOC_MTK_MT6765G,
+  SOC_MTK_MT6765H,
+  SOC_MTK_MT6768,
+  SOC_MTK_MT6769H,
+  SOC_MTK_MT6769T,
+  SOC_MTK_MT6769V,
+  SOC_MTK_MT6769Z,
+  SOC_MTK_MT6771,
+  SOC_MTK_MT6779V_CU,
+  SOC_MTK_MT6779V_CV,
+  SOC_MTK_MT6785V_CC,
+  SOC_MTK_MT6785V_CD,
+  SOC_MTK_MT6789,
+  SOC_MTK_MT6795,
+  SOC_MTK_MT6797,
+  SOC_MTK_MT6797T,
+  SOC_MTK_MT6797X,
+  SOC_MTK_MT6799,
+  SOC_MTK_MT6833,
   SOC_MTK_MT6850,
+  SOC_MTK_MT6853,
+  SOC_MTK_MT6853V,
+  SOC_MTK_MT6873,
+  SOC_MTK_MT6875,
+  SOC_MTK_MT6879,
+  SOC_MTK_MT6883Z,
+  SOC_MTK_MT6885Z,
+  SOC_MTK_MT6889,
+  SOC_MTK_MT6889Z,
+  SOC_MTK_MT6891,
+  SOC_MTK_MT6893,
+  SOC_MTK_MT6893Z,
   SOC_MTK_MT8121,
   SOC_MTK_MT8125,
   SOC_MTK_MT8127,
@@ -140,7 +169,25 @@ enum {
   SOC_MTK_MT8581,
   SOC_MTK_MT8735,
   SOC_MTK_MT8765B,
+  SOC_MTK_MT8781V,
   SOC_MTK_MT8783,
+  SOC_MTK_MT9602,
+  SOC_MTK_MT9612,
+  SOC_MTK_MT9613,
+  SOC_MTK_MT9615,
+  SOC_MTK_MT9618,
+  SOC_MTK_MT9632,
+  SOC_MTK_MT9638,
+  SOC_MTK_MT9652,
+  SOC_MTK_MT9653,
+  SOC_MTK_MT9675,
+  SOC_MTK_MT9685,
+  SOC_MTK_MT9686,
+  SOC_MTK_MT9689,
+  SOC_MTK_MT9902,
+  SOC_MTK_MT9950,
+  SOC_MTK_MT9972,
+  SOC_MTK_MT9982,
   // Snapdragon //
   SOC_SNAPD_QSD8650,
   SOC_SNAPD_QSD8250,
@@ -259,6 +306,12 @@ enum {
   SOC_APPLE_M1_MAX,
   SOC_APPLE_M1_ULTRA,
   SOC_APPLE_M2,
+  SOC_APPLE_M2_PRO,
+  SOC_APPLE_M2_MAX,
+  SOC_APPLE_M2_ULTRA,
+  SOC_APPLE_M3,
+  SOC_APPLE_M3_PRO,
+  SOC_APPLE_M3_MAX,
   // ALLWINNER
   SOC_ALLWINNER_A10,
   SOC_ALLWINNER_A13,
@@ -288,20 +341,37 @@ enum {
   SOC_ALLWINNER_R58,
   SOC_ALLWINNER_R328,
   // ROCKCHIP
+  SOC_ROCKCHIP_3288,
+  SOC_ROCKCHIP_3229,
+  SOC_ROCKCHIP_3308,
+  SOC_ROCKCHIP_3318,
+  SOC_ROCKCHIP_3326,
+  SOC_ROCKCHIP_3328,
+  SOC_ROCKCHIP_3368,
   SOC_ROCKCHIP_3399,
+  SOC_ROCKCHIP_3528,
+  SOC_ROCKCHIP_3562,
+  SOC_ROCKCHIP_3566,
+  SOC_ROCKCHIP_3568,
+  SOC_ROCKCHIP_3588,
+  // GOOGLE
+  SOC_GOOGLE_TENSOR,
+  SOC_GOOGLE_TENSOR_G2,
+  SOC_GOOGLE_TENSOR_G3,
   // UNKNOWN
   SOC_MODEL_UNKNOWN
 };
 
 inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
-  if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_21654) return SOC_VENDOR_BROADCOM;
+  if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_2712) return SOC_VENDOR_BROADCOM;
   else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_3690) return SOC_VENDOR_KIRIN;
   else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
   else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
   else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8450) return SOC_VENDOR_SNAPDRAGON;
-  else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M2) return SOC_VENDOR_APPLE;
+  else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE;
   else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
-  else if(soc >= SOC_ROCKCHIP_3399 && soc <= SOC_ROCKCHIP_3399) return SOC_VENDOR_ROCKCHIP;
+  else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP;
+  else if(soc >= SOC_GOOGLE_TENSOR && soc <= SOC_GOOGLE_TENSOR_G3) return SOC_VENDOR_GOOGLE;
   return SOC_VENDOR_UNKNOWN;
 }
 

src/arm/sysctl.h

@@ -8,6 +8,9 @@
 // APPLE_CPU_PART_M2_BLIZZARD=0x30,M2_AVALANCHE=0x31
 #define MIDR_APPLE_M2_BLIZZARD  0x610F0300
 #define MIDR_APPLE_M2_AVALANCHE 0x610F0310
+// https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c
+#define MIDR_APPLE_M3_SAWTOOTH  0x610F0480
+#define MIDR_APPLE_M3_EVEREST   0x610F0490
 
 // M1 / A14
 #ifndef CPUFAMILY_ARM_FIRESTORM_ICESTORM
@@ -17,6 +20,12 @@
 #ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD
   #define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D
 #endif
+// M3 / A16 / A17
+// https://ratfactor.com/zig/stdlib-browseable2/c/darwin.zig.html
+// https://github.com/Dr-Noob/cpufetch/issues/210
+#define CPUFAMILY_ARM_EVEREST_SAWTOOTH     0x8765EDEA
+#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO 0x5F4DEA93
+#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX 0x72015832
 
 // For detecting different M1 types
 // NOTE: Could also be achieved detecting different

src/arm/uarch.c

@@ -68,10 +68,13 @@ enum {
   UARCH_CORTEX_A78,
   UARCH_CORTEX_A510,
   UARCH_CORTEX_A710,
+  UARCH_CORTEX_A715,
   UARCH_CORTEX_X1,
   UARCH_CORTEX_X2,
+  UARCH_CORTEX_X3,
   UARCH_NEOVERSE_N1,
   UARCH_NEOVERSE_E1,
+  UARCH_NEOVERSE_V1,
   UARCH_SCORPION,
   UARCH_KRAIT,
   UARCH_KYRO,
@@ -102,6 +105,8 @@ enum {
   UARCH_FIRESTORM,  // Apple M1 processor (big cores).
   UARCH_BLIZZARD,   // Apple M2 processor (little cores).
   UARCH_AVALANCHE,  // Apple M2 processor (big cores).
+  UARCH_SAWTOOTH,   // Apple M3 processor (little cores).
+  UARCH_EVEREST,    // Apple M3 processor (big cores).
   // CAVIUM
   UARCH_THUNDERX,   // Cavium ThunderX
   UARCH_THUNDERX2,  // Cavium ThunderX2 (originally Broadcom Vulkan).
@@ -142,10 +147,13 @@ static const ISA isas_uarch[] = {
   [UARCH_CORTEX_A78]   = ISA_ARMv8_2_A,
   [UARCH_CORTEX_A510]   = ISA_ARMv9_A,
   [UARCH_CORTEX_A710]   = ISA_ARMv9_A,
+  [UARCH_CORTEX_A715]  = ISA_ARMv9_A,
   [UARCH_CORTEX_X1]    = ISA_ARMv8_2_A,
   [UARCH_CORTEX_X2]    = ISA_ARMv9_A,
+  [UARCH_CORTEX_X3]    = ISA_ARMv9_A,
   [UARCH_NEOVERSE_N1]  = ISA_ARMv8_2_A,
   [UARCH_NEOVERSE_E1]  = ISA_ARMv8_2_A,
+  [UARCH_NEOVERSE_V1]  = ISA_ARMv8_4_A,
   [UARCH_BRAHMA_B15]   = ISA_ARMv7_A,   // Same as Cortex-A15
   [UARCH_BRAHMA_B53]   = ISA_ARMv8_A,   // Same as Cortex-A53
   [UARCH_THUNDERX]     = ISA_ARMv8_A,
@@ -192,7 +200,9 @@ static char* isas_string[] = {
 #define UARCH_START if (false) {}
 #define CHECK_UARCH(arch, cpu, im_, p_, v_, r_, str, uarch, vendor) \
    else if (im_ == im && p_ == p && (v_ == NA || v_ == v) && (r_ == NA || r_ == r)) fill_uarch(arch, cpu, str, uarch, vendor);
-#define UARCH_END else { printBug("Unknown microarchitecture detected: IM=0x%.8X P=0x%.8X V=0x%.8X R=0x%.8X", im, p, v, r); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
+#define UARCH_END else { printErr("Unknown microarchitecture detected: IM=0x%X P=0x%X V=0x%X R=0x%X", im, p, v, r); \
+fprintf(stderr, "Please see https://github.com/Dr-Noob/cpufetch#61-unknown-microarchitecture-error to know how to report this error\n"); \
+fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
 
 void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
   arch->uarch = u;
@@ -208,10 +218,11 @@ void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u,
 
 /*
  * Codes are based on pytorch/cpuinfo, more precisely:
- * - https://github.com/pytorch/cpuinfo/blob/master/src/arm/uarch.c
+ * - https://github.com/pytorch/cpuinfo/blob/main/src/arm/uarch.c
  * Other sources:
  * - https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/asm/cputype.h
  * - https://elixir.bootlin.com/linux/latest/source/arch/arm/include/asm/cputype.h
+ * - https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c
  */
 struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   struct uarch* arch = emalloc(sizeof(struct uarch));
@@ -254,12 +265,15 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   CHECK_UARCH(arch, cpu, 'A', 0xD0C, NA, NA, "Neoverse N1",           UARCH_NEOVERSE_N1,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD0D, NA, NA, "Cortex-A77",            UARCH_CORTEX_A77,   CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD0E, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD40, NA, NA, "Neoverse V1",           UARCH_NEOVERSE_V1,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD41, NA, NA, "Cortex-A78",            UARCH_CORTEX_A78,   CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD44, NA, NA, "Cortex-X1",             UARCH_CORTEX_X1,    CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD46, NA, NA, "Cortex‑A510",           UARCH_CORTEX_A510,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD47, NA, NA, "Cortex‑A710",           UARCH_CORTEX_A710,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD48, NA, NA, "Cortex-X2",             UARCH_CORTEX_X2,    CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD4A, NA, NA, "Neoverse E1",           UARCH_NEOVERSE_E1,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD4D, NA, NA, "Cortex-A715",           UARCH_CORTEX_A715,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD4E, NA, NA, "Cortex-X3",             UARCH_CORTEX_X3,    CPU_VENDOR_ARM)
 
   CHECK_UARCH(arch, cpu, 'B', 0x00F, NA, NA, "Brahma B15",            UARCH_BRAHMA_B15,   CPU_VENDOR_BROADCOM)
   CHECK_UARCH(arch, cpu, 'B', 0x100, NA, NA, "Brahma B53",            UARCH_BRAHMA_B53,   CPU_VENDOR_BROADCOM)
@@ -316,6 +330,8 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   CHECK_UARCH(arch, cpu, 'a', 0x023, NA, NA, "Firestorm",             UARCH_FIRESTORM,    CPU_VENDOR_APPLE)
   CHECK_UARCH(arch, cpu, 'a', 0x030, NA, NA, "Blizzard",              UARCH_BLIZZARD,     CPU_VENDOR_APPLE)
   CHECK_UARCH(arch, cpu, 'a', 0x031, NA, NA, "Avalanche",             UARCH_AVALANCHE,    CPU_VENDOR_APPLE)
+  CHECK_UARCH(arch, cpu, 'a', 0x048, NA, NA, "Sawtooth",              UARCH_SAWTOOTH,     CPU_VENDOR_APPLE)
+  CHECK_UARCH(arch, cpu, 'a', 0x049, NA, NA, "Everest",               UARCH_EVEREST,      CPU_VENDOR_APPLE)
 
   CHECK_UARCH(arch, cpu, 'V', 0x581, NA, NA, "PJ4",                   UARCH_PJ4,          CPU_VENDOR_MARVELL)
   CHECK_UARCH(arch, cpu, 'V', 0x584, NA, NA, "PJ4B-MP",               UARCH_PJ4,          CPU_VENDOR_MARVELL)
@@ -325,6 +341,99 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   return arch;
 }
 
+bool is_ARMv8_or_newer(struct cpuInfo* cpu) {
+  return cpu->arch->isa == ISA_ARMv8_A         ||
+         cpu->arch->isa == ISA_ARMv8_A_AArch32 ||
+         cpu->arch->isa == ISA_ARMv8_1_A       ||
+         cpu->arch->isa == ISA_ARMv8_2_A       ||
+         cpu->arch->isa == ISA_ARMv8_3_A       ||
+         cpu->arch->isa == ISA_ARMv8_4_A       ||
+         cpu->arch->isa == ISA_ARMv8_5_A       ||
+         cpu->arch->isa == ISA_ARMv9_A;
+}
+
+bool has_fma_support(struct cpuInfo* cpu) {
+  // Arm A64 Instruction Set Architecture
+  // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions
+  return is_ARMv8_or_newer(cpu);
+}
+
+int get_vpus_width(struct cpuInfo* cpu) {
+  // If the CPU has NEON, width can be 64 or 128 [1].
+  // In >= ARMv8, NEON are 128 bits width [2]
+  // If the CPU has SVE/SVE2, width can be between 128-2048 [3],
+  // so we must check the exact width depending on
+  // the exact chip (Neoverse V1 uses 256b implementations.)
+  //
+  // [1] https://en.wikipedia.org/wiki/ARM_architecture_family#Advanced_SIMD_(Neon)
+  // [2] https://developer.arm.com/documentation/102474/0100/Fundamentals-of-Armv8-Neon-technology
+  // [3] https://www.anandtech.com/show/16640/arm-announces-neoverse-v1-n2-platforms-cpus-cmn700-mesh/5
+
+  MICROARCH ua = cpu->arch->uarch;
+  switch(ua) {
+    case UARCH_NEOVERSE_V1:
+      return 256;
+    default:
+      if(cpu->feat->NEON) {
+        if(is_ARMv8_or_newer(cpu)) {
+          return 128;
+        }
+        else {
+          return 64;
+        }
+      }
+      else {
+        return 32;
+      }
+  }
+}
+
+int get_number_of_vpus(struct cpuInfo* cpu) {
+  MICROARCH ua = cpu->arch->uarch;
+
+  switch(ua) {
+    case UARCH_EVEREST:     // Just a guess, needs confirmation.
+    case UARCH_FIRESTORM:   // [https://dougallj.github.io/applecpu/firestorm-simd.html]
+    case UARCH_AVALANCHE:   // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
+    case UARCH_CORTEX_X1:   // [https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging/3]
+    case UARCH_CORTEX_X2:   // [https://www.anandtech.com/show/16693/arm-announces-mobile-armv9-cpu-microarchitectures-cortexx2-cortexa710-cortexa510/2]
+    case UARCH_CORTEX_X3:   // [https://www.hwcooling.net/en/cortex-x3-the-new-fastest-arm-core-architecture-analysis: "The FPU and SIMD unit of the core still has four pipelines"]
+    case UARCH_NEOVERSE_V1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v1]
+      return 4;
+    case UARCH_SAWTOOTH:    // Needs confirmation, rn this is the best we know: https://mastodon.social/@dougall/111118317031041336
+    case UARCH_EXYNOS_M3:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
+    case UARCH_EXYNOS_M4:   // [https://en.wikichip.org/wiki/samsung/microarchitectures/m4#Block_Diagram]
+    case UARCH_EXYNOS_M5:   // [https://en.wikichip.org/wiki/samsung/microarchitectures/m5]
+      return 3;
+    case UARCH_ICESTORM:    // [https://dougallj.github.io/applecpu/icestorm-simd.html]
+    case UARCH_BLIZZARD:    // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
+    case UARCH_CORTEX_A57:  // [https://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/5]
+    case UARCH_CORTEX_A72:  // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]
+    case UARCH_CORTEX_A73:  // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]
+    case UARCH_CORTEX_A75:  // [https://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55/3]
+    case UARCH_CORTEX_A76:  // [https://www.anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse/3]
+    case UARCH_CORTEX_A77:  // [https://fuse.wikichip.org/news/2339/arm-unveils-cortex-a77-emphasizes-single-thread-performance]
+    case UARCH_CORTEX_A78:  // [https://fuse.wikichip.org/news/3536/arm-unveils-the-cortex-a78-when-less-is-more]
+    case UARCH_EXYNOS_M1:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
+    case UARCH_EXYNOS_M2:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
+    case UARCH_NEOVERSE_N1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_n1#Individual_Core]
+    case UARCH_CORTEX_A710: // [https://chipsandcheese.com/2023/08/11/arms-cortex-a710-winning-by-default/]: Fig in Core Overview. Table in Instruction Scheduling and Execution
+    case UARCH_CORTEX_A715: // [https://www.hwcooling.net/en/arm-introduces-new-cortex-a715-core-architecture-analysis/]: "the numbers of ALU and FPU execution units themselves >
+      return 2;
+    case UARCH_NEOVERSE_E1: // [https://www.anandtech.com/show/13959/arm-announces-neoverse-n1-platform/5]
+    // A510 is integrated as part of a Complex. Normally, each complex would incorporate two Cortex-A510 cores.
+    // Each complex incorporates a single VPU with 2 ports, so for each A510 there is theoretically 1 port.
+    case UARCH_CORTEX_A510: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a510#Vector_Processing_Unit_.28VPU.29]
+      return 1;
+    default:
+      // ARMv6
+      // ARMv7
+      // Remaining UARCH_CORTEX_AXX
+      // Old Snapdragon (e.g., Scorpion, Krait, etc)
+      return 1;
+  }
+}
+
 char* get_str_uarch(struct cpuInfo* cpu) {
   return cpu->arch->uarch_str;
 }

src/arm/uarch.h

@@ -6,6 +6,9 @@
 #include "midr.h"
 
 struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu);
+int get_number_of_vpus(struct cpuInfo* cpu);
+int get_vpus_width(struct cpuInfo* cpu);
+bool has_fma_support(struct cpuInfo* cpu);
 char* get_str_uarch(struct cpuInfo* cpu);
 void free_uarch_struct(struct uarch* arch);
 

src/arm/udev.c

@@ -3,8 +3,6 @@
 #include "midr.h"
 
 #define _PATH_DEVICETREE_MODEL       "/sys/firmware/devicetree/base/model"
-#define _PATH_CPUINFO                "/proc/cpuinfo"
-//#define _PATH_CPUINFO                "cpuinfo_debug"
 
 #define CPUINFO_CPU_IMPLEMENTER_STR  "CPU implementer\t: "
 #define CPUINFO_CPU_ARCHITECTURE_STR "CPU architecture: "
@@ -108,27 +106,6 @@ uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success) {
   return midr;
 }
 
-char* get_field_from_cpuinfo(char* CPUINFO_FIELD) {
-  int filelen;
-  char* buf;
-  if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
-    printWarn("read_file: %s: %s:\n", _PATH_CPUINFO, strerror(errno));
-    return NULL;
-  }
-
-  char* tmp1 = strstr(buf, CPUINFO_FIELD);
-  if(tmp1 == NULL) return NULL;
-  tmp1 = tmp1 + strlen(CPUINFO_FIELD);
-  char* tmp2 = strstr(tmp1, "\n");
-
-  int strlen = (1 + (tmp2-tmp1));
-  char* hardware = emalloc(sizeof(char) * strlen);
-  memset(hardware, 0, sizeof(char) * strlen);
-  strncpy(hardware, tmp1, tmp2-tmp1);
-
-  return hardware;
-}
-
 char* get_hardware_from_cpuinfo(void) {
   return get_field_from_cpuinfo(CPUINFO_HARDWARE_STR);
 }

src/arm/udev.h

@@ -5,6 +5,7 @@
 
 #define _PATH_SUNXI_NVMEM  "/sys/bus/nvmem/devices/sunxi-sid0/nvmem"
 #define _PATH_RK_EFUSE0    "/sys/bus/nvmem/devices/rockchip-efuse0/nvmem"
+#define _PATH_RK_OTP0      "/sys/bus/nvmem/devices/rockchip-otp0/nvmem"
 
 #define UNKNOWN -1
 int get_ncores_from_cpuinfo(void);

src/common/ascii.h

@@ -33,7 +33,7 @@ struct ascii_logo {
   uint32_t width;
   uint32_t height;
   bool replace_blocks;
-  char color_ascii[3][100];
+  char color_ascii[4][100];
   char color_text[2][100];
 };
 
@@ -218,6 +218,23 @@ $C1    kMMMMMMMMMMMMMMMMMMMMMMd    \
 $C1     'KMMMMMMMWXXWMMMMMMMk.     \
 $C1       \"cooc\"*    \"*coo'\"       "
 
+#define ASCII_GOOGLE \
+"$C1            aaaaaaaa               \
+$C1        .MMMMMMMMMMMMMMMM.         \
+$C1     .MMMMMMMMMMMMMMMMMMMMM*       \
+$C1   .MMMMMMMM**        *MM*         \
+$C2  MM$C1MMMMM.                         \
+$C2 *MMM$C1MM.                           \
+$C2*MMMMMM          $C4lMMMMMMMMMMMMMMM* \
+$C2MMMMMMM          $C4lMMMMMMMMMMMMMMMM \
+$C2*MMMMMM          $C4lMMMMMMMMMMMMMMMd \
+$C2 MMMM$C3MMM.                  $C4*MMMMM. \
+$C2  MM$C3MMMMMM.              $C4.MMMMMM.  \
+$C3   *MMMMMMMMM*.......MMM$C4MMMMMM*    \
+$C3     *MMMMMMMMMMMMMMMMMMMM$C4MM*      \
+$C3         *MMMMMMMMMMMMMM*          \
+$C3              ******               "
+
 #define ASCII_ALLWINNER \
 "$C1                                               \
 $C1                #################              \
@@ -287,29 +304,6 @@ $C1 ################@@@@@@##@@@@@@################ \
 $C1 ####################@@@@@@#################### \
 $C1 ############################################## "
 
-#define ASCII_SIFIVE_L \
-"$C1 ################################################### \
-$C1 ###########@@@@@@@@@@@@@@@@@@@@@@@@@@@@############ \
-$C1 ##########@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@########### \
-$C1 #########@@@@@#######################@@@@########## \
-$C1 ########@@@@@#########################@@@@######### \
-$C1 #######@@@@@###########################@@@@######## \
-$C1 ######@@@@@########@@@@@@@@@@@@@@@@@@@@@@@@@####### \
-$C1 #####@@@@@########@@@@@@@@@@@@@@@@@@@@@@@@@@@###### \
-$C1 ####@@@@@################################@@@@@##### \
-$C1 ###@@@@@##################################@@@@@#### \
-$C1 ##@@@@@####################################@@@@@### \
-$C1 ##@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@#########@@@@### \
-$C1 ##@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@############@@@@### \
-$C1 ####@@@@@#############@@@@@@@############@@@@@##### \
-$C1 #######@@@@@@############@############@@@@@@####### \
-$C1 ##########@@@@@@###################@@@@@@########## \
-$C1 ##############@@@@@@###########@@@@@@############## \
-$C1 #################@@@@@@#####@@@@@@################# \
-$C1 ####################@@@@@@@@@@@#################### \
-$C1 ########################@@@######################## \
-$C1 ################################################### "
-
 #define ASCII_STARFIVE \
 "$C1                   #             \
 $C1               ##########        \
@@ -329,30 +323,23 @@ $C1    ########   ########          \
 $C1         #########               \
 $C1             #                   "
 
-#define ASCII_STARFIVE_L \
-"$C1                          #######                 \
-$C1                     ################.            \
-$C1                ############   ###########        \
-$C1            ############           ##########.    \
-$C1       ############           #         ######    \
-$C1    ###########               #####         ##    \
-$C1   #######.                   ##########          \
-$C1  ######            ###         *###########      \
-$C1  ######            #######.         ##########   \
-$C1   #########        ############         ######   \
-$C1     ###########.        ###########*         #   \
-$C1         ############        ############         \
-$C1   #         ############.       .###########     \
-$C1   ######         ###########         #########   \
-$C1   ##########         .######,            #####   \
-$C1      ############         ##.            #####.  \
-$C1           #########                   ########   \
-$C1    ##         #####               ##########.    \
-$C1    #######        #          ############        \
-$C1    ###########           ###########.            \
-$C1        ###########. ############                 \
-$C1            ################                      \
-$C1                 #######                          "
+#define ASCII_SIPEED \
+"$C1  ####################################   \
+$C1######@@################################ \
+$C1####@@##@@####@@@@@@@@@@@@@@@@########## \
+$C1######@@####@@@@@@@@@@@@@@@@@@########## \
+$C1#########@@@@########################### \
+$C1#######@@@@@@########################### \
+$C1#########@@@@########################### \
+$C1###########@@@@@@@@@@@@@@@############## \
+$C1##############@@@@@@@@@@@@@@@########### \
+$C1###########################@@@@@######## \
+$C1###########################@@@@@@####### \
+$C1###########################@@@@@######## \
+$C1##########@@@@@@@@@@@@@@@@@@@########### \
+$C1##########@@@@@@@@@@@@@@@@############## \
+$C1######################################## \
+$C1  ####################################   "
 
 // --------------------- LONG LOGOS ------------------------- //
 #define ASCII_AMD_L \
@@ -438,11 +425,59 @@ $C1 ############ ################## #########   ####   ######### \
 $C1                                                              \
 $C1 ############ ################   #########    ##    ######### "
 
+#define ASCII_SIFIVE_L \
+"$C1 ################################################### \
+$C1 ###########@@@@@@@@@@@@@@@@@@@@@@@@@@@@############ \
+$C1 ##########@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@########### \
+$C1 #########@@@@@#######################@@@@########## \
+$C1 ########@@@@@#########################@@@@######### \
+$C1 #######@@@@@###########################@@@@######## \
+$C1 ######@@@@@########@@@@@@@@@@@@@@@@@@@@@@@@@####### \
+$C1 #####@@@@@########@@@@@@@@@@@@@@@@@@@@@@@@@@@###### \
+$C1 ####@@@@@################################@@@@@##### \
+$C1 ###@@@@@##################################@@@@@#### \
+$C1 ##@@@@@####################################@@@@@### \
+$C1 ##@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@#########@@@@### \
+$C1 ##@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@############@@@@### \
+$C1 ####@@@@@#############@@@@@@@############@@@@@##### \
+$C1 #######@@@@@@############@############@@@@@@####### \
+$C1 ##########@@@@@@###################@@@@@@########## \
+$C1 ##############@@@@@@###########@@@@@@############## \
+$C1 #################@@@@@@#####@@@@@@################# \
+$C1 ####################@@@@@@@@@@@#################### \
+$C1 ########################@@@######################## \
+$C1 ################################################### "
+
+#define ASCII_STARFIVE_L \
+"$C1                          #######                 \
+$C1                     ################.            \
+$C1                ############   ###########        \
+$C1            ############           ##########.    \
+$C1       ############           #         ######    \
+$C1    ###########               #####         ##    \
+$C1   #######.                   ##########          \
+$C1  ######            ###         *###########      \
+$C1  ######            #######.         ##########   \
+$C1   #########        ############         ######   \
+$C1     ###########.        ###########*         #   \
+$C1         ############        ############         \
+$C1   #         ############.       .###########     \
+$C1   ######         ###########         #########   \
+$C1   ##########         .######,            #####   \
+$C1      ############         ##.            #####.  \
+$C1           #########                   ########   \
+$C1    ##         #####               ##########.    \
+$C1    #######        #          ############        \
+$C1    ###########           ###########.            \
+$C1        ###########. ############                 \
+$C1            ################                      \
+$C1                 #######                          "
+
 typedef struct ascii_logo asciiL;
 
-//                        ------------------------------------------------------------------------------------------------------+
+//                        +-----------------------------------------------------------------------------------------------------------------+
 //                        | LOGO             | W | H | REPLACE | COLORS LOGO (>0 && <10)                      | COLORS TEXT (=2)            |
-//                        ------------------------------------------------------------------------------------------------------+
+//                        +-----------------------------------------------------------------------------------------------------------------+
 asciiL logo_amd         = { ASCII_AMD,         39, 15, false, {C_FG_WHITE, C_FG_GREEN},                       {C_FG_WHITE,   C_FG_GREEN}   };
 asciiL logo_intel       = { ASCII_INTEL,       48, 14, false, {C_FG_CYAN},                                    {C_FG_CYAN,    C_FG_WHITE}   };
 asciiL logo_intel_new   = { ASCII_INTEL_NEW,   51,  9, false, {C_FG_CYAN},                                    {C_FG_CYAN,    C_FG_WHITE}   };
@@ -454,13 +489,15 @@ asciiL logo_broadcom    = { ASCII_BROADCOM,    44, 19, false, {C_FG_WHITE, C_FG_
 asciiL logo_arm         = { ASCII_ARM,         42,  5, false, {C_FG_CYAN},                                    {C_FG_WHITE,   C_FG_CYAN}    };
 asciiL logo_ibm         = { ASCII_IBM,         42,  9, false, {C_FG_CYAN, C_FG_WHITE},                        {C_FG_CYAN,    C_FG_WHITE}   };
 asciiL logo_apple       = { ASCII_APPLE,       32, 17, false, {C_FG_WHITE},                                   {C_FG_CYAN,    C_FG_B_WHITE} };
+asciiL logo_google      = { ASCII_GOOGLE,      35, 15, false, {C_FG_RED, C_FG_YELLOW, C_FG_GREEN, C_FG_BLUE}, {C_FG_BLUE,    C_FG_B_WHITE} };
 asciiL logo_allwinner   = { ASCII_ALLWINNER,   47, 16, false, {C_FG_CYAN},                                    {C_FG_B_BLACK, C_FG_B_CYAN } };
 asciiL logo_rockchip    = { ASCII_ROCKCHIP,    58,  8, false, {C_FG_CYAN, C_FG_YELLOW},                       {C_FG_CYAN,    C_FG_YELLOW}  };
 asciiL logo_riscv       = { ASCII_RISCV,       63, 18, false, {C_FG_CYAN, C_FG_YELLOW},                       {C_FG_CYAN,    C_FG_YELLOW}  };
 asciiL logo_sifive      = { ASCII_SIFIVE,      48, 19, true,  {C_BG_WHITE, C_BG_BLACK},                       {C_FG_WHITE,   C_FG_BLUE}    };
 asciiL logo_starfive    = { ASCII_STARFIVE,    33, 17, false, {C_FG_WHITE},                                   {C_FG_WHITE,   C_FG_BLUE}    };
+asciiL logo_sipeed      = { ASCII_SIPEED,      41, 16, true,  {C_BG_RED, C_BG_WHITE},                         {C_FG_RED,     C_FG_WHITE}   };
 
-// Long variants          | ----------------------------------------------------------------------------------------------------|
+// Long variants          | ----------------------------------------------------------------------------------------------------------------|
 asciiL logo_amd_l       = { ASCII_AMD_L,       62, 19, true,  {C_BG_WHITE, C_BG_GREEN},                       {C_FG_WHITE, C_FG_GREEN}     };
 asciiL logo_intel_l     = { ASCII_INTEL_L,     62, 19, true,  {C_BG_CYAN, C_BG_WHITE},                        {C_FG_CYAN,  C_FG_WHITE}     };
 asciiL logo_intel_l_new = { ASCII_INTEL_L_NEW, 57, 14, true,  {C_BG_CYAN, C_BG_WHITE, C_BG_BLUE},             {C_FG_CYAN,  C_FG_WHITE}     };

src/common/cpu.c

@@ -194,7 +194,7 @@ void init_topology_struct(struct topology* topo, struct cache* cach) {
   topo->sockets = 0;
 #ifdef ARCH_X86
   topo->smt_available = 0;
-  topo->apic = emalloc(sizeof(struct apic));
+  topo->apic = ecalloc(1, sizeof(struct apic));
 #endif
 #endif
 }

src/common/cpu.h

@@ -36,6 +36,9 @@ enum {
   HV_VENDOR_VMWARE,
   HV_VENDOR_XEN,
   HV_VENDOR_PARALLELS,
+  HV_VENDOR_PHYP,
+  HV_VENDOR_BHYVE,
+  HV_VENDOR_APPLEVZ,
   HV_VENDOR_INVALID
 };
 
@@ -122,7 +125,7 @@ struct features {
 
 struct extensions {
   char* str;
-  uint32_t mask;
+  uint64_t mask;
 };
 
 struct cpuInfo {

src/common/global.c

@@ -51,7 +51,7 @@
 #endif
 
 #ifndef GIT_FULL_VERSION
-  static const char* VERSION = "1.03";
+  static const char* VERSION = "1.04";
 #endif
 
 enum {

src/common/main.c

@@ -40,11 +40,13 @@ void print_help(char *argv[]) {
   printf("  -%c, --%s %*s Print cpufetch version and exit\n", c[ARG_VERSION], t[ARG_VERSION], (int) (max_len-strlen(t[ARG_VERSION])), "");
 
   printf("\nCOLORS: \n");
-  printf("  * \"intel\":     Use Intel default color scheme \n");
-  printf("  * \"amd\":       Use AMD default color scheme \n");
-  printf("  * \"ibm\",       Use IBM default color scheme \n");
-  printf("  * \"arm\":       Use ARM default color scheme \n");
-  printf("  * \"sifive\":    Use SiFive default color scheme \n");
+  printf("  * \"intel\":     Use Intel color scheme \n");
+  printf("  * \"intel-new\": Use Intel (new logo) color scheme \n");
+  printf("  * \"amd\":       Use AMD color scheme \n");
+  printf("  * \"ibm\",       Use IBM color scheme \n");
+  printf("  * \"arm\":       Use ARM color scheme \n");
+  printf("  * \"rockchip\":  Use ARM color scheme \n");
+  printf("  * \"sifive\":    Use SiFive color scheme \n");
   printf("  * custom:      If the argument of --color does not match any of the previous strings, a custom scheme can be specified.\n");
   printf("                 5 colors must be given in RGB with the format: R,G,B:R,G,B:...\n");
   printf("                 The first 3 colors are the CPU art color and the next 2 colors are the text colors\n");
@@ -74,8 +76,10 @@ void print_help(char *argv[]) {
   printf("\nNOTE: \n");
   printf("    Peak performance information is NOT accurate. cpufetch computes peak performance using the max\n");
   printf("    frequency of the CPU. However, to compute the peak performance, you need to know the frequency of the\n");
-  printf("    CPU running AVX code. This value is not be fetched by cpufetch since it depends on each specific CPU.\n");
-  printf("    To correctly measure peak performance, see: https://github.com/Dr-Noob/peakperf\n");
+  printf("    CPU running AVX code. By default, this value is not fetched by cpufetch, but you can use the\n");
+  printf("    --accurate-pp option, which will measure the AVX frequency and show a more precise estimation\n");
+  printf("    (this option is only available in x86 architectures).\n");
+  printf("    To precisely measure peak performance, see: https://github.com/Dr-Noob/peakperf\n");
 }
 
 int main(int argc, char* argv[]) {
@@ -116,8 +120,10 @@ int main(int argc, char* argv[]) {
   #endif
   }
 
-  if(print_cpufetch(cpu, get_style(), get_colors(), show_full_cpu_name()))
+  if(print_cpufetch(cpu, get_style(), get_colors(), show_full_cpu_name())) {
     return EXIT_SUCCESS;
-  else
+  }
+  else {
     return EXIT_FAILURE;
+  }
 }

src/common/printer.c

@@ -20,6 +20,7 @@
   #include "../arm/uarch.h"
   #include "../arm/midr.h"
   #include "../arm/soc.h"
+  #include "../common/soc.h"
 #elif ARCH_RISCV
   #include "../riscv/riscv.h"
   #include "../riscv/uarch.h"
@@ -367,6 +368,8 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
     art->art = &logo_broadcom;
   else if(art->vendor == SOC_VENDOR_APPLE)
     art->art = &logo_apple;
+  else if(art->vendor == SOC_VENDOR_GOOGLE)
+    art->art = &logo_google;
   else if(art->vendor == SOC_VENDOR_ALLWINNER)
     art->art = &logo_allwinner;
   else if(art->vendor == SOC_VENDOR_ROCKCHIP)
@@ -381,6 +384,8 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
     art->art = choose_ascii_art_aux(&logo_starfive_l, &logo_starfive, term, lf);
   else if(art->vendor == SOC_VENDOR_ALLWINNER)
     art->art = &logo_allwinner;
+  else if(art->vendor == SOC_VENDOR_SIPEED)
+    art->art = &logo_sipeed;
   else
     art->art = &logo_riscv;
 #endif
@@ -677,11 +682,14 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
 
   // Step 2. Set attributes
   if(cpu_name != NULL) {
-    setAttribute(art,ATTRIBUTE_NAME,cpu_name);
+    setAttribute(art, ATTRIBUTE_NAME, cpu_name);
   }
-  setAttribute(art,ATTRIBUTE_UARCH,uarch);
-  setAttribute(art,ATTRIBUTE_TECHNOLOGY,manufacturing_process);
-  setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency);
+  setAttribute(art, ATTRIBUTE_UARCH, uarch);
+  if(cpu->hv->present) {
+    setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
+  }
+  setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
+  setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
   uint32_t socket_num = get_nsockets(cpu->topo);
   if (socket_num > 1) {
     setAttribute(art, ATTRIBUTE_SOCKETS, sockets);
@@ -689,16 +697,16 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     setAttribute(art, ATTRIBUTE_NCORES_DUAL, n_cores_dual);
   }
   else {
-    setAttribute(art,ATTRIBUTE_NCORES, n_cores);
+    setAttribute(art, ATTRIBUTE_NCORES, n_cores);
   }
-  setAttribute(art,ATTRIBUTE_ALTIVEC, altivec);
-  setAttribute(art,ATTRIBUTE_L1i,l1i);
-  setAttribute(art,ATTRIBUTE_L1d,l1d);
-  setAttribute(art,ATTRIBUTE_L2,l2);
+  setAttribute(art, ATTRIBUTE_ALTIVEC, altivec);
+  setAttribute(art, ATTRIBUTE_L1i, l1i);
+  setAttribute(art, ATTRIBUTE_L1d, l1d);
+  setAttribute(art, ATTRIBUTE_L2, l2);
   if(l3 != NULL) {
-    setAttribute(art,ATTRIBUTE_L3,l3);
+    setAttribute(art, ATTRIBUTE_L3, l3);
   }
-  setAttribute(art,ATTRIBUTE_PEAK,pp);
+  setAttribute(art, ATTRIBUTE_PEAK, pp);
 
   // Step 3. Print output
   const char** attribute_fields = ATTRIBUTE_FIELDS;
@@ -839,26 +847,17 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   char* manufacturing_process = get_str_process(cpu->soc);
   char* soc_name = get_soc_name(cpu->soc);
   char* features = get_str_features(cpu);
-  setAttribute(art,ATTRIBUTE_SOC,soc_name);
-  setAttribute(art,ATTRIBUTE_TECHNOLOGY,manufacturing_process);
+  setAttribute(art, ATTRIBUTE_SOC, soc_name);
+  setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
 
   if(cpu->num_cpus == 1) {
     char* uarch = get_str_uarch(cpu);
     char* max_frequency = get_str_freq(cpu->freq);
     char* n_cores = get_str_topology(cpu, cpu->topo, false);
-    /*
-     * char* l1i = get_str_l1i(cpu->cach);
-     * char* l1d = get_str_l1d(cpu->cach);
-     * char* l2 = get_str_l2(cpu->cach);
-     * char* l3 = get_str_l3(cpu->cach);
-     * Do not setAttribute for caches.
-     * Cache functionality may be implemented
-     * in the future
-    */
 
-    setAttribute(art,ATTRIBUTE_UARCH,uarch);
-    setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency);
-    setAttribute(art,ATTRIBUTE_NCORES,n_cores);
+    setAttribute(art, ATTRIBUTE_UARCH, uarch);
+    setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
+    setAttribute(art, ATTRIBUTE_NCORES, n_cores);
     if(features != NULL) {
       setAttribute(art, ATTRIBUTE_FEATURES, features);
     }
@@ -869,17 +868,8 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
       char* uarch = get_str_uarch(ptr);
       char* max_frequency = get_str_freq(ptr->freq);
       char* n_cores = get_str_topology(ptr, ptr->topo, false);
-      /*
-       * char* l1i = get_str_l1i(cpu->cach);
-       * char* l1d = get_str_l1d(cpu->cach);
-       * char* l2 = get_str_l2(cpu->cach);
-       * char* l3 = get_str_l3(cpu->cach);
-       * Do not setAttribute for caches.
-       * Cache functionality may be implemented
-       * in the future
-       */
-
       char* cpu_num = emalloc(sizeof(char) * 9);
+
       sprintf(cpu_num, "CPU %d:", i+1);
       setAttribute(art, ATTRIBUTE_CPU_NUM, cpu_num);
       setAttribute(art, ATTRIBUTE_UARCH, uarch);
@@ -891,7 +881,7 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     }
   }
   char* pp = get_str_peak_performance(cpu->peak_performance);
-  setAttribute(art,ATTRIBUTE_PEAK,pp);
+  setAttribute(art, ATTRIBUTE_PEAK, pp);
   if(cpu->hv->present) {
     setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
   }
@@ -931,16 +921,14 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
 #endif
 
 #ifdef ARCH_RISCV
-// https://stackoverflow.com/questions/109023/count-the-number-of-set-bits-in-a-32-bit-integer
-int number_of_bits(uint32_t i) {
-  i = i - ((i >> 1) & 0x55555555);                 // add pairs of bits
-  i = (i & 0x33333333) + ((i >> 2) & 0x33333333);  // quads
-  i = (i + (i >> 4)) & 0x0F0F0F0F;                 // groups of 8
-
-  return (i * 0x01010101) >> 24;                   // horizontal sum of bytes
+// https://stackoverflow.com/a/2709523
+uint64_t number_of_bits(uint64_t i) {
+  i = i - ((i >> 1) & 0x5555555555555555);
+  i = (i & 0x3333333333333333) + ((i >> 2) & 0x3333333333333333);
+  return (((i + (i >> 4)) & 0xF0F0F0F0F0F0F0F) * 0x101010101010101) >> 56;
 }
 
-void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, uint32_t extensions_mask) {
+void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, uint64_t extensions_mask) {
   struct ascii_logo* logo = art->art;
   int attr_to_print = 0;
   int attr_type;
@@ -954,7 +942,7 @@ void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char
   int32_t space_up = ((int)logo->height - (int)(art->n_attributes_set + num_extensions))/2;
   int32_t space_down = (int)logo->height - (int)(art->n_attributes_set + num_extensions) - (int)space_up;
   uint32_t logo_pos = 0;
-  int32_t iters = max(logo->height, art->n_attributes_set);
+  int32_t iters = max(logo->height, art->n_attributes_set + num_extensions);
 
   struct line_buffer* lbuf = emalloc(sizeof(struct line_buffer));
   lbuf->buf = emalloc(sizeof(char) * LINE_BUFFER_SIZE);
@@ -1035,29 +1023,18 @@ bool print_cpufetch_riscv(struct cpuInfo* cpu, STYLE s, struct color** cs, struc
   char* extensions = get_str_extensions(cpu);
   char* max_frequency = get_str_freq(cpu->freq);
   char* n_cores = get_str_topology(cpu, cpu->topo);
-
-  /*char* l1i = get_str_l1i(cpu->cach);
-  char* l1d = get_str_l1d(cpu->cach);
-  char* l2 = get_str_l2(cpu->cach);
-  char* l3 = get_str_l3(cpu->cach);*/
   char* pp = get_str_peak_performance(cpu->peak_performance);
 
   // Step 2. Set attributes
-  setAttribute(art,ATTRIBUTE_SOC,soc_name);
-  setAttribute(art,ATTRIBUTE_TECHNOLOGY,manufacturing_process);
-  setAttribute(art,ATTRIBUTE_UARCH,uarch);
-  setAttribute(art,ATTRIBUTE_NCORES, n_cores);
-  setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency);
+  setAttribute(art, ATTRIBUTE_SOC, soc_name);
+  setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
+  setAttribute(art, ATTRIBUTE_UARCH, uarch);
+  setAttribute(art, ATTRIBUTE_NCORES, n_cores);
+  setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
   if(extensions != NULL) {
-    setAttribute(art,ATTRIBUTE_EXTENSIONS,extensions);
+    setAttribute(art, ATTRIBUTE_EXTENSIONS, extensions);
   }
-  /*setAttribute(art,ATTRIBUTE_L1i,l1i);
-  setAttribute(art,ATTRIBUTE_L1d,l1d);
-  setAttribute(art,ATTRIBUTE_L2,l2);
-  if(l3 != NULL) {
-    setAttribute(art,ATTRIBUTE_L3,l3);
-  }*/
-  setAttribute(art,ATTRIBUTE_PEAK,pp);
+  setAttribute(art, ATTRIBUTE_PEAK, pp);
 
   // Step 3. Print output
   const char** attribute_fields = ATTRIBUTE_FIELDS;

src/common/soc.c

@@ -0,0 +1,90 @@
+#include "soc.h"
+#ifdef ARCH_ARM
+  #include "../arm/socs.h"
+#elif ARCH_RISCV
+  #include "../riscv/socs.h"
+#endif
+#include "udev.h"
+#include "../common/global.h"
+
+#include <string.h>
+
+static char* soc_trademark_string[] = {
+  // ARM
+  [SOC_VENDOR_SNAPDRAGON] = "Snapdragon ",
+  [SOC_VENDOR_MEDIATEK]   = "MediaTek ",
+  [SOC_VENDOR_EXYNOS]     = "Exynos ",
+  [SOC_VENDOR_KIRIN]      = "Kirin ",
+  [SOC_VENDOR_BROADCOM]   = "Broadcom BCM",
+  [SOC_VENDOR_APPLE]      = "Apple ",
+  [SOC_VENDOR_ROCKCHIP]   = "Rockchip ",
+  [SOC_VENDOR_GOOGLE]     = "Google ",
+  // RISC-V
+  [SOC_VENDOR_SIFIVE]     = "SiFive ",
+  [SOC_VENDOR_STARFIVE]   = "StarFive ",
+  [SOC_VENDOR_SIPEED]     = "Sipeed ",
+  // ARM & RISC-V
+  [SOC_VENDOR_ALLWINNER]  = "Allwinner "
+};
+
+VENDOR get_soc_vendor(struct system_on_chip* soc) {
+  return soc->soc_vendor;
+}
+
+char* get_str_process(struct system_on_chip* soc) {
+  char* str;
+
+  if(soc->process == UNKNOWN) {
+    str = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
+    snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+  }
+  else {
+    str = emalloc(sizeof(char) * 5);
+    memset(str, 0, sizeof(char) * 5);
+    snprintf(str, 5, "%dnm", soc->process);
+  }
+  return str;
+}
+
+char* get_soc_name(struct system_on_chip* soc) {
+  if(soc->soc_model == SOC_MODEL_UNKNOWN)
+    return soc->raw_name;
+  return soc->soc_name;
+}
+
+void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process) {
+  soc->soc_model = soc_model;
+  soc->soc_vendor = get_soc_vendor_from_soc(soc_model);
+  soc->process = process;
+  if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+    printBug("fill_soc: soc->soc_vendor == SOC_VENDOR_UNKOWN");
+    // If we fall here there is a bug in socs.h
+    // Reset everything to avoid segfault
+    soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+    soc->soc_model = SOC_MODEL_UNKNOWN;
+    soc->process = UNKNOWN;
+    soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
+    snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+  }
+  else {
+    soc->process = process;
+    int len = strlen(soc_name) + strlen(soc_trademark_string[soc->soc_vendor]) + 1;
+    soc->soc_name = emalloc(sizeof(char) * len);
+    memset(soc->soc_name, 0, sizeof(char) * len);
+    sprintf(soc->soc_name, "%s%s", soc_trademark_string[soc->soc_vendor], soc_name);
+  }
+}
+
+bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
+  int len1 = strlen(raw_name);
+  int len2 = strlen(expected_name);
+  int len = min(len1, len2);
+
+  if(strncmp(raw_name, expected_name, len) != 0) {
+    return false;
+  }
+  else {
+    fill_soc(soc, soc_name, soc_model, process);
+    return true;
+  }
+}

src/common/soc.h

@@ -0,0 +1,54 @@
+#ifndef __SOC__
+#define __SOC__
+
+// NOTE:
+// soc.c/soc.h are used by
+// ARM and RISC-V backends
+
+#include "../common/cpu.h"
+#include <stdint.h>
+
+#define UNKNOWN -1
+
+typedef int32_t SOC;
+
+enum {
+  SOC_VENDOR_UNKNOWN,
+  // ARM
+  SOC_VENDOR_SNAPDRAGON,
+  SOC_VENDOR_MEDIATEK,
+  SOC_VENDOR_EXYNOS,
+  SOC_VENDOR_KIRIN,
+  SOC_VENDOR_BROADCOM,
+  SOC_VENDOR_APPLE,
+  SOC_VENDOR_ROCKCHIP,
+  SOC_VENDOR_GOOGLE,
+  // RISC-V
+  SOC_VENDOR_SIFIVE,
+  SOC_VENDOR_STARFIVE,
+  SOC_VENDOR_SIPEED,
+  // ARM & RISC-V
+  SOC_VENDOR_ALLWINNER
+};
+
+struct system_on_chip {
+  SOC soc_model;
+  VENDOR soc_vendor;
+  int32_t process;
+  char* soc_name;
+  char* raw_name;
+};
+
+struct system_on_chip* get_soc(void);
+char* get_soc_name(struct system_on_chip* soc);
+VENDOR get_soc_vendor(struct system_on_chip* soc);
+bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process);
+char* get_str_process(struct system_on_chip* soc);
+void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process);
+
+#define SOC_START if (false) {}
+#define SOC_EQ(raw_name, expected_name, soc_name, soc_model, soc, process) \
+   else if (match_soc(soc, raw_name, expected_name, soc_name, soc_model, process)) return true;
+#define SOC_END else { return false; }
+
+#endif

src/common/udev.c

@@ -129,6 +129,27 @@ long get_cache_size_from_file(char* path) {
   return ret * 1024;
 }
 
+char* get_field_from_cpuinfo(char* CPUINFO_FIELD) {
+  int filelen;
+  char* buf;
+  if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
+    printWarn("read_file: %s: %s:\n", _PATH_CPUINFO, strerror(errno));
+    return NULL;
+  }
+
+  char* tmp1 = strstr(buf, CPUINFO_FIELD);
+  if(tmp1 == NULL) return NULL;
+  tmp1 = tmp1 + strlen(CPUINFO_FIELD);
+  char* tmp2 = strstr(tmp1, "\n");
+
+  int strlen = (1 + (tmp2-tmp1));
+  char* hardware = emalloc(sizeof(char) * strlen);
+  memset(hardware, 0, sizeof(char) * strlen);
+  strncpy(hardware, tmp1, tmp2-tmp1);
+
+  return hardware;
+}
+
 long get_max_freq_from_file(uint32_t core) {
   char path[_PATH_FREQUENCY_MAX_LEN];
   sprintf(path, "%s%s/cpu%d%s%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_FREQUENCY, _PATH_FREQUENCY_MAX);
@@ -178,7 +199,13 @@ bool maps_equal(uint32_t* map1, uint32_t* map2, int n) {
   return true;
 }
 
-int get_num_caches_from_files(char** paths, int num_paths) {
+// Generic function to count the number of distinct
+// elements in the list of files passed in char** paths.
+// An element can be potentially anything.
+// We use this function to count:
+// - The number of caches
+// - The number of sockets
+int get_num_elements_from_files(char** paths, int num_paths) {
   int filelen;
   char* buf;
   char* tmpbuf;
@@ -193,10 +220,10 @@ int get_num_caches_from_files(char** paths, int num_paths) {
     num_bitmasks += (buf[i] == ',');
   }
 
-  // 2. Read cpu_shared_map from every core
-  uint32_t** shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
+  // 2. Read map from every core
+  uint32_t** maps = emalloc(sizeof(uint32_t *) * num_paths);
   for(int i=0; i < num_paths; i++) {
-    shared_maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
+    maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
 
     if((buf = read_file(paths[i], &filelen)) == NULL) {
       printWarn("Could not open '%s'", paths[i]);
@@ -206,6 +233,7 @@ int get_num_caches_from_files(char** paths, int num_paths) {
     for(int j=0; j < num_bitmasks; j++) {
       char* end;
       tmpbuf = emalloc(sizeof(char) * (strlen(buf) + 1));
+      memset(tmpbuf, 0, sizeof(char) * (strlen(buf) + 1));
       char* commaend = strstr(buf, ",");
       if(commaend == NULL) {
         strcpy(tmpbuf, buf);
@@ -221,35 +249,43 @@ int get_num_caches_from_files(char** paths, int num_paths) {
         return -1;
       }
 
-      shared_maps[i][j] = (uint32_t) ret;
+      maps[i][j] = (uint32_t) ret;
       buf = commaend + 1;
       free(tmpbuf);
     }
   }
 
-  // 2. Count number of different masks; this is the number of caches
-  int num_caches = 0;
+  // 2. Count number of different masks; this is the number of elements
+  int num_elements = 0;
   bool found = false;
-  uint32_t** unique_shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
+  uint32_t** unique_maps = emalloc(sizeof(uint32_t *) * num_paths);
   for(int i=0; i < num_paths; i++) {
-    unique_shared_maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
+    unique_maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
     for(int j=0; j < num_bitmasks; j++) {
-      unique_shared_maps[i][j] = 0;
+      unique_maps[i][j] = 0;
     }
   }
 
   for(int i=0; i < num_paths; i++) {
     for(int j=0; j < num_paths && !found; j++) {
-      if(maps_equal(shared_maps[i], unique_shared_maps[j], num_bitmasks)) found = true;
+      if(maps_equal(maps[i], unique_maps[j], num_bitmasks)) found = true;
     }
     if(!found) {
-      add_shared_map(shared_maps, i, unique_shared_maps, num_caches, num_bitmasks);
-      num_caches++;
+      add_shared_map(maps, i, unique_maps, num_elements, num_bitmasks);
+      num_elements++;
     }
     found = false;
   }
 
-  return num_caches;
+  return num_elements;
+}
+
+int get_num_caches_from_files(char** paths, int num_paths) {
+  return get_num_elements_from_files(paths, num_paths);
+}
+
+int get_num_sockets_from_files(char** paths, int num_paths) {
+  return get_num_elements_from_files(paths, num_paths);
 }
 
 int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level) {
@@ -278,3 +314,38 @@ int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level) {
 
   return ret;
 }
+
+int get_num_sockets_package_cpus(struct topology* topo) {
+  // Get number of sockets using
+  // /sys/devices/system/cpu/cpu*/topology/package_cpus
+
+  char** paths = emalloc(sizeof(char *) * topo->total_cores);
+
+  for(int i=0; i < topo->total_cores; i++) {
+    paths[i] = emalloc(sizeof(char) * _PATH_PACKAGE_MAX_LEN);
+    sprintf(paths[i], "%s%s/cpu%d%s",  _PATH_SYS_SYSTEM, _PATH_SYS_CPU, i, _PATH_TOPO_PACKAGE_CPUS);
+  }
+
+  int ret = get_num_sockets_from_files(paths, topo->total_cores);
+
+  for(int i=0; i < topo->total_cores; i++)
+    free(paths[i]);
+  free(paths);
+
+  return ret;
+}
+
+// Inspired in is_devtree_compatible from lscpu
+bool is_devtree_compatible(char* str) {
+  int filelen;
+  char* buf;
+  if((buf = read_file("/proc/device-tree/compatible", &filelen)) == NULL) {
+    return false;
+  }
+
+  char* tmp;
+  if((tmp = strstr(buf, str)) == NULL) {
+    return false;
+  }
+  return true;
+}

src/common/udev.h

@@ -12,6 +12,7 @@
 
 #include "cpu.h"
 
+#define _PATH_CPUINFO           "/proc/cpuinfo"
 #define _PATH_SYS_SYSTEM        "/sys/devices/system"
 #define _PATH_SYS_CPU           "/cpu"
 #define _PATH_FREQUENCY         "/cpufreq"
@@ -24,9 +25,11 @@
 #define _PATH_CACHE_SIZE        "/size"
 #define _PATH_CACHE_SHARED_MAP  "/shared_cpu_map"
 #define _PATH_CPUS_PRESENT      _PATH_SYS_SYSTEM _PATH_SYS_CPU "/present"
+#define _PATH_TOPO_PACKAGE_CPUS "/topology/package_cpus"
 
 #define _PATH_FREQUENCY_MAX_LEN 100
 #define _PATH_CACHE_MAX_LEN     200
+#define _PATH_PACKAGE_MAX_LEN   200
 
 char* read_file(char* path, int* len);
 long get_max_freq_from_file(uint32_t core);
@@ -36,6 +39,9 @@ long get_l1d_cache_size(uint32_t core);
 long get_l2_cache_size(uint32_t core);
 long get_l3_cache_size(uint32_t core);
 int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level);
+int get_num_sockets_package_cpus(struct topology* topo);
 int get_ncores_from_cpuinfo(void);
+char* get_field_from_cpuinfo(char* CPUINFO_FIELD);
+bool is_devtree_compatible(char* str);
 
 #endif

src/ppc/ppc.c

@@ -11,6 +11,19 @@
 #include "../common/udev.h"
 #include "../common/global.h"
 
+static char *hv_vendors_name[] = {
+  [HV_VENDOR_KVM]       = "KVM",
+  [HV_VENDOR_QEMU]      = "QEMU",
+  [HV_VENDOR_HYPERV]    = "Microsoft Hyper-V",
+  [HV_VENDOR_VMWARE]    = "VMware",
+  [HV_VENDOR_XEN]       = "Xen",
+  [HV_VENDOR_PARALLELS] = "Parallels",
+  [HV_VENDOR_PHYP]      = "pHyp",
+  [HV_VENDOR_BHYVE]     = "bhyve",
+  [HV_VENDOR_APPLEVZ]   = "Apple VZ",
+  [HV_VENDOR_INVALID]   = STRING_UNKNOWN
+};
+
 struct cache* get_cache_info(struct cpuInfo* cpu) {
   struct cache* cach = emalloc(sizeof(struct cache));
   init_cache_struct(cach);
@@ -63,12 +76,17 @@ struct topology* get_topology_info(struct cache* cach) {
     printWarn("fill_core_ids_from_sys failed, output may be incomplete/invalid");
     for(int i=0; i < topo->total_cores; i++) core_ids[i] = 0;
   }
+
   if(!fill_package_ids_from_sys(package_ids, topo->total_cores)) {
     printWarn("fill_package_ids_from_sys failed, output may be incomplete/invalid");
     for(int i=0; i < topo->total_cores; i++) package_ids[i] = 0;
+    // fill_package_ids_from_sys failed, use a
+    // more sophisticated wat to find the number of sockets
+    topo->sockets = get_num_sockets_package_cpus(topo);
   }
-
-  // 2. Socket detection
+  else {
+    // fill_package_ids_from_sys succeeded, use the
+    // traditional socket detection algorithm
     int *package_ids_count = emalloc(sizeof(int) * topo->total_cores);
     for(int i=0; i < topo->total_cores; i++) {
       package_ids_count[i] = 0;
@@ -81,6 +99,8 @@ struct topology* get_topology_info(struct cache* cach) {
         topo->sockets++;
       }
     }
+    free(package_ids_count);
+  }
 
   // 3. Physical cores detection
   int *core_ids_unified = emalloc(sizeof(int) * topo->total_cores);
@@ -105,7 +125,6 @@ struct topology* get_topology_info(struct cache* cach) {
 
   free(core_ids);
   free(package_ids);
-  free(package_ids_count);
   free(core_ids_unified);
 
   return topo;
@@ -129,6 +148,12 @@ struct frequency* get_frequency_info(void) {
   freq->max = get_max_freq_from_file(0);
   freq->base = get_min_freq_from_file(0);
 
+  if(freq->max == UNKNOWN_DATA) {
+    // If we are unable to find it in the
+    // standard path, try /proc/cpuinfo
+    freq->max = get_frequency_from_cpuinfo();
+  }
+
   return freq;
 }
 
@@ -158,6 +183,28 @@ int64_t get_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t
   return flops;
 }
 
+struct hypervisor* get_hp_info(void) {
+  struct hypervisor* hv = emalloc(sizeof(struct hypervisor));
+  hv->present = false;
+
+  // Weird heuristic found in lscpu:
+  // https://github.com/util-linux/util-linux/blob/master/sys-utils/lscpu-virt.c
+  if(access("/proc" _PATH_DT_IBM_PARTIT_NAME, F_OK) == 0 &&
+     access("/proc" _PATH_DT_HMC_MANAGED, F_OK) == 0 &&
+     access("/proc" _PATH_DT_QEMU_WIDTH, F_OK) != 0) {
+    hv->present = true;
+    hv->hv_vendor = HV_VENDOR_PHYP;
+  }
+  else if(is_devtree_compatible("qemu,pseries")) {
+    hv->present = true;
+    hv->hv_vendor = HV_VENDOR_QEMU;
+  }
+
+  hv->hv_name = hv_vendors_name[hv->hv_vendor];
+
+  return hv;
+}
+
 struct cpuInfo* get_cpu_info(void) {
   struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
   struct features* feat = emalloc(sizeof(struct features));
@@ -172,8 +219,11 @@ struct cpuInfo* get_cpu_info(void) {
   char* path = emalloc(sizeof(char) * (strlen(_PATH_DT) + strlen(_PATH_DT_PART) + 1));
   sprintf(path, "%s%s", _PATH_DT, _PATH_DT_PART);
 
-  cpu->cpu_name = read_file(path, &len);
+  if((cpu->cpu_name = read_file(path, &len)) == NULL) {
+    printWarn("Could not open '%s'", path);
+  }
   cpu->pvr = mfpvr();
+  cpu->hv = get_hp_info();
   cpu->arch = get_cpu_uarch(cpu);
   cpu->freq = get_frequency_info();
   cpu->topo = get_topology_info(cpu->cach);

src/ppc/uarch.c

@@ -35,6 +35,7 @@ enum {
   UARCH_POWER7,
   UARCH_POWER7PLUS,
   UARCH_POWER8,
+  UARCH_POWER8_DD21,
   UARCH_POWER9,
   UARCH_POWER9_DD20,
   UARCH_POWER9_DD21,
@@ -84,6 +85,7 @@ void fill_uarch(struct uarch* arch, MICROARCH u) {
   FILL_UARCH(arch->uarch, UARCH_POWER7,      "POWER7",         45)
   FILL_UARCH(arch->uarch, UARCH_POWER7PLUS,  "POWER7+",        32)
   FILL_UARCH(arch->uarch, UARCH_POWER8,      "POWER8",         22)
+  FILL_UARCH(arch->uarch, UARCH_POWER8_DD21, "POWER8 (DD2.1)", 22)
   FILL_UARCH(arch->uarch, UARCH_POWER9,      "POWER9",         14)
   FILL_UARCH(arch->uarch, UARCH_POWER9_DD20, "POWER9 (DD2.0)", 14)
   FILL_UARCH(arch->uarch, UARCH_POWER9_DD21, "POWER9 (DD2.1)", 14)
@@ -100,7 +102,19 @@ void fill_uarch(struct uarch* arch, MICROARCH u) {
 }
 
 /*
- * PVR masks/values from arch/powerpc/kernel/cputable.c (Linux kernel)
+ * PVR masks/values from Linux kernel:
+ * - arch/powerpc/kernel/cputable.c            (kernel <= 6.0)
+ * - arch/powerpc/kernel/cpu_specs_book3s_64.h (kernel >= 6.1)
+ *
+ * In the kernel, there is a POWER8E identifier. In
+ * https://wiki.raptorcs.com/wiki/POWER8E it says it is
+ * actually DD2.1, while other POWER8 should be DD2.0.
+ * The last assumption does not seem to be correct according
+ * to https://openbenchmarking.org/s/POWER8NVL, which shows a
+ * POWER8NVL where kernel says it is DD1.0. We implement this
+ * to show only the uarch, not the revision, since it seems a bit
+ * redundant?
+ *
  * This list may be incorrect, incomplete or overly simplified,
  * specially in the case of 32 bit entries
  */
@@ -125,7 +139,7 @@ struct uarch* get_uarch_from_pvr(uint32_t pvr) {
   CHECK_UARCH(arch, pvr, 0xffffffff, 0x0f000006, UARCH_POWER10)
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x003f0000, UARCH_POWER7)
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x004A0000, UARCH_POWER7PLUS)
-  CHECK_UARCH(arch, pvr, 0xffff0000, 0x004b0000, UARCH_POWER8)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x004b0000, UARCH_POWER8_DD21)
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x004c0000, UARCH_POWER8)
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x004d0000, UARCH_POWER8)
   CHECK_UARCH(arch, pvr, 0xffffefff, 0x004e0200, UARCH_POWER9_DD20)
@@ -234,6 +248,7 @@ bool has_altivec(struct uarch* arch) {
     case UARCH_POWER7:
     case UARCH_POWER7PLUS:
     case UARCH_POWER8:
+    case UARCH_POWER8_DD21:
     case UARCH_POWER9:
     case UARCH_POWER9_DD20:
     case UARCH_POWER9_DD21:

src/ppc/udev.c

@@ -1,16 +1,19 @@
 #include <errno.h>
 
+#include "../common/udev.h"
 #include "../common/global.h"
 #include "udev.h"
 
 #define _PATH_TOPO_CORE_ID         "topology/core_id"
 #define _PATH_TOPO_PACKAGE_ID      "topology/physical_package_id"
+#define CPUINFO_FREQUENCY_STR      "clock\t\t: "
 
 bool fill_array_from_sys(int *core_ids, int total_cores, char* SYS_PATH) {
   int filelen;
   char* buf;
   char* end;
   char path[128];
+  memset(path, 0, 128);
 
   for(int i=0; i < total_cores; i++) {
     sprintf(path, "%s%s/cpu%d/%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, i, SYS_PATH);
@@ -36,5 +39,52 @@ bool fill_core_ids_from_sys(int *core_ids, int total_cores) {
 }
 
 bool fill_package_ids_from_sys(int* package_ids, int total_cores) {
-  return fill_array_from_sys(package_ids, total_cores, _PATH_TOPO_PACKAGE_ID);
+  bool status = fill_array_from_sys(package_ids, total_cores, _PATH_TOPO_PACKAGE_ID);
+  if(status) {
+    // fill_array_from_sys completed successfully, but we
+    // must to check the integrity of the package_ids array
+    for(int i=0; i < total_cores; i++) {
+      if(package_ids[i] == -1) {
+        printWarn("fill_package_ids_from_sys: package_ids[%d] = -1", i);
+        return false;
+      }
+      else if(package_ids[i] >= total_cores || package_ids[i] < 0) {
+        printBug("fill_package_ids_from_sys: package_ids[%d] = %d", i, package_ids[i]);
+        return false;
+      }
+    }
+
+    return true;
+  }
+  return false;
+}
+
+long get_frequency_from_cpuinfo(void) {
+  char* freq_str = get_field_from_cpuinfo(CPUINFO_FREQUENCY_STR);
+  if(freq_str == NULL) {
+    return UNKNOWN_DATA;
+  }
+  else {
+    // freq_str should be in the form XXXX.YYYYYYMHz
+    char* dot = strstr(freq_str, ".");
+    freq_str[dot-freq_str] = '\0';
+
+    char* end;
+    errno = 0;
+    long ret = strtol(freq_str, &end, 10);
+    if(errno != 0) {
+      printBug("strtol: %s", strerror(errno));
+      free(freq_str);
+      return UNKNOWN_DATA;
+    }
+
+    // We consider it an error if frequency is
+    // greater than 10 GHz or less than 100 MHz
+    if(ret > 10000 || ret <  100) {
+      printBug("Invalid data was read from file '%s': %ld\n", CPUINFO_FREQUENCY_STR, ret);
+      return UNKNOWN_DATA;
+    }
+
+    return ret;
+  }
 }

src/ppc/udev.h

@@ -4,8 +4,13 @@
 #include "../common/udev.h"
 #define _PATH_DT                  "/proc/device-tree/vpd/root-node-vpd@a000/enclosure@1e00/backplane@800/processor@1000"
 #define _PATH_DT_PART             "/part-number"
+#define _PATH_DT_IBM_PARTIT_NAME  "/device-tree/ibm,partition-name"
+#define _PATH_DT_HMC_MANAGED      "/device-tree/hmc-managed?"
+#define _PATH_DT_QEMU_WIDTH       "/device-tree/chosen/qemu,graphic-width"
 
 bool fill_core_ids_from_sys(int *core_ids, int total_cores);
 bool fill_package_ids_from_sys(int* package_ids, int total_cores);
+int get_num_sockets_package_cpus(struct topology* topo);
+long get_frequency_from_cpuinfo(void);
 
 #endif

src/riscv/riscv.c

@@ -9,6 +9,13 @@
 #include "uarch.h"
 #include "soc.h"
 
+#define SET_ISA_EXT_MAP(name, bit)          \
+  if(strncmp(multi_letter_extension, name,  \
+        multi_letter_extension_len) == 0) { \
+    ext->mask |= 1UL << bit;                \
+    maskset = true;                         \
+  }                                         \
+
 struct frequency* get_frequency_info(uint32_t core) {
   struct frequency* freq = emalloc(sizeof(struct frequency));
 
@@ -28,6 +35,61 @@ int64_t get_peak_performance(struct cpuInfo* cpu) {
   return flops;
 }
 
+// Returns the length of the multi-letter
+// extension, or -1 if an error occurs
+int parse_multi_letter_extension(struct extensions* ext, char* e) {
+  if(*e != '_') return -1;
+  char* multi_letter_extension_end = strstr(e+1, "_");
+  if(multi_letter_extension_end == NULL) {
+    // This is the last extension, find the end
+    // of the string
+    multi_letter_extension_end = e + strlen(e);
+  }
+
+  int multi_letter_extension_len = multi_letter_extension_end-(e+1);
+  bool maskset = false;
+  char* multi_letter_extension = emalloc(multi_letter_extension_len);
+  strncpy(multi_letter_extension, e+1, multi_letter_extension_len);
+  // This should be up-to-date with
+  // https://elixir.bootlin.com/linux/latest/source/arch/riscv/kernel/cpufeature.c
+  // which should represent the list of extensions available in real chips
+  SET_ISA_EXT_MAP("sscofpmf",    RISCV_ISA_EXT_SSCOFPMF)
+  SET_ISA_EXT_MAP("sstc",        RISCV_ISA_EXT_SSTC)
+  SET_ISA_EXT_MAP("svinval",     RISCV_ISA_EXT_SVINVAL)
+  SET_ISA_EXT_MAP("svpbmt",      RISCV_ISA_EXT_SVPBMT)
+  SET_ISA_EXT_MAP("zbb",         RISCV_ISA_EXT_ZBB)
+  SET_ISA_EXT_MAP("zicbom",      RISCV_ISA_EXT_ZICBOM)
+  SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE)
+  SET_ISA_EXT_MAP("svnapot",     RISCV_ISA_EXT_SVNAPOT)
+  SET_ISA_EXT_MAP("zicboz",      RISCV_ISA_EXT_ZICBOZ)
+  SET_ISA_EXT_MAP("smaia",       RISCV_ISA_EXT_SMAIA)
+  SET_ISA_EXT_MAP("ssaia",       RISCV_ISA_EXT_SSAIA)
+  SET_ISA_EXT_MAP("zba",         RISCV_ISA_EXT_ZBA)
+  SET_ISA_EXT_MAP("zbs",         RISCV_ISA_EXT_ZBS)
+  SET_ISA_EXT_MAP("zicntr",      RISCV_ISA_EXT_ZICNTR)
+  SET_ISA_EXT_MAP("zicsr",       RISCV_ISA_EXT_ZICSR)
+  SET_ISA_EXT_MAP("zifencei",    RISCV_ISA_EXT_ZIFENCEI)
+  SET_ISA_EXT_MAP("zihpm",       RISCV_ISA_EXT_ZIHPM)
+  if(!maskset) {
+    printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension);
+    return -1;
+  }
+
+  return multi_letter_extension_len;
+}
+
+bool valid_extension(char ext) {
+  bool found = false;
+  uint64_t idx = 0;
+
+  while(idx < sizeof(extension_list)/sizeof(extension_list[0]) && !found) {
+    found = (extension_list[idx].id == (ext - 'a'));
+    if(!found) idx++;
+  }
+
+  return found;
+}
+
 struct extensions* get_extensions_from_str(char* str) {
   struct extensions* ext = emalloc(sizeof(struct extensions));
   ext->mask = 0;
@@ -42,7 +104,7 @@ struct extensions* get_extensions_from_str(char* str) {
   memset(ext->str, 0, len);
   strncpy(ext->str, str, sizeof(char) * len);
 
-  // Code inspired in Linux kernel:
+  // Code inspired in Linux kernel (riscv_fill_hwcap):
   // https://elixir.bootlin.com/linux/v6.2.10/source/arch/riscv/kernel/cpufeature.c
   char* isa = str;
   if (!strncmp(isa, "rv32", 4))
@@ -55,9 +117,33 @@ struct extensions* get_extensions_from_str(char* str) {
   }
 
   for(char* e = isa; *e != '\0'; e++) {
+    if(*e == '_') {
+      // Multi-letter extension
+      int multi_letter_extension_len = parse_multi_letter_extension(ext, e);
+      if(multi_letter_extension_len == -1) {
+        return ext;
+      }
+      e += multi_letter_extension_len;
+    }
+    else {
+      // Single-letter extensions 's' and 'u' are invalid
+      // according to Linux kernel (arch/riscv/kernel/cpufeature.c:
+      // riscv_fill_hwcap). Optionally, we could opt for using
+      // hwcap instead of cpuinfo to avoid this
+      if (*e == 's' || *e == 'u') {
+        continue;
+      }
+      // Make sure that the extension is valid before
+      // adding it to the mask
+      if(valid_extension(*e)) {
         int n = *e - 'a';
         ext->mask |= 1UL << n;
       }
+      else {
+        printBug("get_extensions_from_str: Invalid extension: '%c'", *e);
+      }
+    }
+  }
 
   return ext;
 }
@@ -101,5 +187,20 @@ char* get_str_extensions(struct cpuInfo* cpu) {
 }
 
 void print_debug(struct cpuInfo* cpu) {
-  printf("Unimplemented!\n");
+  printf("- soc: ");
+  if(cpu->soc->raw_name == NULL) {
+    printf("NULL\n");
+  }
+  else {
+    printf("'%s'\n", cpu->soc->raw_name);
+  }
+
+  printf("- uarch: ");
+  char* arch_cpuinfo_str = get_arch_cpuinfo_str(cpu);
+  if(arch_cpuinfo_str == NULL) {
+    printf("NULL\n");
+  }
+  else {
+    printf("'%s'\n", arch_cpuinfo_str);
+  }
 }

src/riscv/riscv.h

@@ -8,6 +8,34 @@ struct extension {
   char* str;
 };
 
+#define RISCV_ISA_EXT_NAME_LEN_MAX 32
+#define RISCV_ISA_EXT_BASE         26
+
+// https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/asm/hwcap.h
+// This enum represent the logical ID for multi-letter RISC-V ISA extensions.
+// The logical ID should start from RISCV_ISA_EXT_BASE
+enum riscv_isa_ext_id {
+  RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
+  RISCV_ISA_EXT_SSTC,
+  RISCV_ISA_EXT_SVINVAL,
+  RISCV_ISA_EXT_SVPBMT,
+  RISCV_ISA_EXT_ZBB,
+  RISCV_ISA_EXT_ZICBOM,
+  RISCV_ISA_EXT_ZIHINTPAUSE,
+  RISCV_ISA_EXT_SVNAPOT,
+  RISCV_ISA_EXT_ZICBOZ,
+  RISCV_ISA_EXT_SMAIA,
+  RISCV_ISA_EXT_SSAIA,
+  RISCV_ISA_EXT_ZBA,
+  RISCV_ISA_EXT_ZBS,
+  RISCV_ISA_EXT_ZICNTR,
+  RISCV_ISA_EXT_ZICSR,
+  RISCV_ISA_EXT_ZIFENCEI,
+  RISCV_ISA_EXT_ZIHPM,
+  RISCV_ISA_EXT_ID_MAX
+};
+
+// https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface
 // https://en.wikichip.org/wiki/risc-v/standard_extensions
 // Included all except for G
 static const struct extension extension_list[] = {
@@ -26,7 +54,24 @@ static const struct extension extension_list[] = {
   { 'v' - 'a', "(V) Vector Operations" },
   { 'n' - 'a', "(N) User-Level Interrupts" },
   { 'h' - 'a', "(H) Hypervisor" },
-  { 's' - 'a', "(S) Supervisor-level Instructions" }
+  // multi-letter extensions
+  { RISCV_ISA_EXT_SSCOFPMF,    "(Sscofpmf) Count OverFlow and Privilege Mode Filtering" },
+  { RISCV_ISA_EXT_SSTC,        "(Sstc) S and VS level Time Compare" },
+  { RISCV_ISA_EXT_SVINVAL,     "(Svinval) Fast TLB Invalidation" },
+  { RISCV_ISA_EXT_SVPBMT,      "(Svpbmt) Page-based Memory Types" },
+  { RISCV_ISA_EXT_ZBB,         "(Zbb) Basic bit-manipulation" },
+  { RISCV_ISA_EXT_ZICBOM,      "(Zicbom) Cache Block Management Operations" },
+  { RISCV_ISA_EXT_ZIHINTPAUSE, "(Zihintpause) Pause Hint" },
+  { RISCV_ISA_EXT_SVNAPOT,     "(Svnapot) Naturally Aligned Power of Two Pages" },
+  { RISCV_ISA_EXT_ZICBOZ,      "(Zicboz) Cache Block Zero Operations" },
+  { RISCV_ISA_EXT_SMAIA,       "(Smaia) Advanced Interrupt Architecture" },
+  { RISCV_ISA_EXT_SSAIA,       "(Ssaia) Advanced Interrupt Architecture" },
+  { RISCV_ISA_EXT_ZBA,         "(Zba) Address Generation" },
+  { RISCV_ISA_EXT_ZBS,         "(Zbs) Single-bit Instructions" },
+  { RISCV_ISA_EXT_ZICNTR,      "(Zicntr) Base Counters and Timers" },
+  { RISCV_ISA_EXT_ZICSR,       "(Zicsr) Control and Status Register" },
+  { RISCV_ISA_EXT_ZIFENCEI,    "(Zifencei) Instruction-Fetch Fence" },
+  { RISCV_ISA_EXT_ZIHPM,       "(Zihpm) Hardware Performance Counters" }
 };
 
 struct cpuInfo* get_cpu_info(void);

src/riscv/soc.c

@@ -5,66 +5,6 @@
 
 #include <string.h>
 
-VENDOR get_soc_vendor(struct system_on_chip* soc) {
-  return soc->soc_vendor;
-}
-
-char* get_str_process(struct system_on_chip* soc) {
-  char* str;
-
-  if(soc->process == UNKNOWN) {
-    str = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
-    snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
-  }
-  else {
-    str = emalloc(sizeof(char) * 5);
-    memset(str, 0, sizeof(char) * 5);
-    snprintf(str, 5, "%dnm", soc->process);
-  }
-  return str;
-}
-
-char* get_soc_name(struct system_on_chip* soc) {
-  if(soc->soc_model == SOC_MODEL_UNKNOWN)
-    return soc->raw_name;
-  return soc->soc_name;
-}
-
-static char* soc_trademark_string[] = {
-  [SOC_VENDOR_SIFIVE] = "SiFive ",
-  [SOC_VENDOR_STARFIVE] = "StarFive ",
-  [SOC_VENDOR_ALLWINNER]  = "Allwinner "
-};
-
-void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process) {
-  soc->soc_model = soc_model;
-  soc->soc_vendor = get_soc_vendor_from_soc(soc_model);
-  soc->process = process;
-  int len = strlen(soc_name) + strlen(soc_trademark_string[soc->soc_vendor]) + 1;
-  soc->soc_name = emalloc(sizeof(char) * len);
-  memset(soc->soc_name, 0, sizeof(char) * len);
-  sprintf(soc->soc_name, "%s%s", soc_trademark_string[soc->soc_vendor], soc_name);
-}
-
-bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
-  int len1 = strlen(raw_name);
-  int len2 = strlen(expected_name);
-  int len = min(len1, len2);
-
-  if(strncmp(raw_name, expected_name, len) != 0) {
-    return false;
-  }
-  else {
-    fill_soc(soc, soc_name, soc_model, process);
-    return true;
-  }
-}
-
-#define SOC_START if (false) {}
-#define SOC_EQ(raw_name, expected_name, soc_name, soc_model, soc, process) \
-   else if (match_soc(soc, raw_name, expected_name, soc_name, soc_model, process)) return true;
-#define SOC_END else { return false; }
-
 bool match_sifive(char* soc_name, struct system_on_chip* soc) {
   char* tmp = soc_name;
 
@@ -92,6 +32,12 @@ bool match_allwinner(char* soc_name, struct system_on_chip* soc) {
   SOC_END
 }
 
+bool match_sipeed(char* soc_name, struct system_on_chip* soc) {
+  SOC_START
+  SOC_EQ(soc_name, "light", "Lichee Pi 4A", SOC_SIPEED_LICHEEPI4A, soc, 12) // https://github.com/Dr-Noob/cpufetch/issues/200, https://sipeed.com/licheepi4a
+  SOC_END
+}
+
 struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
   char* raw_name = soc->raw_name;
 
@@ -101,7 +47,10 @@ struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
   if(match_allwinner(raw_name, soc))
     return soc;
 
-  match_sifive(raw_name, soc);
+  if(match_sifive(raw_name, soc))
+    return soc;
+
+  match_sipeed(raw_name, soc);
   return soc;
 }
 

src/riscv/soc.h

@@ -1,29 +1,10 @@
-#ifndef __SOC__
-#define __SOC__
+#ifndef __SOC_RISCV__
+#define __SOC_RISCV__
 
+#include "../common/soc.h"
 #include "../common/cpu.h"
 #include <stdint.h>
 
-typedef int32_t SOC;
-
-enum {
-  SOC_VENDOR_UNKNOWN,
-  SOC_VENDOR_SIFIVE,
-  SOC_VENDOR_STARFIVE,
-  SOC_VENDOR_ALLWINNER
-};
-
-struct system_on_chip {
-  SOC soc_model;
-  VENDOR soc_vendor;
-  int32_t process;
-  char* soc_name;
-  char* raw_name;
-};
-
 struct system_on_chip* get_soc(void);
-char* get_soc_name(struct system_on_chip* soc);
-VENDOR get_soc_vendor(struct system_on_chip* soc);
-char* get_str_process(struct system_on_chip* soc);
 
 #endif

src/riscv/socs.h

@@ -11,6 +11,8 @@ enum {
   SOC_STARFIVE_VF2,
   // ALLWINNER
   SOC_ALLWINNER_D1H,
+  // SIPEED
+  SOC_SIPEED_LICHEEPI4A,
   // UNKNOWN
   SOC_MODEL_UNKNOWN
 };
@@ -19,6 +21,7 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
   if(soc >= SOC_SIFIVE_U740 && soc <= SOC_SIFIVE_U740) return SOC_VENDOR_SIFIVE;
   if(soc >= SOC_STARFIVE_VF2 && soc <= SOC_STARFIVE_VF2) return SOC_VENDOR_STARFIVE;
   if(soc >= SOC_ALLWINNER_D1H && soc <= SOC_ALLWINNER_D1H) return SOC_VENDOR_ALLWINNER;
+  if(soc >= SOC_SIPEED_LICHEEPI4A && soc <= SOC_SIPEED_LICHEEPI4A) return SOC_VENDOR_SIPEED;
   return SOC_VENDOR_UNKNOWN;
 }
 

src/riscv/uarch.c

@@ -11,6 +11,7 @@ typedef uint32_t MICROARCH;
 struct uarch {
   MICROARCH uarch;
   char* uarch_str;
+  char* cpuinfo_str;
 };
 
 enum {
@@ -40,6 +41,7 @@ void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u,
 // T-Head: https://www.t-head.cn/product/c906
 struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu) {
   struct uarch* arch = emalloc(sizeof(struct uarch));
+  arch->cpuinfo_str = cpuinfo_str;
   if(cpuinfo_str == NULL) {
     printWarn("get_uarch_from_cpuinfo: Unable to detect microarchitecture, cpuinfo_str is NULL");
     fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN);
@@ -72,6 +74,10 @@ char* get_str_uarch(struct cpuInfo* cpu) {
   return cpu->arch->uarch_str;
 }
 
+char* get_arch_cpuinfo_str(struct cpuInfo* cpu) {
+  return cpu->arch->cpuinfo_str;
+}
+
 void free_uarch_struct(struct uarch* arch) {
   free(arch->uarch_str);
   free(arch);

src/riscv/uarch.h

@@ -6,6 +6,7 @@
 
 struct uarch;
 
+char* get_arch_cpuinfo_str(struct cpuInfo* cpu);
 char* get_str_uarch(struct cpuInfo* cpu);
 void free_uarch_struct(struct uarch* arch);
 struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu);

src/riscv/udev.c

@@ -4,7 +4,6 @@
 #include "../common/global.h"
 #include "udev.h"
 
-#define _PATH_CPUINFO          "/proc/cpuinfo"
 #define _PATH_DEVTREE          "/proc/device-tree/compatible"
 #define CPUINFO_UARCH_STR      "uarch\t\t: "
 #define CPUINFO_EXTENSIONS_STR "isa\t\t: "
@@ -86,7 +85,7 @@ char* get_uarch_from_cpuinfo(void) {
   return parse_cpuinfo_field(CPUINFO_UARCH_STR);
 }
 
-char* get_extensions_from_cpuinfo() {
+char* get_extensions_from_cpuinfo(void) {
   return parse_cpuinfo_field(CPUINFO_EXTENSIONS_STR);
 }
 

src/x86/cpuid.c

@@ -30,6 +30,9 @@ static const char *hv_vendors_string[] = {
   [HV_VENDOR_VMWARE]    = "VMwareVMware",
   [HV_VENDOR_XEN]       = "XenVMMXenVMM",
   [HV_VENDOR_PARALLELS] = "lrpepyh vr",
+  [HV_VENDOR_PHYP]      = NULL,
+  [HV_VENDOR_BHYVE]     = "bhyve bhyve ",
+  [HV_VENDOR_APPLEVZ]   = "Apple VZ"
 };
 
 static char *hv_vendors_name[] = {
@@ -39,11 +42,12 @@ static char *hv_vendors_name[] = {
   [HV_VENDOR_VMWARE]    = "VMware",
   [HV_VENDOR_XEN]       = "Xen",
   [HV_VENDOR_PARALLELS] = "Parallels",
+  [HV_VENDOR_PHYP]      = "pHyp",
+  [HV_VENDOR_BHYVE]     = "bhyve",
+  [HV_VENDOR_APPLEVZ]   = "Apple VZ",
   [HV_VENDOR_INVALID]   = STRING_UNKNOWN
 };
 
-#define HYPERVISOR_NAME_MAX_LENGTH 17
-
 #define MASK 0xFF
 
 /*
@@ -223,9 +227,10 @@ int64_t get_peak_performance(struct cpuInfo* cpu, bool accurate_pp) {
     if(feat->FMA3 || feat->FMA4)
       flops = flops*2;
 
-    // Ice Lake has AVX512, but it has 1 VPU for AVX512, while
-    // it has 2 for AVX2. If this is a Ice Lake CPU, we are computing
-    // the peak performance supposing AVX2, not AVX512
+    // NOTE:
+    // Some CPUs (Ice Lake, Zen 4) have AVX512, but they have only
+    // 1 VPU for AVX512, while they have 2 for AVX2. In such cases,
+    // we are computing the peak performance supposing AVX2, not AVX512
     if(feat->AVX512 && vpus_are_AVX512(ptr))
       flops = flops*16;
     else if(feat->AVX || feat->AVX2)
@@ -260,6 +265,11 @@ struct hypervisor* get_hp_info(bool hv_present) {
 
   cpuid(&eax, &ebx, &ecx, &edx);
 
+  if(ebx == 0x0 && ecx == 0x0 && edx == 0x0) {
+    hv->hv_vendor = HV_VENDOR_INVALID;
+    printWarn("Hypervisor vendor is empty");
+  }
+  else {
     char name[13];
     memset(name, 0, 13);
     get_name_cpuid(name, ebx, ecx, edx);
@@ -268,7 +278,7 @@ struct hypervisor* get_hp_info(bool hv_present) {
     uint8_t len = sizeof(hv_vendors_string) / sizeof(hv_vendors_string[0]);
 
     for(uint8_t v=0; v < len && !found; v++) {
-    if(strcmp(hv_vendors_string[v], name) == 0) {
+      if(hv_vendors_string[v] != NULL && strcmp(hv_vendors_string[v], name) == 0) {
         hv->hv_vendor = v;
         found = true;
       }
@@ -276,7 +286,8 @@ struct hypervisor* get_hp_info(bool hv_present) {
 
     if(!found) {
       hv->hv_vendor = HV_VENDOR_INVALID;
-    printWarn("Unknown hypervisor vendor: %s", name);
+      printBug("Unknown hypervisor vendor: '%s'", name);
+    }
   }
 
   hv->hv_name = hv_vendors_name[hv->hv_vendor];
@@ -625,6 +636,7 @@ bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
   return true;
 }
 
+#ifdef __linux__
 void get_topology_from_udev(struct topology* topo) {
   // TODO: To be improved in the future
   topo->total_cores = get_ncores_from_cpuinfo();
@@ -634,6 +646,7 @@ void get_topology_from_udev(struct topology* topo) {
   topo->smt_supported = 1;
   topo->sockets = 1;
 }
+#endif
 
 // Main reference: https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html
 // Very interesting resource: https://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
@@ -1084,12 +1097,29 @@ void print_debug(struct cpuInfo* cpu) {
   free_cpuinfo_struct(cpu);
 }
 
-// TODO: Query HV and Xeon Phi levels
+void print_raw_level(uint32_t reg) {
+  uint32_t eax = reg;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+
+  cpuid(&eax, &ebx, &ecx, &edx);
+
+  printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
+}
+
+void print_raw_sublevel(uint32_t reg, uint32_t reg2) {
+  uint32_t eax = reg;
+  uint32_t ebx = 0;
+  uint32_t ecx = reg2;
+  uint32_t edx = 0;
+
+  cpuid(&eax, &ebx, &ecx, &edx);
+
+  printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
+}
+
 void print_raw(struct cpuInfo* cpu) {
-  uint32_t eax;
-  uint32_t ebx;
-  uint32_t ecx;
-  uint32_t edx;
   printf("%s\n\n", cpu->cpu_name);
   printf("  CPUID leaf sub   EAX        EBX        ECX        EDX       \n");
   printf("--------------------------------------------------------------\n");
@@ -1104,66 +1134,40 @@ void print_raw(struct cpuInfo* cpu) {
 
     printf("CPU %d:\n", c);
 
+    // Standard levels
     for(uint32_t reg=0x00000000; reg <= cpu->maxLevels; reg++) {
       if(reg == 0x00000004) {
         for(uint32_t reg2=0x00000000; reg2 < cpu->cach->max_cache_level; reg2++) {
-          eax = reg;
-          ebx = 0;
-          ecx = reg2;
-          edx = 0;
-
-          cpuid(&eax, &ebx, &ecx, &edx);
-
-          printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
+          print_raw_sublevel(reg, reg2);
         }
       }
       else if(reg == 0x0000000B) {
         for(uint32_t reg2=0x00000000; reg2 < cpu->topo->smt_supported; reg2++) {
-          eax = reg;
-          ebx = 0;
-          ecx = reg2;
-          edx = 0;
-
-          cpuid(&eax, &ebx, &ecx, &edx);
-
-          printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
+          print_raw_sublevel(reg, reg2);
         }
       }
       else {
-        eax = reg;
-        ebx = 0;
-        ecx = 0;
-        edx = 0;
-
-        cpuid(&eax, &ebx, &ecx, &edx);
-
-        printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
+        print_raw_level(reg);
       }
     }
+
+    // Hypervisor levels
+    for(uint32_t reg=0x40000000; reg <= 0x40000006; reg++) {
+      print_raw_level(reg);
+    }
+
+    // Extended levels
     for(uint32_t reg=0x80000000; reg <= cpu->maxExtendedLevels; reg++) {
       if(reg == 0x8000001D) {
         for(uint32_t reg2=0x00000000; reg2 < cpu->cach->max_cache_level; reg2++) {
-          eax = reg;
-          ebx = 0;
-          ecx = reg2;
-          edx = 0;
-
-          cpuid(&eax, &ebx, &ecx, &edx);
-
-          printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
+          print_raw_sublevel(reg, reg2);
         }
       }
       else {
-        eax = reg;
-        ebx = 0;
-        ecx = 0;
-        edx = 0;
-
-        cpuid(&eax, &ebx, &ecx, &edx);
-
-        printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
+        print_raw_level(reg);
       }
     }
+
   }
 }
 

src/x86/uarch.c

@@ -112,7 +112,8 @@ enum {
   UARCH_ZEN2,
   UARCH_ZEN3,
   UARCH_ZEN3_PLUS,
-  UARCH_ZEN4
+  UARCH_ZEN4,
+  UARCH_ZEN4C
 };
 
 struct uarch {
@@ -124,7 +125,9 @@ struct uarch {
 #define UARCH_START if (false) {}
 #define CHECK_UARCH(arch, ef_, f_, em_, m_, s_, str, uarch, process) \
    else if (ef_ == ef && f_ == f && (em_ == NA || em_ == em) && (m_ == NA || m_ == m) && (s_ == NA || s_ == s)) fill_uarch(arch, str, uarch, process);
-#define UARCH_END else { printBug("Unknown microarchitecture detected: M=0x%.8X EM=0x%.8X F=0x%.8X EF=0x%.8X S=0x%.8X", m, em, f, ef, s); fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, 0); }
+#define UARCH_END else { printErr("Unknown microarchitecture detected: M=0x%X EM=0x%X F=0x%X EF=0x%X S=0x%X", m, em, f, ef, s); \
+fprintf(stderr, "Please see https://github.com/Dr-Noob/cpufetch#61-unknown-microarchitecture-error to know how to report this error\n"); \
+fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK); }
 
 void fill_uarch(struct uarch* arch, char* str, MICROARCH u, uint32_t process) {
   arch->uarch_str = emalloc(sizeof(char) * (strlen(str)+1));
@@ -245,6 +248,9 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 0,  6, 10,  6, NA, "Comet Lake",      UARCH_COMET_LAKE,       14) // instlatx64.atw.hu (i7-10710U)
   CHECK_UARCH(arch, 0,  6, 10,  7, NA, "Rocket Lake",     UARCH_ROCKET_LAKE,      14) // instlatx64.atw.hu (i7-11700K)
   CHECK_UARCH(arch, 0,  6, 11,  7, NA, "Raptor Lake",     UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i5-13600K)
+  CHECK_UARCH(arch, 0,  6, 11, 10, NA, "Raptor Lake",     UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i7-1370P)
+  CHECK_UARCH(arch, 0,  6, 11, 14, NA, "Alder Lake",      UARCH_ALDER_LAKE,       10) // instlatx64.atw.hu (Alder Lake-N)
+  CHECK_UARCH(arch, 0,  6, 11, 15, NA, "Raptor Lake",     UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i5-13500)
   CHECK_UARCH(arch, 0, 11,  0,  0, NA, "Knights Ferry",   UARCH_KNIGHTS_FERRY,    45) // found only on en.wikichip.org
   CHECK_UARCH(arch, 0, 11,  0,  1, NA, "Knights Corner",  UARCH_KNIGHTS_CORNER,   22)
   CHECK_UARCH(arch, 0, 15,  0,  0, NA, "Willamette",      UARCH_WILLAMETTE,      180)
@@ -257,7 +263,6 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 1, 15,  0,  1, NA, "Itanium2",        UARCH_ITANIUM2,        130)
   CHECK_UARCH(arch, 1, 15,  0,  2, NA, "Itanium2",        UARCH_ITANIUM2,        130)
   UARCH_END
-
   return arch;
 }
 
@@ -348,6 +353,7 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
   CHECK_UARCH(arch,  6, 15,  6,  5, NA, "Excavator",   UARCH_EXCAVATOR,   28) // undocumented, but sample from Alexandros Couloumbis
   CHECK_UARCH(arch,  6, 15,  7,  0, NA, "Excavator",   UARCH_EXCAVATOR,   28)
   CHECK_UARCH(arch,  7, 15,  0,  0, NA, "Jaguar",      UARCH_JAGUAR,      28)
+  CHECK_UARCH(arch,  7, 15,  1, NA, NA, "Jaguar",      UARCH_JAGUAR,      14) // instlatx64 (PS4) Normal PS4 is 28nm, Slim and Pro are 16nm
   CHECK_UARCH(arch,  7, 15,  2,  6, NA, "Jaguar",      UARCH_JAGUAR,      28) // AMD Cato (Xbox One?)
   CHECK_UARCH(arch,  7, 15,  3,  0, NA, "Puma 2014",   UARCH_PUMA_2014,   28)
   CHECK_UARCH(arch,  8, 15,  0,  0, NA, "Zen",         UARCH_ZEN,         14) // instlatx64 engr sample
@@ -362,12 +368,23 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
   CHECK_UARCH(arch,  8, 15,  6,  0, NA, "Zen 2",       UARCH_ZEN2,         7) // undocumented, geekbench.com example
   CHECK_UARCH(arch,  8, 15,  6,  8, NA, "Zen 2",       UARCH_ZEN2,         7) // found on instlatx64
   CHECK_UARCH(arch,  8, 15,  7,  1, NA, "Zen 2",       UARCH_ZEN2,         7) // samples from Steven Noonan and instlatx64
+  CHECK_UARCH(arch,  8, 15,  8,  4, NA, "Zen 2",       UARCH_ZEN2,         7) // instlatx64 (Xbox Series X?)
   CHECK_UARCH(arch,  8, 15,  9,  0,  2, "Zen 2",       UARCH_ZEN2,         7) // Steam Deck (instlatx64)
+  CHECK_UARCH(arch,  8, 15,  10, 0, NA, "Zen 2",       UARCH_ZEN2,         6) // instlatx64
   CHECK_UARCH(arch, 10, 15,  0,  1, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  0,  8, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  1,  1, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  1,  8, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64
   CHECK_UARCH(arch, 10, 15,  2,  1, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  3, NA, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
   CHECK_UARCH(arch, 10, 15,  4,  4, NA, "Zen 3+",      UARCH_ZEN3_PLUS,    6) // instlatx64 (they say it is Zen3...)
   CHECK_UARCH(arch, 10, 15,  5,  0, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
   CHECK_UARCH(arch, 10, 15,  6,  1,  2, "Zen 4",       UARCH_ZEN4,         5) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  7,  4,  1, "Zen 4",       UARCH_ZEN4,         4) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  7,  8,  0, "Zen 4",       UARCH_ZEN4,         4) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  8, NA, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64 (AMD MI300C)
+  CHECK_UARCH(arch, 10, 15,  9, NA, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64 (AMD MI300A)
+  CHECK_UARCH(arch, 10, 15, 10, NA, NA, "Zen 4c",      UARCH_ZEN4C,        5) // instlatx64
   UARCH_END
 
   return arch;
@@ -413,7 +430,10 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
 }
 
 bool vpus_are_AVX512(struct cpuInfo* cpu) {
-  return cpu->arch->uarch != UARCH_ICE_LAKE && cpu->arch->uarch != UARCH_TIGER_LAKE;
+  return cpu->arch->uarch != UARCH_ICE_LAKE &&
+         cpu->arch->uarch != UARCH_TIGER_LAKE &&
+         cpu->arch->uarch != UARCH_ZEN4 &&
+         cpu->arch->uarch != UARCH_ZEN4C;
 }
 
 bool is_knights_landing(struct cpuInfo* cpu) {
@@ -449,6 +469,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
       case UARCH_ZEN3:
       case UARCH_ZEN3_PLUS:
       case UARCH_ZEN4:
+      case UARCH_ZEN4C:
         return 2;
       default:
         return 1;