[v0.94][ARM] Do not print cache sizes

[v0.94] When SoC string is not matched against any SoC is not considered a bug anymore
[v0.94] Add reminder in Qualcomm SoCs, that need more time to work properly
2026-03-25 07:50:40 +01:00 · 2020-12-08 18:33:42 +01:00 · 2020-12-08 18:04:13 +01:00 · 2020-12-08 18:01:26 +01:00 · 2020-12-08 15:56:13 +01:00 · 2020-12-05 11:56:40 +01:00
53 changed files with 5512 additions and 1500 deletions
--- a/44
+++ b/44
@@ -1,18 +1,37 @@
 CXX=gcc

-CXXFLAGS=-Wall -Wextra -Werror -fstack-protector-all -pedantic -Wno-unused -std=c99
-SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-overflow=5 -Wformat=2
+CXXFLAGS=-Wall -Wextra -Werror -pedantic -fstack-protector-all -pedantic -std=c99
+SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith

-SRC_DIR=src/
-SOURCE=$(SRC_DIR)main.c $(SRC_DIR)standart.c $(SRC_DIR)extended.c $(SRC_DIR)cpuid.c $(SRC_DIR)printer.c $(SRC_DIR)args.c $(SRC_DIR)global.c
-HEADERS=$(SRC_DIR)standart.h $(SRC_DIR)extended.h  $(SRC_DIR)cpuid.h $(SRC_DIR)printer.h $(SRC_DIR)ascii.h $(SRC_DIR)args.h $(SRC_DIR)global.h
+SRC_COMMON=src/common/
+
+COMMON_SRC = $(SRC_COMMON)main.c $(SRC_COMMON)cpu.c $(SRC_COMMON)udev.c $(SRC_COMMON)printer.c $(SRC_COMMON)args.c $(SRC_COMMON)global.c
+COMMON_HDR = $(SRC_COMMON)ascii.h $(SRC_COMMON)cpu.h $(SRC_COMMON)udev.h $(SRC_COMMON)printer.h $(SRC_COMMON)args.h $(SRC_COMMON)global.h

 ifneq ($(OS),Windows_NT)
-	SOURCE += $(SRC_DIR)udev.c
-	HEADERS += $(SRC_DIR)udev.h
-endif
+	arch := $(shell uname -m)
+	ifeq ($(arch), x86_64)
+		SRC_DIR=src/x86/
+		SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
+		HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h 
+		CXXFLAGS += -DARCH_X86
+	else
+		SRC_DIR=src/arm/
+		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
+		HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h  $(SRC_DIR)soc.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
+		CXXFLAGS += -DARCH_ARM -Wno-unused-parameter
+	endif

-OUTPUT=cpufetch
+	OUTPUT=cpufetch
+else
+	# Assume x86_64
+	SRC_DIR=src/x86/
+	SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
+	HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h 
+	CXXFLAGS += -DARCH_X86
+	SANITY_FLAGS += -Wno-pedantic-ms-format
+	OUTPUT=cpufetch.exe
+endif

 all: $(OUTPUT)

@@ -25,8 +44,13 @@ release: $(OUTPUT)
 $(OUTPUT): Makefile $(SOURCE) $(HEADERS)
 	$(CXX) $(CXXFLAGS) $(SANITY_FLAGS) $(SOURCE) -o $(OUTPUT)

-run:
+run: $(OUTPUT)
 	./$(OUTPUT)

 clean:
 	@rm $(OUTPUT)
+
+install: $(OUTPUT)
+	install -Dm755 "cpufetch"   "/usr/bin/cpufetch"
+	install -Dm644 "LICENSE"    "/usr/share/licenses/cpufetch-git/LICENSE"
+	install -Dm644 "cpufetch.8" "/usr/share/man/man8/cpufetch.8.gz"
--- a/README.md
+++ b/README.md
@@ -1,14 +1,41 @@
 # cpufetch

-Prints a fancy summary of the CPU with some advanced information
+Simplistic yet fancy CPU architecture fetching tool
+![cpu1](pictures/i9.png)

 ### Platforms
-This tool works on both 64 only and under Linux because of its [implementation details](#implementation). AMD support is not guaranteed so information may not be correct
+cpufetch currently supports x86_64 CPUs (both Intel and AMD) and ARM (experimental support)
+
+| Platform  | Intel                     | AMD                      | ARM                      | Notes             |
+|:---------:|:-------------------------:|:------------------------:|:------------------------:|:-----------------:|
+| Linux     | :heavy_check_mark:        | :heavy_check_mark:       | :heavy_check_mark:       | Prefered platform. <br> Experimental ARM support |
+| Windows   | :heavy_check_mark:        | :heavy_check_mark:       | :x:                      | Some information may be missing. <br> Colors will be used if supported |
+| Android   | :heavy_exclamation_mark:  | :heavy_exclamation_mark: | :heavy_check_mark:       | Experimental ARM support |
+| macOS     | :heavy_exclamation_mark:  | :heavy_exclamation_mark: | :heavy_exclamation_mark: | Untested |
+
+| Emoji                   | Meaning       |
+|:-----------------------:|:-------------:|
+|:heavy_check_mark:       | Supported     |
+|:x:                      | Not Supported |
+|:heavy_exclamation_mark: | Unested       |
+
+
+

 ### Usage and installation
+#### Linux
+There is a cpufetch package available in Arch Linux ([cpufetch-git](https://aur.archlinux.org/packages/cpufetch-git)).

-Just clone the repo and use `make` to compile it
+If you are in other distro, you can build `cpufetch` from source (see below)

+#### Windows
+In the [releases](https://github.com/Dr-Noob/cpufetch/releases) section you will find some cpufetch executables compiled for Windows. Just download and run it from Windows CMD.
+
+#### Android
+You need to build `cpufetch` from source (see below).
+
+### Building from source
+#### Linux and Windows
 ```
 git clone https://github.com/Dr-Noob/cpufetch
 cd cpufetch
@@ -16,38 +43,43 @@ make
 ./cpufetch
 ```

-### Example
+#### Android
+I recommend using `termux` terminal emulator. Once you installed it, run the following commands:

-This is the output of `cpufetch` in a i7-4790K
+```
+pkg install -y git make clang
+git clone https://github.com/Dr-Noob/cpufetch
+cd cpufetch
+make
+./cpufetch
+```

-![Example](/preview.png)
+### Examples

-### Output
+Here are more examples of how `cpufetch` looks on different CPUs.

-Output is detailed as follows:
+![cpu2](pictures/epyc.png)

-| Field      | Description             | Possible Values  |
-|:----------:|:-----------------------:|:-----------------:|
-| Name       | Name of the CPU   | Any valid CPU name |
-| Frequency  | Max frequency of the CPU(in GHz) | X.XX(GHz or MHz)
-| N.Cores    | Number of cores the CPU has. If CPU supports `Hyperthreading` or similar, this will show cores and threads separately | X(cores)X(threads)
-| AVX        | Type of AVX supported by the CPU or None. AVX instructions allows the CPU to vectorize the code with a witdh of 256 bits in single precision(or 512bits if AVX512 is supported) | AVX,AVX2,AVX512,None
-| SSE        | Same as AVX, but SSE family are 128bits witdh | SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4_1, SSE4_2,None |
-| FMA        | Does this CPU support FMA(Fused Multiply Add)?This instruction allows the CPU to multiply and add a value on the same clock cycle | FMA3,FMA4,None |
-| AES        | Does this CPU support AES? This instruction is allows the CPU to make AES cypher efficiently | Yes or No |
-| SHA        | Does this CPU support SHA? This instruction is allows the CPU to make SHA hashing efficiently | Yes or No |
-| L1 Size    | Size(in bytes) of the L1 cache, separated in data and instructions | XXB(Data)XXB(instructions) |
-| L2 Size    | Size(in bytes) of the L2 cache(both are unified) | XXXKB or None |
-| L3 Size    | Same as L3 | XXXXKB or None |
-| Peak FLOPS | Max FLOPS(Floating Point Operation Per Second) this CPU could theoretical achieve. This is calculated by: `N.Cores*Freq*2(Because 2 functional units)*2(If has FMA)*VectorWidth` | XXX.XX (G/T)FLOPs |
+![cpu3](pictures/cascade_lake.png)

-`cpufetch` also prints a simple ascii art of the manufacturer logo.
+### Colors and style
+By default, `cpufetch` will print the CPU art with the system colorscheme. However, you can always set a custom color scheme, either
+specifying Intel or AMD, or specifying the colors in RGB format:
+
+```
+./cpufetch --color intel (default color for Intel)
+./cpufetch --color amd (default color for AND)
+./cpufetch --color 239,90,45:210,200,200:100,200,45:0,200,200 (example)
+```
+
+In the case of setting the colors using RGB, 4 colors must be given in with the format: ``[R,G,B:R,G,B:R,G,B:R,G,B]``. These colors correspond to CPU art color (2 colors) and for the text colors (following 2). Thus, you can customize all the colors.

 ### Implementation

-`cpufetch` makes use of two techniques to fetch data:
-* __cpuid__: CPU name, number of threads per core and instructions features are fetched via _cpuid_. See [this](http://www.sandpile.org/x86/cpuid.htm) and [Intel  Processor Identification and the CPUID Instruction](https://www.scss.tcd.ie/~jones/CS4021/processor-identification-cpuid-instruction-note.pdf) for more information.
-* __udev__: Cache and frequency are fetched via _udev_, by looking at specific files from `/sys/devices/system/cpu`
+`cpufetch` fetches all of the information using the `CPUID` x86 instruction. There are, however, some cases where the CPU does not support fetching some needed information. In this case, `cpufetch` will use `/sys/devices/system/cpu` in Linux as a fallback. If `cpufetch` is running on Windows and `CPUID` does not give all the data, `cpufetch` won't be able to show it. [I hope this can be fixed in the future](https://github.com/Dr-Noob/cpufetch/issues/30)

 ### Bugs or improvements
-Feel free to open a issue on the repo to report a issue or propose any improvement in the tool
+There are many open issues in github (see [issues](https://github.com/Dr-Noob/cpufetch/issues)). Feel free to open a new one report a issue or propose any improvement in `cpufetch`
+
+### Testers
+I would like to thank [Gonzalocl](https://github.com/Gonzalocl) and [OdnetninI](https://github.com/OdnetninI) for their help, running `cpufeth` in many different CPUs they have access to, which makes it easier to debug and check the correctness of `cpufetch`.
--- a/ascii/amdASCII
+++ b/ascii/amdASCII
@@ -1,21 +0,0 @@
-
-
-
-
-
-
-     @@@@      @@@%      @@@.  @@@@@@@@(      .############
-    @@@@@@     @@@@@   %@@@@.  @@@    @@@@      .((((((####
-   @@@  @@@    @@@/@@@@@@&@@.  @@@     %@@%     #      ####
-  @@@,  (@@#   @@@  @@@/ @@@.  @@@     .@@@   ###      ####
- ,@@@@@@@@@@,  @@@       @@@.  @@@     @@@   ####      ####
- @@@      @@@  @@@       @@@.  @@@@@@@@@&    #######/   .##
-
-
-
-
-
-
-
-
- 
--- a/ascii/intelASCII
+++ b/ascii/intelASCII
@@ -1,19 +0,0 @@
-                              ################
-                      #######                #######
-                 ####                              ####
-             ###                                     ####
-        ###                                             ###
-        ###                                  ###        ###
-     #                    ###                ###        ###
-   ##   ###   #########   ######   ######    ###        ###
-  ##    ###   ###    ###  ###    ####  ####  ###        ###
- ##     ###   ###    ###  ###    ###    ###  ###       ###
-##      ###   ###    ###  ###    ##########  ###     ####
-##      ###   ###    ###  ###    ###         ###   #####
-##       ##   ###    ###   #####  #########   ##  ###
-###
-(###
- ####                                        ####
-   #####                               ##########
-     ##########               ################
-         ###############################
--- a/cpufetch.8
+++ b/cpufetch.8
@@ -1,33 +1,57 @@
-.TH man 8 "22 Jun 2018" "0.32" "cpufetch man page"
+.TH man 8 "1 Sep 2020" "0.7" "cpufetch man page"
 .SH NAME
-cpufetch \- Prints a fancy summary of the CPU with some advanced information
+cpufetch \- Simplistic yet fancy CPU architecture fetching tool
 .SH SYNOPSIS
-cpufetch [--help] [--style STYLE]
+cpufetch [--version] [--help] [--levels] [--style fancy|retro|legacy] [--color intel|amd|'R,G,B:R,G,B:R,G,B:R,G,B']
 .SH DESCRIPTION
-cpufetch will print CPU information, for which will query cpuid instructions and udev directories on Linux. It should display:
+cpufetch will print CPU information, for which will query CPUID instructions and udev directories on Linux as a fallback method. Some of this features are:
 .IP \[bu] 2
 Name
 .IP \[bu]
 Frequency
 .IP \[bu]
-Number of cores(Physical and Logical)
+Number of cores (Physical and Logical)
 .IP \[bu]
-AVX,SSE,FMA,AES and SHA support
+Cache sizes
 .IP \[bu]
-L1,L2 and L3 size
-.IP \[bu]
-Theoretical peak flops
+Theoretical peak performance in floating point operations per second (FLOP/s)
 .SH OPTIONS
 .TP
+\fB\-\-style\fR \f[I][intel|amd|R,G,B:R,G,B:R,G,B:R,G,B]\f[]
+Set the color scheme. By default, cpufetch uses the system color scheme. This option lets the user use different colors to print the CPU art:
+.IP \[bu]
+\fB"intel"\fR: Use intel color scheme
+.IP \[bu]
+\fB"amd"\fR: Use amd color scheme
+.IP \[bu]
+\fBcustom\fR: If color do not match "intel" or "amd", a custom scheme can be specified: 4 colors must be given in RGB with the format: R,G,B:R,G,B:... 
+             These colors correspond to CPU art color (2 colors) and for the text colors (following 2) 
+.TP
+\fB\-\-style\fR \f[I]STYLE\f[]
+Specify the style of ascii logo:
+.IP \[bu] 
+\fB"fancy"\fR:  Default style
+.IP \[bu]
+\fB"retro"\fR:  Old cpufetch style
+.IP \[bu]
+\fB"legacy"\fR: Fallback style for terminals that does not support colors
+.TP
+\fB\-\-levels\fR
+Prints CPUID levels and CPU name
+.TP
+\fB\-\-verbose\fR
+Prints extra information (if available) about how cpufetch tried fetching information
+.TP
 \fB\-\-help\fR
 Prints help
 .TP
 \fB\-\-version\fR
 Prints cpufetch version
-.TP
-\fB\-\-style\fR
-Specify the color style of ascii logo
 .SH BUGS
-No known bugs. AMD CPUs may not be fully supported
+Bugs should be posted on: https://github.com/Dr-Noob/cpufetch/issues
+.SH NOTES
+Peak performance information is NOT accurate. cpufetch computes peak performance using the max   
+frequency. However, to properly compute peak performance, you need to know the frequency of the  
+CPU running AVX code, which is not be fetched by cpufetch since it depends on each specific CPU.
 .SH AUTHOR
 Dr-Noob (https://github.com/Dr-Noob)
--- a/doc/DOCUMENTATION_ARM.md
+++ b/doc/DOCUMENTATION_ARM.md
@@ -0,0 +1,2 @@
+### 2. Why ARM cpufetch works on Linux based systems?
+TODO
--- a/doc/DOCUMENTATION_X86.md
+++ b/doc/DOCUMENTATION_X86.md
@@ -0,0 +1,121 @@
+### 2. Why differences between Intel and AMD?
+There are many different CPUID leaves (see [Useful documentation](#useful-documentation)). However, there are cases where a given leaf does the same thing in Intel and AMD, but the majority of them, they don't. For example, leaf 0x4 gives you the caches information, but in
+AMD is a reserved (invalid) leaf! In the case of AMD, is more common to fetch information using extended levels than using the standard levels (the other way around with Intel).
+
+### 3. How to get the frequency?
+__Involved code: get_frequency_info (cpuid.c)__
+
+We use CPUID leaf 0x16.
+
+If the CPU supports it, we are done. If not:
+- Linux: cpufetch will try to obtain this information using `/sys` filesystem in Linux. I think that, in this case, Linux knows the frequency using MSRs, so at the user level you can't know it, but I will look at the kernel source code to check it.
+- Windows: We are dead. cpufetch can't fetch CPU frequency. This means that peak performance can't be computed because the frequency is needed to compute it.
+
+### 4. How to get cache sizes?
+__Involved code: get_cache_info (cpuid.c)__
+
+- Intel: We use CPUID leaf 0x4
+- AMD: We use extended CPUID leaf 0x1D
+
+If CPU does not support it, we are dead: cpufetch can't get this information. If CPU does, we can fetch it, and 0x4 in Intel behaves the same way as 0x1D in AMD.
+
+### 5. How to get CPU microarchitecture?
+__Involved code: get_cpu_uarch (cpuid.c), get_uarch_from_cpuid (uarch.c)__
+
+We use CPUID leaf 0x1. From there, we get:
+- Model
+- Extended Model
+- Family
+- Extended Family
+- Stepping
+
+Knowing this information, we can distinguish any CPU microarchitecture. Inside __uarch.c__ there is a function that behaves as it had a database. It will search, for this information, what kind of microarchitecture the current CPU is. I got the data using and adapting the code form Todd Allen's cpuid program (Link 5 in [Useful documentation](#useful-documentation)). From the microarchitecture, we can obtain the manufacturing process (or technology, the size in nm of the transistors).
+
+### 6. How to get CPU topology?
+__Involved code: cpuid.h, get_topology_info (cpuid.c), apic.c__
+
+cpufetch tries to support the most complex systems, so it supports multi socket CPUs and a detailed SMT (Intel HyperThreading) information. The CPU topology is stored like this:
+
+```
+struct topology {
+  int64_t total_cores;
+  uint32_t physical_cores;
+  uint32_t logical_cores;
+  uint32_t smt_available;
+  uint32_t smt_supported;
+  uint32_t sockets;
+};
+```
+
+This structure needs a bit of explanation, to know what are we looking for:
+- `physical_cores`: Number of physical cores. In a multi socket system, this field stores the number of cores for just one socket.
+- `logical_cores`: Number of logical cores. In a multi socket system, this field stores the number of logical cores for just one socket.
+- `total_cores`: Total number of logical cores. In a multi socket system, this field stores the number of logical cores for the entire system.
+- `sockets`: How many sockets the system has.
+- `smt_supported`: Stores if SMT (or Intel HT) is supported in the CPU, storing the number of threads per core. So, if `smt_supported == 1`, it means that there is 1 thread per core, and SMT is not supported. If SMT is supported, then `smt_supported >= 1`. Note this field tells if CPU if supports it, but not if SMT is activated or not.
+- `smt_available`: The same idea as `smt_supported`, but it stores if SMT is available. If SMT is not supported, then `smt_available` is always `1`. The differentiation between supported and available lets cpufetch distinguish when a CPU has SMT capabilities, but are disabled (probably in the BIOS).
+
+Let's give two CPU examples and the values that `struct topology` would have in these CPUs.
+- Example 1: Dual Socket Intel Xeon 6248:
+
+```
+total_cores = 80
+physical_cores = 20
+logical_cores = 40
+smt_available = 2
+smt_supported = 2
+sockets = 2
+```
+
+- Example 2: Intel Core i7-4790K with SMT disabled in BIOS:
+
+```
+total_cores = 8
+physical_cores = 4
+logical_cores = 8
+smt_available = 1
+smt_supported = 2
+sockets = 1
+```
+
+Now that we know what data are we looking for, let's see how we get it:
+
+- __Intel__: We use the methodology explained in the Intel webpage (Link 2 in [Useful documentation](#useful-documentation)). Here, Intel explains how to do it and also gives an example source code. I used it and modified it to fit cpufetch style. The core of this methodology is the usage of the APIC id, so the code is inside __apic.c__.
+- __AMD__: Intel's algorithm using APIC does not work for AMD. To get the same information in AMD, I used the reference from OSdev(Link 3 in [Useful documentation](#useful-documentation)) and also ideas from lscpu(Link 4 in [Useful documentation](#useful-documentation)). This uses:
+  - CPUID extended leaf 0x8: Fill `logical_cores`
+  - CPUID extended leaf 0x1E: Fill `smt_supported`
+  - CPUID standard leaf 0x1 (APIC): Fill `smt_available`
+
+  If any of these levels are not supported, these fields are just guessed. For example, if we are not able to know if SMT is supported, we guess it is not. With all of these data, we can calculate the rest of the fields:
+
+  ```
+  physical_cores = logical_cores / smt_available;  
+  if(topo->smt_supported > 1)
+    sockets = total_cores / smt_supported / physical_cores; // Idea borrowed from lscpu
+  else
+    sockets = total_cores / physical_cores;    
+  ```
+
+### 7. How to get cache topology?
+__Involved code: get_cache_topology_amd (cpuid.c), apic.c__
+
+The topology is reduced to the idea of how many caches we have at a given level. It usually follows the rule of:
+- L1: The same as the number of cores (one L1i and one L1d per core).
+- L2: If L2 is the last level cache, one L2. If not, the same as the number of cores (one L2 per core).
+- L3: One L3 cache per socket (shared among all cores).
+
+These assumptions are generally (but not always) true. For example, for the AMD Zen generation, or the Intel Xeon Phi KNL. Thus, cpufetch does not assume the topology and tries to fetch it instead.
+
+- __Intel__: We can use the methodology explained in the Intel webpage (Link 2 in [Useful documentation](#useful-documentation)) again (it also covers how to get cache topology using APIC id).
+
+- __AMD__: Again, we have to look another path for AMD. This time, the way to do it is easier and (I think) more solid and future proof. We just use extended CPUID leaf 0x1D. If the CPU does not support it, we can still guess the topology of the caches (as mentioned earlier). If it does, CPUID can give us how many cores shares a given level of cache. So, if we have the number of cores, we can guess how many caches are there for any given level (see __get_cache_topology_amd__).
+
+#### Useful documentation
+- Link 1: [sandpile CPUID webpage](https://www.sandpile.org/x86/cpuid.htm)
+- Link 2: [CPU topology and cache topology: Intel](https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html)
+- Link 3: [CPU topology: AMD](https://wiki.osdev.org/Detecting_CPU_Topology_(80x86))
+- Link 4: [lscpu](https://github.com/karelzak/util-linux/blob/master/sys-utils/lscpu.c)
+- Link 5: [Todd Allen's cpuid](http://www.etallen.com/cpuid.html)
+- Link 6: [AMD specific CPUID specification](https://www.amd.com/system/files/TechDocs/25481.pdf)
+
+In addition to all these resources, I found very interesting to search in the Linux kernel source code (for example, the directory `arch/x86/kernel/cpu/`), because sometetimes you can find ideas that cannot be found anywhere else!
--- a/doc/README.md
+++ b/doc/README.md
@@ -0,0 +1,56 @@
+# cpufetch programming documentation (v0.88)
+This documentation explains how cpufetch works internally and all the design decisions I made. The intention of this documentation is to be useful for me in the future, for everyone interested in the project, and for anyone who is trying to obtain any specific information from the CPU. In this way, this can be used as a manual or a page which collects interesting material in this area.
+
+### 1. Basics
+cpufetch works for __x86_64__ CPUs (Intel and AMD) and experimental support for __ARM__. Other kinds of x86_64 CPU are not supported (I don't think supporting other CPUs may pay off). Depending on the architecture, cpufetch choose certain files to be compiled. A summarized tree of the source code of cpufetch is shown below.
+
+```
+cpufetch/
+├── DOCUMENTATION.md
+├── Makefile
+├── README.md
+└── src/
+    ├── arm/
+    │   ├── midr.c
+    │   ├── midr.h
+    │   └── other files ...
+    ├── common/
+    │   └── common files ...
+    └── x86/
+        ├── cpuid.c
+        ├── cpuid.h
+        └── other files ...
+```
+
+Source code is divided in three directories:
+
+- `common/`: Source code shared beteen x86 and ARM
+- `arm/`: ARM dependant source code
+- `x86/`: x86_64 dependant source code
+
+##### 1.1 Basics (x86_64)
+
+In x86, __cpufetch works using the CPUID instruction__. It is called directly using assembly (see `src/x86/cpuid_asm.c`). To understand how CPUID works you may have a look at the [Useful documentation](https://github.com/Dr-Noob/cpufetch/blob/master/DOCUMENTATION_x86.md#useful-documentation) section (more precisely, Link 1).
+
+At the beginning of execution, cpufetch needs to know the max standard CPUID level and max CPUID extended level supported in the running CPU. We also need to know if the x86 CPU is Intel or AMD because some fetching depends on it. This information will be stored in:
+
+```
+struct cpuInfo {
+  ...
+  VENDOR cpu_vendor;
+  uint32_t maxLevels;  
+  uint32_t maxExtendedLevels;
+  ...
+};
+```
+
+To use any CPUID leaf, we always need to check that it is supported in the current CPU. cpufetch will always check if the leaf is supported in the current CPU, and will use a different workaround if the CPU is Intel or AMD, which leads us to the following section.
+
+##### 1.2 Basics (ARM)
+In ARM, __cpufetch works using the MIDR register and Linux filesystem__. MIDR (Main ID Register) is fetched from `/proc/cpuinfo`. It allows the detection of the microarchitecture of the cores. Furthermore, Linux filesystem `/sys/devices/system/cpu/` is used to fetch the number of cores, and other information. This is the main reason to explain __why `cpufetch` only works on Linux kernel based systems.__
+
+##### 1.3 Documentation organization
+The rest of the documentation is divided into x86 and ARM architectures, since each one need different implementations:
+
+- [DOCUMENTATION_X86.md](https://github.com/Dr-Noob/cpufetch/blob/master/doc/DOCUMENTATION_X86.md)
+- [DOCUMENTATION_ARM.md](https://github.com/Dr-Noob/cpufetch/blob/master/doc/DOCUMENTATION_ARM.md)
--- a/pictures/cascade_lake.png
+++ b/pictures/cascade_lake.png
--- a/pictures/epyc.png
+++ b/pictures/epyc.png
--- a/pictures/i9.png
+++ b/pictures/i9.png
--- a/preview.png
+++ b/preview.png
--- a/src/args.c
+++ b/src/args.c
@@ -1,118 +0,0 @@
-#include <getopt.h>
-#include <stdio.h>
-#include <string.h>
-#include "args.h"
-
-#define ARG_STR_STYLE    "style"
-#define ARG_STR_HELP     "help"
-#define ARG_STR_VERSION  "version"
-#define ARG_CHAR_STYLE    's'
-#define ARG_CHAR_HELP     'h'
-#define ARG_CHAR_VERSION  'v'
-#define STYLE_STR_1 "default"
-#define STYLE_STR_2 "dark"
-#define STYLE_STR_3 "none"
-
-struct args_struct {
-  int help_flag;
-  int version_flag;
-  STYLE style;
-};
-
-static const char* SYTLES_STR_LIST[STYLES_COUNT] = { STYLE_STR_1, STYLE_STR_2, STYLE_STR_3 };
-static struct args_struct args;
-
-STYLE parseStyle(char* style) {
-  int i = 0;
-  while(i != STYLES_COUNT && strcmp(SYTLES_STR_LIST[i],style) != 0)
-    i++;
-
-  if(i == STYLES_COUNT)
-    return STYLE_INVALID;
-  return i;
-}
-
-STYLE getStyle() {
-  return args.style;
-}
-
-int showHelp() {
-  return args.help_flag;
-}
-
-int showVersion() {
-  return args.version_flag;
-}
-
-bool verbose_enabled() {
-  return false;
-}
-
-bool parseArgs(int argc, char* argv[]) {
-  int c;
-  int digit_optind = 0;
-  int option_index = 0;
-  opterr = 0;
-
-  args.help_flag = false;
-  args.style = STYLE_EMPTY;
-
-  static struct option long_options[] = {
-      {ARG_STR_STYLE,    required_argument, 0, ARG_CHAR_STYLE   },
-      {ARG_STR_HELP,     no_argument,       0, ARG_CHAR_HELP    },
-      {ARG_STR_VERSION,  no_argument,       0, ARG_CHAR_VERSION },
-      {0, 0, 0, 0}
-  };
-
-  c = getopt_long(argc, argv,"",long_options, &option_index);
-
-  while (c != -1) {
-     if(c == ARG_CHAR_STYLE) {
-       if(args.style != STYLE_EMPTY) {
-         printf("ERROR: Style option specified more than once\n");
-         return false;
-       }
-       args.style = parseStyle(optarg);
-       if(args.style == STYLE_INVALID) {
-          printf("ERROR: Invalid style '%s'\n",optarg);
-          return false;
-       }
-     }
-     else if(c == ARG_CHAR_HELP) {
-       if(args.help_flag) {
-         printf("ERROR: Help option specified more than once\n");
-         return false;
-       }
-       args.help_flag  = true;
-     }
-     else if (c == ARG_CHAR_VERSION) {
-       if(args.version_flag) {
-         printf("ERROR: Version option specified more than once\n");
-         return false;
-       }
-       args.version_flag = true;
-     }
-     else if(c == '?') {
-       printf("WARNING: Invalid options\n");
-       args.help_flag  = true;
-       break;
-     }
-     else
-      printf("Bug at line number %d in file %s\n", __LINE__, __FILE__);
-
-    option_index = 0;
-    c = getopt_long(argc, argv,"",long_options, &option_index);
-  }
-
-  if (optind < argc) {
-    printf("WARNING: Invalid options\n");
-    args.help_flag  = true;
-  }
-
-  if((args.help_flag + args.version_flag + (args.style != STYLE_EMPTY)) > 1) {
-    printf("WARNING: You should specify just one option\n");
-    args.help_flag  = true;
-  }
-
-  return true;
-}
--- a/src/args.h
+++ b/src/args.h
@@ -1,13 +0,0 @@
-#ifndef __ARGS__
-#define __ARGS__
-
-#include <stdbool.h>
-#include "printer.h"
-
-bool parseArgs(int argc, char* argv[]);
-STYLE getStyle();
-int showHelp();
-int showVersion();
-bool verbose_enabled();
-
-#endif
--- a/src/arm/midr.c
+++ b/src/arm/midr.c
@@ -0,0 +1,330 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <sys/auxv.h>
+#include <asm/hwcap.h>
+
+#include "../common/global.h"
+#include "udev.h"
+#include "midr.h"
+#include "uarch.h"
+#include "soc.h"
+
+#define STRING_UNKNOWN    "Unknown"
+
+void init_cache_struct(struct cache* cach) {
+  cach->L1i = malloc(sizeof(struct cach));
+  cach->L1d = malloc(sizeof(struct cach));
+  cach->L2 = malloc(sizeof(struct cach));
+  cach->L3 = malloc(sizeof(struct cach));
+
+  cach->cach_arr = malloc(sizeof(struct cach*) * 4);
+  cach->cach_arr[0] = cach->L1i;
+  cach->cach_arr[1] = cach->L1d;
+  cach->cach_arr[2] = cach->L2;
+  cach->cach_arr[3] = cach->L3;
+
+  cach->max_cache_level = 0;
+  cach->L1i->exists = false;
+  cach->L1d->exists = false;
+  cach->L2->exists = false;
+  cach->L3->exists = false;
+}
+
+struct cache* get_cache_info(struct cpuInfo* cpu) { 
+  struct cache* cach = malloc(sizeof(struct cache));
+  init_cache_struct(cach);
+
+  cach->max_cache_level = 2;
+  for(int i=0; i < cach->max_cache_level + 1; i++) {
+    cach->cach_arr[i]->exists = true;
+    cach->cach_arr[i]->num_caches = 1;
+    cach->cach_arr[i]->size = 0;
+  }
+
+  return cach;
+}
+
+struct frequency* get_frequency_info(uint32_t core) {
+  struct frequency* freq = malloc(sizeof(struct frequency));
+
+  freq->base = UNKNOWN_FREQ;
+  freq->max = get_max_freq_from_file(core);
+
+  return freq;
+}
+
+struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, uint32_t* midr_array, int socket_idx, int ncores) {
+  struct topology* topo = malloc(sizeof(struct topology));
+
+  topo->cach = cach;
+  topo->total_cores = 0;
+  
+  int sockets_seen = 0;
+  int first_core_idx = 0;
+  int currrent_core_idx = 0;
+  int cores_in_socket = 0;
+  
+  while(socket_idx + 1 > sockets_seen) {
+    if(midr_array[first_core_idx] == midr_array[currrent_core_idx] && currrent_core_idx < ncores) {
+      currrent_core_idx++;
+      cores_in_socket++;
+    }
+    else {
+      topo->total_cores = cores_in_socket;  
+      cores_in_socket = 0;
+      first_core_idx = currrent_core_idx;
+      sockets_seen++;
+    }
+  }
+  
+  return topo;
+}
+
+bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
+  return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
+}
+    
+uint32_t fill_ids_from_midr(uint32_t* midr_array, int32_t* freq_array, uint32_t* ids_array, int len) {
+  uint32_t latest_id = 0;
+  bool found;
+  ids_array[0] = latest_id;
+
+  for (int i = 1; i < len; i++) {
+    int j = 0;
+    found = false;
+
+    for (j = 0; j < len && !found; j++) {
+      if (i != j && cores_are_equal(i, j, midr_array, freq_array)) {
+        if(j > i) {
+          latest_id++;
+          ids_array[i] = latest_id;
+        }
+        else {
+          ids_array[i] = ids_array[j];
+        }
+        found = true;
+      }
+    }
+    if(!found) {
+      latest_id++;
+      ids_array[i] = latest_id;
+    }
+  }
+
+  return latest_id+1;
+}
+
+void init_cpu_info(struct cpuInfo* cpu) {
+  cpu->next_cpu = NULL;
+}
+
+// We assume all cpus share the same hardware
+// capabilities but I'm not sure it is always
+// true...
+// ARM32 https://elixir.bootlin.com/linux/latest/source/arch/arm/include/uapi/asm/hwcap.h
+// ARM64 https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/uapi/asm/hwcap.h
+struct features* get_features_info() {
+  struct features* feat = malloc(sizeof(struct features));
+  bool *ptr = &(feat->AES);
+  for(uint32_t i = 0; i < sizeof(struct features)/sizeof(bool); i++, ptr++) {
+    *ptr = false;
+  }
+  
+  errno = 0;
+  long hwcaps = getauxval(AT_HWCAP);
+  
+  if(errno == ENOENT) {
+    printWarn("Unable to retrieve AT_HWCAP using getauxval");    
+  }
+#ifdef __aarch64__
+  else {
+    feat->AES = hwcaps & HWCAP_AES;
+    feat->CRC32 = hwcaps & HWCAP_CRC32;
+    feat->SHA1 = hwcaps & HWCAP_SHA1;
+    feat->SHA2 = hwcaps & HWCAP_SHA2;
+    feat->NEON = hwcaps & HWCAP_ASIMD;
+  }
+#else
+  else {
+    feat->NEON = hwcaps & HWCAP_NEON;
+  }
+  
+  hwcaps = getauxval(AT_HWCAP2);
+  if(errno == ENOENT) {
+    printWarn("Unable to retrieve AT_HWCAP2 using getauxval");
+  }
+  else {
+    feat->AES = hwcaps & HWCAP2_AES;
+    feat->CRC32 = hwcaps & HWCAP2_CRC32;
+    feat->SHA1 = hwcaps & HWCAP2_SHA1;
+    feat->SHA2 = hwcaps & HWCAP2_SHA2;
+  }
+#endif
+
+  return feat;
+}
+
+struct cpuInfo* get_cpu_info() {
+  struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
+  init_cpu_info(cpu);
+
+  int ncores = get_ncores_from_cpuinfo();
+  bool success = false;
+  int32_t* freq_array = malloc(sizeof(uint32_t) * ncores);
+  uint32_t* midr_array = malloc(sizeof(uint32_t) * ncores);  
+  uint32_t* ids_array = malloc(sizeof(uint32_t) * ncores);
+
+  for(int i=0; i < ncores; i++) {
+    midr_array[i] = get_midr_from_cpuinfo(i, &success);
+    
+    if(!success) {
+      printWarn("Unable to fetch MIDR for core %d. This is probably because the core is offline", i);
+      midr_array[i] = midr_array[0];
+    }
+    
+    freq_array[i] = get_max_freq_from_file(i);
+    if(freq_array[i] == UNKNOWN_FREQ) {
+      printWarn("Unable to fetch max frequency for core %d. This is probably because the core is offline", i);
+      freq_array[i] = freq_array[0];
+    }    
+  }
+  uint32_t sockets = fill_ids_from_midr(midr_array, freq_array, ids_array, ncores);
+  
+  struct cpuInfo* ptr = cpu;
+  int midr_idx = 0;
+  int tmp_midr_idx = 0;
+  for(uint32_t i=0; i < sockets; i++) {
+    if(i > 0) {
+      ptr->next_cpu = malloc(sizeof(struct cpuInfo));      
+      ptr = ptr->next_cpu;
+      init_cpu_info(ptr);
+
+      tmp_midr_idx = midr_idx;
+      while(cores_are_equal(midr_idx, tmp_midr_idx, midr_array, freq_array)) tmp_midr_idx++;
+      midr_idx = tmp_midr_idx;
+    }    
+    
+    ptr->midr = midr_array[midr_idx];
+    ptr->arch = get_uarch_from_midr(ptr->midr, ptr);
+    
+    ptr->feat = get_features_info();
+    ptr->freq = get_frequency_info(midr_idx);
+    ptr->cach = get_cache_info(ptr);
+    ptr->topo = get_topology_info(ptr, ptr->cach, midr_array, i, ncores);
+  }
+  
+  cpu->num_cpus = sockets;
+  cpu->hv = malloc(sizeof(struct hypervisor));
+  cpu->hv->present = false;
+  cpu->soc = get_soc();  
+
+  return cpu;
+}
+
+char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket) {
+  uint32_t size = 3+7+1;
+  char*  string = malloc(sizeof(char)*size);
+  snprintf(string, size, "%d cores", topo->total_cores);
+
+  return string;
+}
+
+char* get_str_peak_performance(struct cpuInfo* cpu) { 
+  //7 for GFLOP/s and 6 for digits,eg 412.14
+  uint32_t size = 7+6+1+1;
+  assert(strlen(STRING_UNKNOWN)+1 <= size);
+  char* string = malloc(sizeof(char)*size);
+  struct cpuInfo* ptr = cpu;
+  
+  //First check we have consistent data
+  for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
+    if(get_freq(ptr->freq) == UNKNOWN_FREQ) {
+      snprintf(string, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+      return string;
+    }
+  }
+
+  double flops = 0.0;
+  
+  ptr = cpu;
+  for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
+    flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000);
+  }
+  if(cpu->feat->NEON) flops = flops * 4;
+  
+  if(flops >= (double)1000000000000.0)
+    snprintf(string,size,"%.2f TFLOP/s",flops/1000000000000);
+  else if(flops >= 1000000000.0)
+    snprintf(string,size,"%.2f GFLOP/s",flops/1000000000);
+  else
+    snprintf(string,size,"%.2f MFLOP/s",flops/1000000);
+
+  return string;
+}
+
+char* get_str_features(struct cpuInfo* cpu) {
+  struct features* feat = cpu->feat;  
+  char* string = malloc(sizeof(char) * 25);
+  uint32_t len = 0;
+  
+  if(feat->NEON) {
+    strcat(string, "NEON,");
+    len += 5;
+  }
+  if(feat->SHA1) {
+    strcat(string, "SHA1,");
+    len += 5;
+  }
+  if(feat->SHA2) {
+    strcat(string, "SHA2,");
+    len += 5;
+  }
+  if(feat->AES) {
+    strcat(string, "AES,");
+    len += 4;
+  }
+  if(feat->CRC32) {
+    strcat(string, "CRC32,");
+    len += 6;
+  }
+  
+  if(len > 0) {
+    string[len-1] = '\0';
+    return string;
+  }
+  else  
+    return NULL;    
+}
+
+void print_debug(struct cpuInfo* cpu) {
+  int ncores = get_ncores_from_cpuinfo();
+  bool success = false;
+  
+  for(int i=0; i < ncores; i++) {
+    printf("[Core %d] ", i);
+    long freq = get_max_freq_from_file(i);
+    uint32_t midr = get_midr_from_cpuinfo(i, &success);
+    if(!success) {
+      printWarn("Unable to fetch MIDR for core %d. This is probably because the core is offline", i);
+      printf("0x%.8X ", get_midr_from_cpuinfo(0, &success));
+    }
+    else {
+      printf("0x%.8X ", midr);    
+    }
+    if(freq == UNKNOWN_FREQ) {
+      printWarn("Unable to fetch max frequency for core %d. This is probably because the core is offline", i);
+      printf("%ld MHz\n", get_max_freq_from_file(0));
+    }
+    else {
+      printf("%ld MHz\n", freq);    
+    }
+  }    
+}
+
+void free_topo_struct(struct topology* topo) {
+  free(topo);
+}
--- a/src/arm/midr.h
+++ b/src/arm/midr.h
@@ -0,0 +1,70 @@
+#ifndef __MIDR__
+#define __MIDR__
+
+#include "../common/cpu.h"
+
+struct cpuInfo* get_cpu_info();
+
+uint32_t get_nsockets(struct topology* topo);
+char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket);
+char* get_str_peak_performance(struct cpuInfo* cpu);
+char* get_str_features(struct cpuInfo* cpu);
+
+void print_debug(struct cpuInfo* cpu);
+void free_topo_struct(struct topology* topo);
+
+// Code taken from cpuinfo (https://github.com/pytorch/cpuinfo/blob/master/src/arm/midr.h)
+#define CPUINFO_ARM_MIDR_IMPLEMENTER_MASK  UINT32_C(0xFF000000)
+#define CPUINFO_ARM_MIDR_VARIANT_MASK      UINT32_C(0x00F00000)
+#define CPUINFO_ARM_MIDR_ARCHITECTURE_MASK UINT32_C(0x000F0000)
+#define CPUINFO_ARM_MIDR_PART_MASK         UINT32_C(0x0000FFF0)
+#define CPUINFO_ARM_MIDR_REVISION_MASK     UINT32_C(0x0000000F)
+
+#define CPUINFO_ARM_MIDR_IMPLEMENTER_OFFSET  24
+#define CPUINFO_ARM_MIDR_VARIANT_OFFSET      20
+#define CPUINFO_ARM_MIDR_ARCHITECTURE_OFFSET 16
+#define CPUINFO_ARM_MIDR_PART_OFFSET          4
+#define CPUINFO_ARM_MIDR_REVISION_OFFSET      0
+
+inline static uint32_t midr_set_implementer(uint32_t midr, uint32_t implementer) {
+        return (midr & ~CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) |
+                ((implementer << CPUINFO_ARM_MIDR_IMPLEMENTER_OFFSET) & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK);
+}
+
+inline static uint32_t midr_set_variant(uint32_t midr, uint32_t variant) {
+        return (midr & ~CPUINFO_ARM_MIDR_VARIANT_MASK) |
+                ((variant << CPUINFO_ARM_MIDR_VARIANT_OFFSET) & CPUINFO_ARM_MIDR_VARIANT_MASK);
+}
+
+inline static uint32_t midr_set_architecture(uint32_t midr, uint32_t architecture) {
+        return (midr & ~CPUINFO_ARM_MIDR_ARCHITECTURE_MASK) |
+                ((architecture << CPUINFO_ARM_MIDR_ARCHITECTURE_OFFSET) & CPUINFO_ARM_MIDR_ARCHITECTURE_MASK);
+}
+
+inline static uint32_t midr_set_part(uint32_t midr, uint32_t part) {
+        return (midr & ~CPUINFO_ARM_MIDR_PART_MASK) |
+                ((part << CPUINFO_ARM_MIDR_PART_OFFSET) & CPUINFO_ARM_MIDR_PART_MASK);
+}
+
+inline static uint32_t midr_set_revision(uint32_t midr, uint32_t revision) {
+        return (midr & ~CPUINFO_ARM_MIDR_REVISION_MASK) |
+                ((revision << CPUINFO_ARM_MIDR_REVISION_OFFSET) & CPUINFO_ARM_MIDR_REVISION_MASK);
+}
+
+inline static uint32_t midr_get_variant(uint32_t midr) {
+	return (midr & CPUINFO_ARM_MIDR_VARIANT_MASK) >> CPUINFO_ARM_MIDR_VARIANT_OFFSET;
+}
+
+inline static uint32_t midr_get_implementer(uint32_t midr) {
+	return (midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) >> CPUINFO_ARM_MIDR_IMPLEMENTER_OFFSET;
+}
+
+inline static uint32_t midr_get_part(uint32_t midr) {
+	return (midr & CPUINFO_ARM_MIDR_PART_MASK) >> CPUINFO_ARM_MIDR_PART_OFFSET;
+}
+
+inline static uint32_t midr_get_revision(uint32_t midr) {
+	return (midr & CPUINFO_ARM_MIDR_REVISION_MASK) >> CPUINFO_ARM_MIDR_REVISION_OFFSET;
+}
+
+#endif
--- a/src/arm/soc.c
+++ b/src/arm/soc.c
@@ -0,0 +1,562 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+
+#include "soc.h"
+#include "socs.h"
+#include "udev.h"
+#include "../common/global.h"
+
+#define min(a,b) (((a)<(b))?(a):(b))
+#define STRING_UNKNOWN    "Unknown"
+
+static char* soc_trademark_string[] = {
+  [SOC_VENDOR_SNAPDRAGON] = "Snapdragon ",
+  [SOC_VENDOR_MEDIATEK]   = "MediaTek ",
+  [SOC_VENDOR_EXYNOS]     = "Exynos ",
+  [SOC_VENDOR_KIRIN]      = "Kirin ",
+  [SOC_VENDOR_BROADCOM]   = "Broadcom BCM",
+};
+
+void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process) {
+  soc->soc_model = soc_model;
+  soc->soc_vendor = get_soc_vendor_from_soc(soc_model);
+  soc->process = process;
+  int len = strlen(soc_name) + strlen(soc_trademark_string[soc->soc_vendor]) + 1;
+  soc->soc_name = malloc(sizeof(char) * len);
+  memset(soc->soc_name, 0, sizeof(char) * len);
+  sprintf(soc->soc_name, "%s%s", soc_trademark_string[soc->soc_vendor], soc_name);    
+}
+
+bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
+  if(strlen(raw_name) > strlen(expected_name))
+    return false;
+  
+  int len = strlen(raw_name);
+  if(strncmp(raw_name, expected_name, len) != 0) {
+    return false;
+  }
+  else {
+    fill_soc(soc, soc_name, soc_model, process);
+    return true;    
+  }
+}
+
+char* toupperstr(char* str) {
+  int len = strlen(str) + 1;
+  char* ret = malloc(sizeof(char) * len);
+  memset(ret, 0, sizeof(char) * len);
+  
+  for(int i=0; i < len; i++) {
+    ret[i] = toupper((unsigned char) str[i]);    
+  }
+  
+  return ret;
+}
+
+#define SOC_START if (false) {}
+#define SOC_EQ(raw_name, expected_name, soc_name, soc_model, soc, process) \
+   else if (match_soc(soc, raw_name, expected_name, soc_name, soc_model, process)) return true;
+#define SOC_END else { return false; }
+
+// https://en.wikipedia.org/wiki/Raspberry_Pi
+// http://phonedb.net/index.php?m=processor&id=562&c=broadcom_bcm21663
+// https://hwbot.org/hardware/processors#key=bcmxxx
+bool match_broadcom(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+
+  if((tmp = strstr(soc_name, "BCM")) == NULL)
+    return false;
+  
+  SOC_START
+  SOC_EQ(tmp, "BCM2835",              "2835",              SOC_BCM_2835,   soc, 65)    
+  SOC_EQ(tmp, "BCM2836",              "2836",              SOC_BCM_2836,   soc, 40)    
+  SOC_EQ(tmp, "BCM2837",              "2837",              SOC_BCM_2837,   soc, 40) 
+  SOC_EQ(tmp, "BCM2837B0",            "2837B0",            SOC_BCM_2837B0, soc, 40) 
+  SOC_EQ(tmp, "BCM2711",              "2711",              SOC_BCM_2711,   soc, 28)  
+  SOC_EQ(tmp, "BCM21553",             "21553",             SOC_BCM_21553,  soc, 65)    
+  SOC_EQ(tmp, "BCM21553-Thunderbird", "21553 Thunderbird", SOC_BCM_21553T, soc, 65)      
+  SOC_EQ(tmp, "BCM21663",             "21663",             SOC_BCM_21663,  soc, 40) 
+  SOC_EQ(tmp, "BCM21664",             "21664",             SOC_BCM_21664,  soc, 40) 
+  SOC_EQ(tmp, "BCM28155",             "28155",             SOC_BCM_28155,  soc, 40) 
+  SOC_EQ(tmp, "BCM23550",             "23550",             SOC_BCM_23550,  soc, 40) 
+  SOC_EQ(tmp, "BCM28145",             "28145",             SOC_BCM_28145,  soc, 40) 
+  SOC_EQ(tmp, "BCM2157",              "2157",              SOC_BCM_2157,   soc, 65) 
+  SOC_EQ(tmp, "BCM21654",             "21654",             SOC_BCM_21654,  soc, 40) 
+  SOC_END
+}
+
+// https://www.techinsights.com/
+// https://datasheetspdf.com/pdf-file/1316605/HiSilicon/Hi3660/1
+bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+
+  if((tmp = strstr(soc_name, "Hi")) == NULL)
+    return false;
+  
+  SOC_START
+  SOC_EQ(tmp, "Hi3620GFC",  "K3V2",  SOC_HISILICON_3620, soc, 40)
+  //SOC_EQ(tmp, "?",        "K3V2E", SOC_KIRIN, soc,  ?)
+  //SOC_EQ(tmp, "?",        "620",   SOC_KIRIN, soc, 28)
+  //SOC_EQ(tmp, "?",        "650",   SOC_KIRIN, soc, 16)
+  //SOC_EQ(tmp, "?",        "655",   SOC_KIRIN, soc, 16)
+  //SOC_EQ(tmp, "?",        "658",   SOC_KIRIN, soc, 16)
+  //SOC_EQ(tmp, "?",        "659",   SOC_KIRIN, soc, 16)
+  //SOC_EQ(tmp, "?",        "710",   SOC_KIRIN, soc, 12)
+  //SOC_EQ(tmp, "?",        "710A",  SOC_KIRIN, soc, 12)
+  //SOC_EQ(tmp, "?",        "710F",  SOC_KIRIN, soc, 12)
+  //SOC_EQ(tmp, "?",        "810",   SOC_KIRIN, soc,  7)
+  //SOC_EQ(tmp, "?",        "820",   SOC_KIRIN, soc,  7)
+  //SOC_EQ(tmp, "?",        "9000",  SOC_KIRIN, soc,  5)
+  //SOC_EQ(tmp, "?",        "9000E", SOC_KIRIN, soc,  5)
+  //SOC_EQ(tmp, "?",        "910",   SOC_KIRIN, soc, 28)
+  //SOC_EQ(tmp, "?",        "910T",  SOC_KIRIN, soc, 28)
+  SOC_EQ(tmp, "Hi3630",     "920",   SOC_HISILICON_3630, soc, 28)
+  //SOC_EQ(tmp, "?",        "925",   SOC_KIRIN, soc, 28)
+  //SOC_EQ(tmp, "?",        "930",   SOC_KIRIN, soc, ?)
+  //SOC_EQ(tmp, "?",        "935",   SOC_KIRIN, soc, ?)
+  SOC_EQ(tmp, "Hi3650",     "950",   SOC_HISILICON_3650, soc, 16)
+  //SOC_EQ(tmp, "?",        "955",   SOC_KIRIN, soc, ?)
+  SOC_EQ(tmp, "Hi3660",     "960",   SOC_HISILICON_3660, soc, 16)
+  //SOC_EQ(tmp, "?",        "960S",  SOC_KIRIN, soc, 16)
+  SOC_EQ(tmp, "Hi3670",     "970",   SOC_HISILICON_3670, soc, 10)
+  SOC_EQ(tmp, "Hi3680",     "980",   SOC_HISILICON_3680, soc,  7)
+  //SOC_EQ(tmp, "?",        "985",   SOC_KIRIN, soc,  7)
+  SOC_EQ(tmp, "Hi3690",     "990",   SOC_HISILICON_3690, soc,  7)
+  SOC_END
+}
+
+bool match_exynos(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+
+  if((tmp = strstr(soc_name, "universal")) == NULL)
+    return false;
+  
+  SOC_START
+  // universalXXXX //
+  SOC_EQ(tmp, "universal3475", "3475", SOC_EXYNOS_3475, soc, 28) 
+  SOC_EQ(tmp, "universal4210", "4210", SOC_EXYNOS_4210, soc, 45)
+  SOC_EQ(tmp, "universal4212", "4212", SOC_EXYNOS_4212, soc, 32)
+  SOC_EQ(tmp, "universal4412", "4412", SOC_EXYNOS_4412, soc, 32)
+  SOC_EQ(tmp, "universal5250", "5250", SOC_EXYNOS_5250, soc, 32)
+  SOC_EQ(tmp, "universal5410", "5410", SOC_EXYNOS_5410, soc, 28)
+  SOC_EQ(tmp, "universal5420", "5420", SOC_EXYNOS_5420, soc, 28)
+  SOC_EQ(tmp, "universal5422", "5422", SOC_EXYNOS_5422, soc, 28)
+  SOC_EQ(tmp, "universal5430", "5430", SOC_EXYNOS_5430, soc, 20)
+  SOC_EQ(tmp, "universal5433", "5433", SOC_EXYNOS_5433, soc, 20)
+  SOC_EQ(tmp, "universal5260", "5260", SOC_EXYNOS_5260, soc, 28)
+  SOC_EQ(tmp, "universal7270", "7270", SOC_EXYNOS_7270, soc, 14)
+  SOC_EQ(tmp, "universal7420", "7420", SOC_EXYNOS_7420, soc, 14)
+  SOC_EQ(tmp, "universal7570", "7570", SOC_EXYNOS_7570, soc, 14)
+  SOC_EQ(tmp, "universal7870", "7870", SOC_EXYNOS_7870, soc, 14)
+  SOC_EQ(tmp, "universal7872", "7872", SOC_EXYNOS_7872, soc, 14)
+  SOC_EQ(tmp, "universal7880", "7880", SOC_EXYNOS_7880, soc, 14)
+  SOC_EQ(tmp, "universal7884", "7884", SOC_EXYNOS_7884, soc, 14)
+  SOC_EQ(tmp, "universal7885", "7885", SOC_EXYNOS_7885, soc, 14)
+  SOC_EQ(tmp, "universal7904", "7904", SOC_EXYNOS_7904, soc, 14)
+  SOC_EQ(tmp, "universal8890", "8890", SOC_EXYNOS_8890, soc, 14)
+  SOC_EQ(tmp, "universal8895", "8895", SOC_EXYNOS_8895, soc, 10)
+  SOC_EQ(tmp, "universal9110", "9110", SOC_EXYNOS_9110, soc, 14)
+  SOC_EQ(tmp, "universal9609", "9609", SOC_EXYNOS_9609, soc, 10)
+  SOC_EQ(tmp, "universal9610", "9610", SOC_EXYNOS_9610, soc, 10)
+  SOC_EQ(tmp, "universal9611", "9611", SOC_EXYNOS_9611, soc, 10)
+  SOC_EQ(tmp, "universal9810", "9810", SOC_EXYNOS_9810, soc, 10)
+  SOC_EQ(tmp, "universal9820", "9820", SOC_EXYNOS_9820, soc,  8)
+  SOC_EQ(tmp, "universal9825", "9825", SOC_EXYNOS_9825, soc,  7)
+  // New exynos. Dont know if they will work //
+  SOC_EQ(tmp, "universal1080", "1080", SOC_EXYNOS_1080, soc,  5)  
+  SOC_EQ(tmp, "universal990",   "990", SOC_EXYNOS_990,  soc,  7)
+  SOC_EQ(tmp, "universal980",   "980", SOC_EXYNOS_980,  soc,  8)    
+  SOC_EQ(tmp, "universal880",   "880", SOC_EXYNOS_880,  soc,  8)
+  SOC_END
+}
+
+bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+
+  if((tmp = strstr(soc_name, "MT")) == NULL)
+    return false;
+  
+  SOC_START
+  // Dimensity //
+  SOC_EQ(tmp, "MT6889",   "Dimensity 1000",  SOC_MTK_MT6889,   soc, 7) 
+  SOC_EQ(tmp, "MT6885Z",  "Dimensity 1000L", SOC_MTK_MT6885Z,  soc, 7) 
+  //SOC_EQ(tmp, "?",      "Dimensity 700",   SOC_MTK_,         soc, 7) 
+  SOC_EQ(tmp, "MT6853",   "Dimensity 720",   SOC_MTK_MT6853,   soc, 7) 
+  SOC_EQ(tmp, "MT6873",   "Dimensity 800",   SOC_MTK_MT6873,   soc, 7)
+  SOC_EQ(tmp, "MT6875",   "Dimensity 820",   SOC_MTK_MT6875,   soc, 7)
+  // Helio //  
+  SOC_EQ(tmp, "MT6761D",  "Helio A20",       SOC_MTK_MT6761D,  soc, 12)
+  SOC_EQ(tmp, "MT6761",   "Helio A22",       SOC_MTK_MT6761,   soc, 12)
+  SOC_EQ(tmp, "MT6762D",  "Helio A25",       SOC_MTK_MT6762D,  soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G25",       SOC_MTK_,         soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G35",       SOC_MTK_,         soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G70",       SOC_MTK_,         soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G80",       SOC_MTK_,         soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G90",       SOC_MTK_,         soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G90T",      SOC_MTK_,         soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio G95",       SOC_MTK_,         soc, 12)
+  SOC_EQ(tmp, "MT6755",   "Helio P10",       SOC_MTK_MT6755M,  soc, 28)
+  SOC_EQ(tmp, "MT6755M",  "Helio P10 M",     SOC_MTK_MT6755M,  soc, 28)
+  SOC_EQ(tmp, "MT6755T",  "Helio P15",       SOC_MTK_MT6755T,  soc, 28)
+  SOC_EQ(tmp, "MT6757",   "Helio P20",       SOC_MTK_MT6757,   soc, 16)
+  SOC_EQ(tmp, "MT6762",   "Helio P22",       SOC_MTK_MT6762,   soc, 12)
+  SOC_EQ(tmp, "MT6763V",  "Helio P23",       SOC_MTK_MT6763V,  soc, 16)
+  SOC_EQ(tmp, "MT6763T",  "Helio P23",       SOC_MTK_MT6763T,  soc, 16)
+  SOC_EQ(tmp, "MT6757CD", "Helio P25",       SOC_MTK_MT6757CD, soc, 16)
+  SOC_EQ(tmp, "MT6758",   "Helio P30",       SOC_MTK_MT6758,   soc, 16)
+  SOC_EQ(tmp, "MT6765",   "Helio P35",       SOC_MTK_MT6765,   soc, 12)
+  SOC_EQ(tmp, "MT6771",   "Helio P60",       SOC_MTK_MT6771,   soc, 12)
+  SOC_EQ(tmp, "MT6768",   "Helio P65",       SOC_MTK_MT6768,   soc, 12)
+  SOC_EQ(tmp, "MT6771T",  "Helio P70",       SOC_MTK_MT6771,   soc, 12)
+  SOC_EQ(tmp, "MT6771V",  "Helio P70",       SOC_MTK_MT6771,   soc, 12)
+  SOC_EQ(tmp, "MT6779",   "Helio P90",       SOC_MTK_MT6779,   soc, 12)
+  //SOC_EQ(tmp, "?",      "Helio P95",       SOC_MTK_,         soc, 12)
+  SOC_EQ(tmp, "MT6795",   "Helio X10",       SOC_MTK_MT6795,   soc, 28)
+  SOC_EQ(tmp, "MT6795T",  "Helio X10 T",     SOC_MTK_MT6795,   soc, 28)
+  SOC_EQ(tmp, "MT6797",   "Helio X20",       SOC_MTK_MT6797,   soc, 20)
+  SOC_EQ(tmp, "MT6797M",  "Helio X20 M",     SOC_MTK_MT6797,   soc, 20)
+  SOC_EQ(tmp, "MT6797D",  "Helio X23",       SOC_MTK_MT6797,   soc, 20)
+  SOC_EQ(tmp, "MT6797T",  "Helio X25",       SOC_MTK_MT6797T,  soc, 20)
+  SOC_EQ(tmp, "MT6797X",  "Helio X27",       SOC_MTK_MT6797X,  soc, 20)
+  SOC_EQ(tmp, "MT6799",   "Helio X30",       SOC_MTK_MT6799,   soc, 10)
+  // MT XXXX //
+  SOC_EQ(tmp, "MT6515",   "MT6515",          SOC_MTK_MT6515,   soc, 40)
+  SOC_EQ(tmp, "MT6516",   "MT6516",          SOC_MTK_MT6516,   soc, 65)
+  SOC_EQ(tmp, "MT6517",   "MT6517",          SOC_MTK_MT6517,   soc, 40)
+  SOC_EQ(tmp, "MT6572",   "MT6572",          SOC_MTK_MT6572,   soc, 28)
+  SOC_EQ(tmp, "MT6572M",  "MT6572M",         SOC_MTK_MT6572M,  soc, 28)
+  SOC_EQ(tmp, "MT6573",   "MT6573",          SOC_MTK_MT6573,   soc, 65)
+  SOC_EQ(tmp, "MT6575",   "MT6575",          SOC_MTK_MT6575,   soc, 40)
+  SOC_EQ(tmp, "MT6577",   "MT6577",          SOC_MTK_MT6577,   soc, 40)
+  SOC_EQ(tmp, "MT6577T",  "MT6577T",         SOC_MTK_MT6577T,  soc, 40)
+  SOC_EQ(tmp, "MT6580",   "MT6580",          SOC_MTK_MT6580,   soc, 28)
+  SOC_EQ(tmp, "MT6582",   "MT6582",          SOC_MTK_MT6582,   soc, 28)
+  SOC_EQ(tmp, "MT6582M",  "MT6582M",         SOC_MTK_MT6582M,  soc, 28)
+  SOC_EQ(tmp, "MT6589",   "MT6589",          SOC_MTK_MT6589,   soc, 28)
+  SOC_EQ(tmp, "MT6589T",  "MT6589T",         SOC_MTK_MT6589T,  soc, 28)
+  SOC_EQ(tmp, "MT6592",   "MT6592",          SOC_MTK_MT6592,   soc, 28)
+  SOC_EQ(tmp, "MT6595",   "MT6595",          SOC_MTK_MT6595,   soc, 28)
+  SOC_EQ(tmp, "MT6732",   "MT6732",          SOC_MTK_MT6732,   soc, 28)
+  SOC_EQ(tmp, "MT6735",   "MT6735",          SOC_MTK_MT6735,   soc, 28)
+  SOC_EQ(tmp, "MT6735M",  "MT6735M",         SOC_MTK_MT6735M,  soc, 28)
+  SOC_EQ(tmp, "MT6735P",  "MT6735P",         SOC_MTK_MT6735P,  soc, 28)
+  SOC_EQ(tmp, "MT6737",   "MT6737",          SOC_MTK_MT6737,   soc, 28)
+  SOC_EQ(tmp, "MT6737M",  "MT6737M",         SOC_MTK_MT6737M,  soc, 28)
+  SOC_EQ(tmp, "MT6737T",  "MT6737T",         SOC_MTK_MT6737T,  soc, 28)
+  SOC_EQ(tmp, "MT6739",   "MT6739",          SOC_MTK_MT6739,   soc, 28)
+  SOC_EQ(tmp, "MT6750",   "MT6750",          SOC_MTK_MT6750,   soc, 28)
+  SOC_EQ(tmp, "MT6750S",  "MT6750S",         SOC_MTK_MT6750S,  soc, 28)
+  SOC_EQ(tmp, "MT6750T",  "MT6750T",         SOC_MTK_MT6750T,  soc, 28)
+  SOC_EQ(tmp, "MT6752",   "MT6752",          SOC_MTK_MT6752,   soc, 28)
+  SOC_EQ(tmp, "MT6753",   "MT6753",          SOC_MTK_MT6753,   soc, 28)
+  SOC_EQ(tmp, "MT6850",   "MT6850",          SOC_MTK_MT6850,   soc, 28)
+  SOC_EQ(tmp, "MT8121",   "MT8121",          SOC_MTK_MT8121,   soc, 40)
+  SOC_EQ(tmp, "MT8125",   "MT8125",          SOC_MTK_MT8125,   soc, 40)
+  SOC_EQ(tmp, "MT8127",   "MT8127",          SOC_MTK_MT8127,   soc, 32)
+  SOC_EQ(tmp, "MT8135",   "MT8135",          SOC_MTK_MT8135,   soc, 28)
+  SOC_EQ(tmp, "MT8163A",  "MT8163A",         SOC_MTK_MT8163A,  soc, 28)
+  SOC_EQ(tmp, "MT8163B",  "MT8163B",         SOC_MTK_MT8163B,  soc, 28)
+  SOC_EQ(tmp, "MT8167B",  "MT8167B",         SOC_MTK_MT8167B,  soc, 28)
+  SOC_EQ(tmp, "MT8173",   "MT8173",          SOC_MTK_MT8173,   soc, 28)
+  SOC_EQ(tmp, "MT8176",   "MT8176",          SOC_MTK_MT8176,   soc, 28)
+  SOC_EQ(tmp, "MT8321",   "MT8321",          SOC_MTK_MT8321,   soc, 28)
+  SOC_EQ(tmp, "MT8382",   "MT8382",          SOC_MTK_MT8382,   soc, 28)
+  SOC_EQ(tmp, "MT8581",   "MT8581",          SOC_MTK_MT8581,   soc, 28)
+  SOC_EQ(tmp, "MT8735",   "MT8735",          SOC_MTK_MT8735,   soc, 28)
+  SOC_EQ(tmp, "MT8765B",  "MT8765B",         SOC_MTK_MT8765B,  soc, 28)
+  SOC_EQ(tmp, "MT8783",   "MT8783",          SOC_MTK_MT8783,   soc, 28)
+  SOC_END
+}
+
+/*
+ * APQ: Application Processor Qualcomm
+ * MSM: Mobile Station Modem
+ * In a APQXXXX or MSMXXXX, the second digit represents:
+ * *------------------*
+ * | Value | Meaning  |
+ * *------------------*
+ * |     0 | No modem |
+ * |     2 | HPSA+    |
+ * |     6 | CDMA     |
+ * |     9 | LTE      |
+ * *------------------*
+ * Ref: https://www.tomshardware.com/reviews/snapdragon-801-performance-xperia-z2,3777-2.html
+ *      TWO-HEADED SNAPDRAGON TAKES FLIGHT By Linley Gwennap
+ *
+ * If Qualcomm official website reports the SoC name without the initial two or three SKU name,
+ * we assume APQ if second number is 0, or MSM if second number is different than 0
+ * 
+ * All SoC names here have been retrieved from official Qualcomm resources. However, Linux kernel
+ * and Android may report the SoC with slightly different. Therefore, this function needs some
+ * rework (e.g, debug with http://specdevice.com/unmoderated.php?lang=en)
+ */
+bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+  char* soc_name_upper = toupperstr(soc_name);
+
+  if((tmp = strstr(soc_name_upper, "MSM")) != NULL);
+  else if((tmp = strstr(soc_name_upper, "SDM")) != NULL);
+  else if((tmp = strstr(soc_name_upper, "APQ")) != NULL);
+  else if((tmp = strstr(soc_name_upper, "SM")) != NULL);    
+  else if((tmp = strstr(soc_name_upper, "QM")) != NULL);      
+  else if((tmp = strstr(soc_name_upper, "QSD")) != NULL);
+  else return false;
+  
+  SOC_START
+  // Snapdragon S1 //
+  SOC_EQ(tmp, "QSD8650",        "S1",        SOC_SNAPD_QSD8650,        soc, 65)
+  SOC_EQ(tmp, "QSD8250",        "S1",        SOC_SNAPD_QSD8250,        soc, 65)
+  SOC_EQ(tmp, "MSM7627",        "S1",        SOC_SNAPD_MSM7627,        soc, 65)
+  SOC_EQ(tmp, "MSM7227",        "S1",        SOC_SNAPD_MSM7227,        soc, 65)
+  SOC_EQ(tmp, "MSM7627A",       "S1",        SOC_SNAPD_MSM7627A,       soc, 45)
+  SOC_EQ(tmp, "MSM7227A",       "S1",        SOC_SNAPD_MSM7227A,       soc, 45)
+  SOC_EQ(tmp, "MSM7625",        "S1",        SOC_SNAPD_MSM7625,        soc, 65)
+  SOC_EQ(tmp, "MSM7225",        "S1",        SOC_SNAPD_MSM7225,        soc, 65)
+  SOC_EQ(tmp, "MSM7625A",       "S1",        SOC_SNAPD_MSM7625A,       soc, 45)
+  SOC_EQ(tmp, "MSM7225A",       "S1",        SOC_SNAPD_MSM7225A,       soc, 45)
+  // Snapdragon S2 //
+  SOC_EQ(tmp, "MSM8655",        "S2",        SOC_SNAPD_MSM8655,        soc, 45) 
+  SOC_EQ(tmp, "MSM8255",        "S2",        SOC_SNAPD_MSM8255,        soc, 45) 
+  SOC_EQ(tmp, "APQ8055",        "S2",        SOC_SNAPD_APQ8055,        soc, 45)
+  SOC_EQ(tmp, "MSM7630",        "S2",        SOC_SNAPD_MSM7630,        soc, 45)
+  SOC_EQ(tmp, "MSM7230",        "S2",        SOC_SNAPD_MSM7230,        soc, 45)     
+  // Snapdragon S3 //
+  SOC_EQ(tmp, "MSM8660",        "S3",        SOC_SNAPD_MSM8660,        soc, 45) 
+  SOC_EQ(tmp, "MSM8260",        "S3",        SOC_SNAPD_MSM8260,        soc, 45)   
+  SOC_EQ(tmp, "APQ8060",        "S3",        SOC_SNAPD_APQ8060,        soc, 45) 
+  // Snapdragon S4 //
+  SOC_EQ(tmp, "MSM8225",        "S4 Play",   SOC_SNAPD_MSM8225,        soc, 45)
+  SOC_EQ(tmp, "MSM8625",        "S4 Play",   SOC_SNAPD_MSM8625,        soc, 45)
+  SOC_EQ(tmp, "APQ8060A",       "S4 Plus",   SOC_SNAPD_APQ8060A,       soc, 28) 
+  SOC_EQ(tmp, "MSM8960",        "S4 Plus",   SOC_SNAPD_MSM8960,        soc, 28) 
+  SOC_EQ(tmp, "MSM8260A",       "S4 Plus",   SOC_SNAPD_MSM8260A,       soc, 28) 
+  SOC_EQ(tmp, "MSM8627",        "S4 Plus",   SOC_SNAPD_MSM8627,        soc, 28)   
+  SOC_EQ(tmp, "MSM8227",        "S4 Plus",   SOC_SNAPD_MSM8227,        soc, 28)   
+  SOC_EQ(tmp, "APQ8064",        "S4 Pro",    SOC_SNAPD_APQ8064,        soc, 28) 
+  SOC_EQ(tmp, "MSM8960T",       "S4 Pro",    SOC_SNAPD_MSM8960T,       soc, 28) 
+  // Snapdragon 2XX //
+  SOC_EQ(tmp, "MSM8110",        "200",       SOC_SNAPD_MSM8110,        soc, 28) 
+  SOC_EQ(tmp, "MSM8210",        "200",       SOC_SNAPD_MSM8210,        soc, 28) 
+  SOC_EQ(tmp, "MSM8610",        "200",       SOC_SNAPD_MSM8610,        soc, 28) 
+  SOC_EQ(tmp, "MSM8112",        "200",       SOC_SNAPD_MSM8112,        soc, 28) 
+  SOC_EQ(tmp, "MSM8212",        "200",       SOC_SNAPD_MSM8212,        soc, 28) 
+  SOC_EQ(tmp, "MSM8612",        "200",       SOC_SNAPD_MSM8612,        soc, 28) 
+  SOC_EQ(tmp, "MSM8225Q",       "200",       SOC_SNAPD_MSM8225Q,       soc, 45) 
+  SOC_EQ(tmp, "MSM8625Q",       "200",       SOC_SNAPD_MSM8625Q,       soc, 45) 
+  SOC_EQ(tmp, "MSM8208",        "208",       SOC_SNAPD_MSM8208,        soc, 28) 
+  SOC_EQ(tmp, "MSM8905",        "205",       SOC_SNAPD_MSM8905,        soc, 28) 
+  SOC_EQ(tmp, "MSM8909",        "210 / 212", SOC_SNAPD_MSM8909,        soc, 28) // In the future, we can differenciate them using frequency
+  SOC_EQ(tmp, "QM215",          "215",       SOC_SNAPD_QM215,          soc, 28)
+  // Snapdragon 4XX //
+  SOC_EQ(tmp, "APQ8028",        "400",       SOC_SNAPD_APQ8028,        soc, 28)
+  SOC_EQ(tmp, "MSM8228",        "400",       SOC_SNAPD_MSM8228,        soc, 28)
+  SOC_EQ(tmp, "MSM8628",        "400",       SOC_SNAPD_MSM8628,        soc, 28)
+  SOC_EQ(tmp, "MSM8928",        "400",       SOC_SNAPD_MSM8928,        soc, 28)
+  SOC_EQ(tmp, "MSM8926",        "400",       SOC_SNAPD_MSM8926,        soc, 28)
+  SOC_EQ(tmp, "APQ8030AB",      "400",       SOC_SNAPD_APQ8030AB,      soc, 28)
+  SOC_EQ(tmp, "MSM8226",        "400",       SOC_SNAPD_MSM8226,        soc, 28)
+  SOC_EQ(tmp, "MSM8230AB",      "400",       SOC_SNAPD_MSM8230AB,      soc, 28)
+  SOC_EQ(tmp, "MSM8626",        "400",       SOC_SNAPD_MSM8626,        soc, 28)
+  SOC_EQ(tmp, "MSM8630",        "400",       SOC_SNAPD_MSM8630,        soc, 28)
+  SOC_EQ(tmp, "MSM8630AB",      "400",       SOC_SNAPD_MSM8630AB,      soc, 28)
+  SOC_EQ(tmp, "MSM8930",        "400",       SOC_SNAPD_MSM8930,        soc, 28)
+  SOC_EQ(tmp, "MSM8930AB",      "400",       SOC_SNAPD_MSM8930AB,      soc, 28)
+  SOC_EQ(tmp, "MSM8916",        "410 / 412", SOC_SNAPD_MSM8916,        soc, 28)
+  SOC_EQ(tmp, "MSM8929",        "415",       SOC_SNAPD_MSM8929,        soc, 28)
+  SOC_EQ(tmp, "MSM8917",        "425",       SOC_SNAPD_MSM8917,        soc, 28)
+  SOC_EQ(tmp, "MSM8920",        "427",       SOC_SNAPD_MSM8920,        soc, 28)
+  SOC_EQ(tmp, "SDM429",         "429",       SOC_SNAPD_SDM429,         soc, 12)
+  SOC_EQ(tmp, "MSM8937",        "430",       SOC_SNAPD_MSM8937,        soc, 28)
+  SOC_EQ(tmp, "MSM8940",        "435",       SOC_SNAPD_MSM8940,        soc, 28)
+  SOC_EQ(tmp, "SDM439",         "439",       SOC_SNAPD_SDM439,         soc, 12)
+  SOC_EQ(tmp, "SDM450",         "450",       SOC_SNAPD_SDM450,         soc, 14)
+  SOC_EQ(tmp, "SM4250-AA",      "460",       SOC_SNAPD_SM4250_AA,      soc, 11)
+  // Snapdragon 6XX //
+  SOC_EQ(tmp, "APQ8064T",       "600",       SOC_SNAPD_APQ8064T,       soc, 28)
+  SOC_EQ(tmp, "APQ8064M",       "600",       SOC_SNAPD_APQ8064M,       soc, 28)
+  SOC_EQ(tmp, "MSM8936",        "610",       SOC_SNAPD_MSM8936,        soc, 28)
+  SOC_EQ(tmp, "MSM8939",        "615 / 616", SOC_SNAPD_MSM8939,        soc, 28)
+  SOC_EQ(tmp, "MSM8952",        "617",       SOC_SNAPD_MSM8952,        soc, 28)
+  SOC_EQ(tmp, "MSM8953",        "625",       SOC_SNAPD_MSM8953,        soc, 14)
+  SOC_EQ(tmp, "MSM8953 PRO",    "626",       SOC_SNAPD_MSM8953_PRO,    soc, 14)
+  SOC_EQ(tmp, "SDM630",         "630",       SOC_SNAPD_SDM630,         soc, 14)
+  SOC_EQ(tmp, "SDM632",         "632",       SOC_SNAPD_SDM632,         soc, 14)
+  SOC_EQ(tmp, "SDM636",         "636",       SOC_SNAPD_SDM636,         soc, 14)
+  SOC_EQ(tmp, "MSM8956",        "650",       SOC_SNAPD_MSM8956,        soc, 28)
+  SOC_EQ(tmp, "MSM8976",        "652",       SOC_SNAPD_MSM8976,        soc, 28)
+  SOC_EQ(tmp, "MSM8976 PRO",    "653",       SOC_SNAPD_MSM8976_PRO,    soc, 28)
+  SOC_EQ(tmp, "SDM660",         "660",       SOC_SNAPD_SDM660,         soc, 14)
+  SOC_EQ(tmp, "SM6115",         "662",       SOC_SNAPD_SM6115,         soc, 11)
+  SOC_EQ(tmp, "SM6125",         "665",       SOC_SNAPD_SM6125,         soc, 11)
+  SOC_EQ(tmp, "SDM670",         "670",       SOC_SNAPD_SDM670,         soc, 10)
+  SOC_EQ(tmp, "SM6150",         "675",       SOC_SNAPD_SM6150,         soc, 11)
+  SOC_EQ(tmp, "SM6350",         "690",       SOC_SNAPD_SM6350,         soc,  8)
+  // Snapdragon 7XX //
+  SOC_EQ(tmp, "SDM710",         "710",       SOC_SNAPD_SDM710,         soc, 10)
+  SOC_EQ(tmp, "SDM712",         "712",       SOC_SNAPD_SDM712,         soc, 10)
+  SOC_EQ(tmp, "SM7125",         "720G",      SOC_SNAPD_SM7125,         soc,  8)
+  SOC_EQ(tmp, "SM7150-AA",      "730",       SOC_SNAPD_SM7150_AA,      soc,  8)
+  SOC_EQ(tmp, "SM7150-AB",      "730G",      SOC_SNAPD_SM7150_AB,      soc,  8)
+  SOC_EQ(tmp, "SM7150-AC",      "732G",      SOC_SNAPD_SM7150_AC,      soc,  8)
+  SOC_EQ(tmp, "SM7225",         "750G",      SOC_SNAPD_SM7225,         soc,  8)
+  SOC_EQ(tmp, "SM7250-AA",      "765",       SOC_SNAPD_SM7250_AA,      soc,  7)
+  SOC_EQ(tmp, "SM7250-AB",      "765G",      SOC_SNAPD_SM7250_AB,      soc,  7)
+  SOC_EQ(tmp, "SM7250-AC",      "768G",      SOC_SNAPD_SM7250_AC,      soc,  7)
+  // Snapdragon 8XX //
+  SOC_EQ(tmp, "MSM8974AA",      "800",       SOC_SNAPD_MSM8974AA,      soc, 28)
+  SOC_EQ(tmp, "MSM8974AB",      "800",       SOC_SNAPD_MSM8974AB,      soc, 28)
+  SOC_EQ(tmp, "MSM8974AC",      "800",       SOC_SNAPD_MSM8974AC,      soc, 28)
+  SOC_EQ(tmp, "MSM8974PRO-AB",  "801",       SOC_SNAPD_MSM8974PRO_AB,  soc, 28)
+  SOC_EQ(tmp, "MSM8974PRO-AC",  "801",       SOC_SNAPD_MSM8974PRO_AC,  soc, 28)
+  SOC_EQ(tmp, "APQ8084",        "805",       SOC_SNAPD_APQ8084,        soc, 28)
+  SOC_EQ(tmp, "MSM8992",        "808",       SOC_SNAPD_MSM8992,        soc, 20)
+  SOC_EQ(tmp, "MSM8994",        "810",       SOC_SNAPD_MSM8994,        soc, 20)
+  SOC_EQ(tmp, "MSM8996",        "820",       SOC_SNAPD_MSM8996,        soc, 14)
+  SOC_EQ(tmp, "MSM8996 PRO A",  "821",       SOC_SNAPD_MSM8996_PRO_A,  soc, 14)
+  SOC_EQ(tmp, "MSM8998",        "835",       SOC_SNAPD_MSM8998,        soc, 10)
+  SOC_EQ(tmp, "APQ8098",        "835",       SOC_SNAPD_APQ8098,        soc, 10)
+  SOC_EQ(tmp, "SDM845",         "845",       SOC_SNAPD_SDM845,         soc, 10)
+  SOC_EQ(tmp, "SDM850",         "850",       SOC_SNAPD_SDM850,         soc, 10)
+  SOC_EQ(tmp, "SM8150",         "855",       SOC_SNAPD_SM8150,         soc,  7)
+  SOC_EQ(tmp, "SM8150-AC",      "855+",      SOC_SNAPD_SM8150_AC,      soc,  7)
+  SOC_EQ(tmp, "SM8250",         "865",       SOC_SNAPD_SM8250,         soc,  7)
+  SOC_EQ(tmp, "SM8250-AB",      "865+",      SOC_SNAPD_SM8250_AB,      soc,  7)
+  SOC_EQ(tmp, "SM8350",         "888",       SOC_SNAPD_SM8350,         soc,  5)
+  SOC_END
+}
+
+bool match_special(char* soc_name, struct system_on_chip* soc) {
+  char* tmp;
+
+  // Xiaomi hides Redmi Note 8/8T under "Qualcomm Technologies, Inc TRINKET"
+  if((tmp = strstr(soc_name, "TRINKET")) != NULL) {
+    fill_soc(soc, "665", SOC_SNAPD_SM6125, 11);
+    return true;
+  }
+  
+  return false;  
+}
+
+struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
+  char* raw_name = soc->raw_name;
+  
+  if (match_qualcomm(raw_name, soc))
+    return soc;
+  
+  if(match_mediatek(raw_name, soc))
+    return soc;
+  
+  if(match_exynos(raw_name, soc))
+    return soc;
+  
+  if(match_hisilicon(raw_name, soc))
+    return soc;
+  
+  if(match_broadcom(raw_name, soc))
+    return soc;
+  
+  match_special(raw_name, soc);  
+  
+  return soc;
+}
+
+#ifdef __ANDROID__
+#include <sys/system_properties.h>
+
+static inline int android_property_get(const char* key, char* value) {
+  return __system_property_get(key, value);
+}
+
+struct system_on_chip* guess_soc_from_android(struct system_on_chip* soc) {
+  char tmp[100];
+  int property_len = 0;
+  
+  property_len = android_property_get("ro.mediatek.platform", (char *) &tmp);
+  if(property_len > 0) {
+    soc->raw_name = malloc(sizeof(char) * (property_len + 1));
+    strncpy(soc->raw_name, tmp, property_len + 1);
+    soc->raw_name[property_len] = '\0';
+    soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+    return parse_soc_from_string(soc);
+  }
+  
+  property_len = android_property_get("ro.product.board", (char *) &tmp);
+  if(property_len > 0) {    
+    soc->raw_name = malloc(sizeof(char) * (property_len + 1));
+    strncpy(soc->raw_name, tmp, property_len + 1);
+    soc->raw_name[property_len] = '\0';
+    soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+    return parse_soc_from_string(soc);
+  }    
+  
+  return soc;
+}
+#endif
+
+struct system_on_chip* guess_soc_from_cpuinfo(struct system_on_chip* soc) {
+  char* tmp = get_hardware_from_cpuinfo(&strlen);
+  
+  if(tmp != NULL) {
+    soc->raw_name = tmp;
+    return parse_soc_from_string(soc);
+  }
+  
+  return soc;
+}
+
+struct system_on_chip* get_soc() {
+  struct system_on_chip* soc = malloc(sizeof(struct system_on_chip));
+  soc->raw_name = NULL;
+  soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+  soc->process = UNKNOWN;
+  
+  soc = guess_soc_from_cpuinfo(soc);
+  if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+    if(soc->raw_name != NULL)
+      printWarn("SoC detection failed using /proc/cpuinfo: Found '%s' string", soc->raw_name);   
+    else
+      printWarn("SoC detection failed using /proc/cpuinfo: No string found");
+#ifdef __ANDROID__
+    soc = guess_soc_from_android(soc);
+    if(soc->raw_name == NULL)
+      printWarn("SoC detection failed using Android: No string found");
+    else if(soc->soc_vendor == SOC_VENDOR_UNKNOWN)
+      printWarn("SoC detection failed using Android: Found '%s' string", soc->raw_name);   
+#endif
+  }
+
+  if(soc->raw_name == NULL) {
+    soc->raw_name = malloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
+    snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+  }
+  
+  return soc;    
+}
+
+char* get_soc_name(struct system_on_chip* soc) {
+  if(soc->soc_vendor == SOC_VENDOR_UNKNOWN)
+    return soc->raw_name;
+  return soc->soc_name;
+}
+
+VENDOR get_soc_vendor(struct system_on_chip* soc) {
+  return soc->soc_vendor;
+}
+
+char* get_str_process(struct system_on_chip* soc) {
+  char* str;
+  
+  if(soc->process == UNKNOWN) {
+    str = malloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
+    snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+  }
+  else {
+    str = malloc(sizeof(char) * 5);
+    memset(str, 0, sizeof(char) * 5);
+    snprintf(str, 5, "%dnm", soc->process);    
+  }
+  return str;
+}
+
--- a/src/arm/soc.h
+++ b/src/arm/soc.h
@@ -0,0 +1,31 @@
+#ifndef __SOC__
+#define __SOC__
+
+#include "../common/cpu.h"
+#include <stdint.h>
+
+typedef int32_t SOC;
+
+enum {
+  SOC_VENDOR_UNKNOWN,
+  SOC_VENDOR_SNAPDRAGON,
+  SOC_VENDOR_MEDIATEK,
+  SOC_VENDOR_EXYNOS,
+  SOC_VENDOR_KIRIN,
+  SOC_VENDOR_BROADCOM
+};
+
+struct system_on_chip {
+  SOC soc_model;
+  VENDOR soc_vendor;
+  int32_t process;
+  char* soc_name;
+  char* raw_name;    
+};
+
+struct system_on_chip* get_soc();
+char* get_soc_name(struct system_on_chip* soc);
+VENDOR get_soc_vendor(struct system_on_chip* soc);
+char* get_str_process(struct system_on_chip* soc);
+
+#endif
--- a/src/arm/socs.h
+++ b/src/arm/socs.h
@@ -0,0 +1,264 @@
+#ifndef __SOCS__
+#define __SOCS__
+
+#include "soc.h"
+
+// List of supported SOCs
+enum {
+  // Broadcom //
+  SOC_BCM_2835,
+  SOC_BCM_2836,
+  SOC_BCM_2837,
+  SOC_BCM_2837B0,
+  SOC_BCM_2711,
+  SOC_BCM_21553,
+  SOC_BCM_21553T,
+  SOC_BCM_21663,
+  SOC_BCM_21664,
+  SOC_BCM_28155,
+  SOC_BCM_23550,
+  SOC_BCM_28145,
+  SOC_BCM_2157,
+  SOC_BCM_21654,
+  // Hisilicon //
+  SOC_HISILICON_3620,
+  SOC_HISILICON_3630,
+  SOC_HISILICON_3650,
+  SOC_HISILICON_3660,
+  SOC_HISILICON_3670,
+  SOC_HISILICON_3680,
+  SOC_HISILICON_3690,
+  // Exynos //
+  SOC_EXYNOS_3475,
+  SOC_EXYNOS_4210,
+  SOC_EXYNOS_4212,
+  SOC_EXYNOS_4412,
+  SOC_EXYNOS_5250,
+  SOC_EXYNOS_5410,
+  SOC_EXYNOS_5420,
+  SOC_EXYNOS_5422,
+  SOC_EXYNOS_5430,
+  SOC_EXYNOS_5433,
+  SOC_EXYNOS_5260,
+  SOC_EXYNOS_7270,
+  SOC_EXYNOS_7420,
+  SOC_EXYNOS_7570,
+  SOC_EXYNOS_7870,
+  SOC_EXYNOS_7872,
+  SOC_EXYNOS_7880,
+  SOC_EXYNOS_7884,
+  SOC_EXYNOS_7885,
+  SOC_EXYNOS_7904,
+  SOC_EXYNOS_8890,
+  SOC_EXYNOS_8895,
+  SOC_EXYNOS_9110,
+  SOC_EXYNOS_9609,
+  SOC_EXYNOS_9610,
+  SOC_EXYNOS_9611,
+  SOC_EXYNOS_9810,
+  SOC_EXYNOS_9820,
+  SOC_EXYNOS_9825,
+  SOC_EXYNOS_1080,
+  SOC_EXYNOS_990,
+  SOC_EXYNOS_980,
+  SOC_EXYNOS_880,
+  // Mediatek //
+  SOC_MTK_MT6889,
+  SOC_MTK_MT6885Z,
+  SOC_MTK_MT6853,
+  SOC_MTK_MT6873,
+  SOC_MTK_MT6875,
+  SOC_MTK_MT6761D,
+  SOC_MTK_MT6761,
+  SOC_MTK_MT6762D,
+  SOC_MTK_MT6755,
+  SOC_MTK_MT6755M,
+  SOC_MTK_MT6755T,
+  SOC_MTK_MT6757,
+  SOC_MTK_MT6762,
+  SOC_MTK_MT6763V,
+  SOC_MTK_MT6763T,
+  SOC_MTK_MT6757CD,
+  SOC_MTK_MT6758,
+  SOC_MTK_MT6765,
+  SOC_MTK_MT6771,
+  SOC_MTK_MT6768,
+  SOC_MTK_MT6771T,
+  SOC_MTK_MT6771V,
+  SOC_MTK_MT6779,
+  SOC_MTK_MT6795,
+  SOC_MTK_MT6795T,
+  SOC_MTK_MT6797,
+  SOC_MTK_MT6797M,
+  SOC_MTK_MT6797D,
+  SOC_MTK_MT6797T,
+  SOC_MTK_MT6797X,
+  SOC_MTK_MT6799,
+  SOC_MTK_MT6515,
+  SOC_MTK_MT6516,
+  SOC_MTK_MT6517,
+  SOC_MTK_MT6572,
+  SOC_MTK_MT6572M,
+  SOC_MTK_MT6573,
+  SOC_MTK_MT6575,
+  SOC_MTK_MT6577,
+  SOC_MTK_MT6577T,
+  SOC_MTK_MT6580,
+  SOC_MTK_MT6582,
+  SOC_MTK_MT6582M,
+  SOC_MTK_MT6589,
+  SOC_MTK_MT6589T,
+  SOC_MTK_MT6592,
+  SOC_MTK_MT6595,
+  SOC_MTK_MT6732,
+  SOC_MTK_MT6735,
+  SOC_MTK_MT6735M,
+  SOC_MTK_MT6735P,
+  SOC_MTK_MT6737,
+  SOC_MTK_MT6737M,
+  SOC_MTK_MT6737T,
+  SOC_MTK_MT6739,
+  SOC_MTK_MT6750,
+  SOC_MTK_MT6750S,
+  SOC_MTK_MT6750T,
+  SOC_MTK_MT6752,
+  SOC_MTK_MT6753,
+  SOC_MTK_MT6850,
+  SOC_MTK_MT8121,
+  SOC_MTK_MT8125,
+  SOC_MTK_MT8127,
+  SOC_MTK_MT8135,
+  SOC_MTK_MT8163A,
+  SOC_MTK_MT8163B,
+  SOC_MTK_MT8167B,
+  SOC_MTK_MT8173,
+  SOC_MTK_MT8176,
+  SOC_MTK_MT8321,
+  SOC_MTK_MT8382,
+  SOC_MTK_MT8581,
+  SOC_MTK_MT8735,
+  SOC_MTK_MT8765B,
+  SOC_MTK_MT8783,
+  // Snapdragon //
+  SOC_SNAPD_QSD8650,
+  SOC_SNAPD_QSD8250,
+  SOC_SNAPD_MSM7627,
+  SOC_SNAPD_MSM7227,
+  SOC_SNAPD_MSM7627A,
+  SOC_SNAPD_MSM7227A,
+  SOC_SNAPD_MSM7625,
+  SOC_SNAPD_MSM7225,
+  SOC_SNAPD_MSM7625A,
+  SOC_SNAPD_MSM7225A,
+  SOC_SNAPD_MSM8655,
+  SOC_SNAPD_MSM8255,
+  SOC_SNAPD_APQ8055,
+  SOC_SNAPD_MSM7630,
+  SOC_SNAPD_MSM7230,
+  SOC_SNAPD_MSM8660,
+  SOC_SNAPD_MSM8260,
+  SOC_SNAPD_APQ8060,
+  SOC_SNAPD_MSM8225,
+  SOC_SNAPD_MSM8625,
+  SOC_SNAPD_APQ8060A,
+  SOC_SNAPD_MSM8960,
+  SOC_SNAPD_MSM8260A,
+  SOC_SNAPD_MSM8627,
+  SOC_SNAPD_MSM8227,
+  SOC_SNAPD_APQ8064,
+  SOC_SNAPD_MSM8960T,
+  SOC_SNAPD_MSM8110,
+  SOC_SNAPD_MSM8210,
+  SOC_SNAPD_MSM8610,
+  SOC_SNAPD_MSM8112,
+  SOC_SNAPD_MSM8212,
+  SOC_SNAPD_MSM8612,
+  SOC_SNAPD_MSM8225Q,
+  SOC_SNAPD_MSM8625Q,
+  SOC_SNAPD_MSM8208,
+  SOC_SNAPD_MSM8905,
+  SOC_SNAPD_MSM8909,
+  SOC_SNAPD_QM215,
+  SOC_SNAPD_APQ8028,
+  SOC_SNAPD_MSM8228,
+  SOC_SNAPD_MSM8628,
+  SOC_SNAPD_MSM8928,
+  SOC_SNAPD_MSM8926,
+  SOC_SNAPD_APQ8030AB,
+  SOC_SNAPD_MSM8226,
+  SOC_SNAPD_MSM8230AB,
+  SOC_SNAPD_MSM8626,
+  SOC_SNAPD_MSM8630,
+  SOC_SNAPD_MSM8630AB,
+  SOC_SNAPD_MSM8930,
+  SOC_SNAPD_MSM8930AB,
+  SOC_SNAPD_MSM8916,
+  SOC_SNAPD_MSM8929,
+  SOC_SNAPD_MSM8917,
+  SOC_SNAPD_MSM8920,
+  SOC_SNAPD_SDM429,
+  SOC_SNAPD_MSM8937,
+  SOC_SNAPD_MSM8940,
+  SOC_SNAPD_SDM439,
+  SOC_SNAPD_SDM450,
+  SOC_SNAPD_SM4250_AA,
+  SOC_SNAPD_APQ8064T,
+  SOC_SNAPD_APQ8064M,
+  SOC_SNAPD_MSM8936,
+  SOC_SNAPD_MSM8939,
+  SOC_SNAPD_MSM8952,
+  SOC_SNAPD_MSM8953,
+  SOC_SNAPD_MSM8953_PRO,
+  SOC_SNAPD_SDM630,
+  SOC_SNAPD_SDM632,
+  SOC_SNAPD_SDM636,
+  SOC_SNAPD_MSM8956,
+  SOC_SNAPD_MSM8976,
+  SOC_SNAPD_MSM8976_PRO,
+  SOC_SNAPD_SDM660,
+  SOC_SNAPD_SM6115,
+  SOC_SNAPD_SM6125,
+  SOC_SNAPD_SDM670,
+  SOC_SNAPD_SM6150,
+  SOC_SNAPD_SM6350,
+  SOC_SNAPD_SDM710,
+  SOC_SNAPD_SDM712,
+  SOC_SNAPD_SM7125,
+  SOC_SNAPD_SM7150_AA,
+  SOC_SNAPD_SM7150_AB,
+  SOC_SNAPD_SM7150_AC,
+  SOC_SNAPD_SM7225,
+  SOC_SNAPD_SM7250_AA,
+  SOC_SNAPD_SM7250_AB,
+  SOC_SNAPD_SM7250_AC,
+  SOC_SNAPD_MSM8974AA,
+  SOC_SNAPD_MSM8974AB,
+  SOC_SNAPD_MSM8974AC,
+  SOC_SNAPD_MSM8974PRO_AB,
+  SOC_SNAPD_MSM8974PRO_AC,
+  SOC_SNAPD_APQ8084,
+  SOC_SNAPD_MSM8992,
+  SOC_SNAPD_MSM8994,
+  SOC_SNAPD_MSM8996,
+  SOC_SNAPD_MSM8996_PRO_A,
+  SOC_SNAPD_MSM8998,
+  SOC_SNAPD_APQ8098,
+  SOC_SNAPD_SDM845,
+  SOC_SNAPD_SDM850,
+  SOC_SNAPD_SM8150,
+  SOC_SNAPD_SM8150_AC,
+  SOC_SNAPD_SM8250,
+  SOC_SNAPD_SM8250_AB,
+  SOC_SNAPD_SM8350,
+};
+
+inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
+  if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_21654) return SOC_VENDOR_BROADCOM;
+  else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_3690) return SOC_VENDOR_KIRIN;
+  else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
+  else if(soc >= SOC_MTK_MT6889 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
+  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8350) return SOC_VENDOR_SNAPDRAGON;
+  return SOC_VENDOR_UNKNOWN;  
+}
+
+#endif
--- a/src/arm/socs_generation.sh
+++ b/src/arm/socs_generation.sh
@@ -0,0 +1,23 @@
+#!/bin/bash -u
+
+SOC_LIST="$(grep SOC_EQ soc.c | grep -v '//SOC_EQ' | grep -v 'define' | cut -d',' -f2 | sed 's/"//')"
+
+IFS=$'"'
+
+for soc in $SOC_LIST
+do
+  # CLEAN
+  soc=$(echo $soc | tr -d '\n')
+  soc="${soc:1}"
+  
+  # REPLACE
+  soc=$(echo $soc | sed "s/BCM/BCM_/g")
+  soc=$(echo $soc | sed "s/universal/EXYNOS_/g")
+  soc=$(echo $soc | sed "s/Hi/HISILICON_/g")
+  soc=$(echo $soc | sed "s/^MSM/SNAPD_MSM/g" | sed "s/SDM/SNAPD_SDM/g" | sed "s/APQ/SNAPD_APQ/g" | sed "s/^SM/SNAPD_SM/g" | sed "s/QM/SNAPD_QM/g" | sed "s/QSD/SNAPD_QSD/g")
+  soc=$(echo $soc | sed "s/MT/MTK_MT/g")
+  soc=$(echo $soc | sed "s/-/_/g" | sed "s/ /_/g")
+  echo '  SOC_'"$soc"','
+done
+
+unset IFS
--- a/src/arm/uarch.c
+++ b/src/arm/uarch.c
@@ -0,0 +1,282 @@
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <inttypes.h>
+
+#include "uarch.h"
+#include "../common/global.h"
+
+#define STRING_UNKNOWN    "Unknown"
+
+// Data not available
+#define NA                   -1
+
+typedef uint32_t MICROARCH;
+typedef uint32_t ISA;
+
+struct uarch {
+  MICROARCH uarch;
+  ISA isa;
+  char* uarch_str;
+  char* isa_str;
+  // int32_t process; process depends on SoC
+};
+
+enum {
+  ISA_ARMv7_A,
+  ISA_ARMv8_A,
+  ISA_ARMv8_A_AArch32,
+  ISA_ARMv8_1_A,
+  ISA_ARMv8_2_A,
+  ISA_ARMv8_3_A,
+};
+
+enum {
+  UARCH_UNKNOWN,
+  // ARM
+  UARCH_ARM7,
+  UARCH_ARM9,  
+  UARCH_ARM11,       // ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore.
+  UARCH_CORTEX_A5,  
+  UARCH_CORTEX_A7,  
+  UARCH_CORTEX_A8,    
+  UARCH_CORTEX_A9,    
+  UARCH_CORTEX_A12,    
+  UARCH_CORTEX_A15,    
+  UARCH_CORTEX_A17,    
+  UARCH_CORTEX_A32,    
+  UARCH_CORTEX_A35,    
+  UARCH_CORTEX_A53,    
+  UARCH_CORTEX_A55r0, // ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+).
+  UARCH_CORTEX_A55, 
+  UARCH_CORTEX_A57, 
+  UARCH_CORTEX_A65, 
+  UARCH_CORTEX_A72, 
+  UARCH_CORTEX_A73, 
+  UARCH_CORTEX_A75, 
+  UARCH_CORTEX_A76,
+  UARCH_CORTEX_A77,
+  UARCH_CORTEX_A78, 
+  UARCH_NEOVERSE_N1,
+  UARCH_NEOVERSE_E1,
+  UARCH_SCORPION,
+  UARCH_KRAIT,
+  UARCH_KYRO,
+  UARCH_FALKOR,
+  UARCH_SAPHIRA,
+  UARCH_DENVER,
+  UARCH_DENVER2,
+  UARCH_CARMEL,
+  // SAMSUNG
+  UARCH_EXYNOS_M1,  // Samsung Exynos M1 (Exynos 8890 big cores)
+  UARCH_EXYNOS_M2,  // Samsung Exynos M2 (Exynos 8895 big cores)
+  UARCH_EXYNOS_M3,  // Samsung Exynos M3 (Exynos 9810 big cores)
+  UARCH_EXYNOS_M4,  // Samsung Exynos M4 (Exynos 9820 big cores)
+  UARCH_EXYNOS_M5,  // Samsung Exynos M5 (Exynos 9830 big cores)
+  // APPLE
+  UARCH_SWIFT,      // Apple A6 and A6X processors.
+  UARCH_CYCLONE,    // Apple A7 processor.
+  UARCH_TYPHOON,    // Apple A8 and A8X processor
+  UARCH_TWISTER,    // Apple A9 and A9X processor.
+  UARCH_HURRICANE,  // Apple A10 and A10X processor.
+  UARCH_MONSOON,    // Apple A11 processor (big cores).
+  UARCH_MISTRAL,    // Apple A11 processor (little cores).
+  UARCH_VORTEX,     // Apple A12 processor (big cores).
+  UARCH_TEMPEST,    // Apple A12 processor (big cores).
+  UARCH_LIGHTNING,  // Apple A13 processor (big cores).
+  UARCH_THUNDER,    // Apple A13 processor (little cores).
+  // CAVIUM
+  UARCH_THUNDERX,   // Cavium ThunderX
+  UARCH_THUNDERX2,  //  Cavium ThunderX2 (originally Broadcom Vulkan).
+  // MARVELL
+  UARCH_PJ4,
+  UARCH_BRAHMA_B15,
+  UARCH_BRAHMA_B53,
+  UARCH_XGENE,        // Applied Micro X-Gene.
+  UARCH_TAISHAN_V110  // HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors).
+};
+
+static const ISA isas_uarch[] = {
+  [UARCH_CORTEX_A5]    = ISA_ARMv7_A,
+  [UARCH_CORTEX_A7]    = ISA_ARMv7_A,
+  [UARCH_CORTEX_A8]    = ISA_ARMv7_A,
+  [UARCH_CORTEX_A9]    = ISA_ARMv7_A,
+  [UARCH_CORTEX_A12]   = ISA_ARMv7_A,
+  [UARCH_CORTEX_A15]   = ISA_ARMv7_A,
+  [UARCH_CORTEX_A17]   = ISA_ARMv7_A,
+  [UARCH_CORTEX_A32]   = ISA_ARMv8_A_AArch32,
+  [UARCH_CORTEX_A35]   = ISA_ARMv8_A,
+  [UARCH_CORTEX_A53]   = ISA_ARMv8_A,  
+  [UARCH_CORTEX_A55r0] = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A55]   = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A57]   = ISA_ARMv8_A,
+  [UARCH_CORTEX_A65]   = ISA_ARMv8_2_A,  
+  [UARCH_CORTEX_A72]   = ISA_ARMv8_A,
+  [UARCH_CORTEX_A73]   = ISA_ARMv8_A,
+  [UARCH_CORTEX_A75]   = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A76]   = ISA_ARMv8_2_A,  
+  [UARCH_CORTEX_A77]   = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A78]   = ISA_ARMv8_2_A,
+  [UARCH_NEOVERSE_N1]  = ISA_ARMv8_2_A,
+  [UARCH_NEOVERSE_E1]  = ISA_ARMv8_2_A,
+  [UARCH_BRAHMA_B15]   = ISA_ARMv7_A,   // Same as Cortex-A15
+  [UARCH_BRAHMA_B53]   = ISA_ARMv8_A,   // Same as Cortex-A53
+  [UARCH_THUNDERX]     = ISA_ARMv8_A,
+  [UARCH_THUNDERX2]    = ISA_ARMv8_1_A,
+  [UARCH_TAISHAN_V110] = ISA_ARMv8_2_A,
+  [UARCH_DENVER]       = ISA_ARMv8_A,
+  [UARCH_DENVER2]      = ISA_ARMv8_A,
+  [UARCH_CARMEL]       = ISA_ARMv8_A,
+  [UARCH_XGENE]        = ISA_ARMv8_A, // https://en.wikichip.org/wiki/apm/x-gene
+  [UARCH_SCORPION]     = ISA_ARMv7_A, // https://www.geektopia.es/es/product/qualcomm/snapdragon-s3-apq8060/
+  [UARCH_KRAIT]        = ISA_ARMv7_A,
+  [UARCH_KYRO]         = ISA_ARMv8_A,
+  [UARCH_FALKOR]       = ISA_ARMv8_A,
+  [UARCH_SAPHIRA]      = ISA_ARMv8_3_A,
+  [UARCH_EXYNOS_M1]    = ISA_ARMv8_A,
+  [UARCH_EXYNOS_M2]    = ISA_ARMv8_A,
+  [UARCH_EXYNOS_M3]    = ISA_ARMv8_A,
+  [UARCH_EXYNOS_M4]    = ISA_ARMv8_2_A,
+  [UARCH_EXYNOS_M5]    = ISA_ARMv8_2_A,
+  [UARCH_PJ4]          = ISA_ARMv7_A,
+};
+
+static char* isas_string[] = {
+  [ISA_ARMv7_A] = "ARMv7",
+  [ISA_ARMv8_A] = "ARMv8",
+  [ISA_ARMv8_A_AArch32] = "ARMv8 AArch32",
+  [ISA_ARMv8_1_A] = "ARMv8.1",
+  [ISA_ARMv8_2_A] = "ARMv8.2",
+  [ISA_ARMv8_3_A] = "ARMv8.3",
+};
+
+#define UARCH_START if (false) {}
+#define CHECK_UARCH(arch, cpu, im_, p_, v_, r_, str, uarch, vendor) \
+   else if (im_ == im && p_ == p && (v_ == NA || v_ == v) && (r_ == NA || r_ == r)) fill_uarch(arch, cpu, str, uarch, vendor);
+#define UARCH_END else { printBug("Unknown microarchitecture detected: IM=0x%.8X P=0x%.8X V=0x%.8X R=0x%.8X", im, p, v, r); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
+   
+void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
+  arch->uarch = u;  
+  arch->isa = isas_uarch[arch->uarch];
+  cpu->cpu_vendor = vendor;
+  
+  arch->uarch_str = malloc(sizeof(char) * (strlen(str)+1));
+  strcpy(arch->uarch_str, str);
+  
+  arch->isa_str = malloc(sizeof(char) * (strlen(isas_string[arch->isa])+1));
+  strcpy(arch->isa_str, isas_string[arch->isa]);  
+}   
+
+/*
+ * Codes are based on pytorch/cpuinfo, more precisely:
+ * - https://github.com/pytorch/cpuinfo/blob/master/src/arm/uarch.c
+ * Other sources:
+ * - https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/asm/cputype.h
+ * - https://elixir.bootlin.com/linux/latest/source/arch/arm/include/asm/cputype.h
+ */
+struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
+  struct uarch* arch = malloc(sizeof(struct uarch));
+  uint32_t im = midr_get_implementer(midr);
+  uint32_t p = midr_get_part(midr);
+  uint32_t v = midr_get_variant(midr);
+  uint32_t r = midr_get_revision(midr);
+  
+  // ----------------------------------------------------------------------- //
+  // IM: Implementer                                                         //
+  // P:  Part                                                                //
+  // V:  Variant                                                             //
+  // R:  Revision                                                            //
+  // ----------------------------------------------------------------------- //
+  //                     IM   P      V   R                                   //
+  UARCH_START  
+  CHECK_UARCH(arch, cpu, 'A', 0xC05, NA, NA, "Cortex-A5",             UARCH_CORTEX_A5,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC07, NA, NA, "Cortex-A7",             UARCH_CORTEX_A7,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC08, NA, NA, "Cortex-A8",             UARCH_CORTEX_A8,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC09, NA, NA, "Cortex-A9",             UARCH_CORTEX_A9,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC0C, NA, NA, "Cortex-A12",            UARCH_CORTEX_A12,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC0E, NA, NA, "Cortex-A17",            UARCH_CORTEX_A17,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC0D, NA, NA, "Cortex-A12",            UARCH_CORTEX_A12,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xC0F, NA, NA, "Cortex-A15",            UARCH_CORTEX_A15,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD01, NA, NA, "Cortex-A32",            UARCH_CORTEX_A32,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD03, NA, NA, "Cortex-A53",            UARCH_CORTEX_A53,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD04, NA, NA, "Cortex-A35",            UARCH_CORTEX_A35,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD05, NA,  0, "Cortex-A55",            UARCH_CORTEX_A55r0, CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD05, NA, NA, "Cortex-A55",            UARCH_CORTEX_A55,   CPU_VENDOR_ARM)  
+  CHECK_UARCH(arch, cpu, 'A', 0xD06, NA, NA, "Cortex-A65",            UARCH_CORTEX_A65,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD07, NA, NA, "Cortex-A57",            UARCH_CORTEX_A57,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD08, NA, NA, "Cortex-A72",            UARCH_CORTEX_A72,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD09, NA, NA, "Cortex-A73",            UARCH_CORTEX_A73,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD0A, NA, NA, "Cortex-A75",            UARCH_CORTEX_A75,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD0B, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD0C, NA, NA, "Neoverse N1",           UARCH_NEOVERSE_N1,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD0D, NA, NA, "Cortex-A77",            UARCH_CORTEX_A77,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD0E, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD41, NA, NA, "Cortex-A78",            UARCH_CORTEX_A78,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD4A, NA, NA, "Neoverse E1",           UARCH_NEOVERSE_E1,  CPU_VENDOR_ARM)
+     
+  CHECK_UARCH(arch, cpu, 'B', 0x00F, NA, NA, "Brahma B15",            UARCH_BRAHMA_B15,   CPU_VENDOR_BROADCOM)
+  CHECK_UARCH(arch, cpu, 'B', 0x100, NA, NA, "Brahma B53",            UARCH_BRAHMA_B53,   CPU_VENDOR_BROADCOM)
+  CHECK_UARCH(arch, cpu, 'B', 0x516, NA, NA, "ThunderX2",             UARCH_THUNDERX2,    CPU_VENDOR_CAVIUM)
+  
+  CHECK_UARCH(arch, cpu, 'C', 0x0A0, NA, NA, "ThunderX",              UARCH_THUNDERX,     CPU_VENDOR_CAVIUM)
+  CHECK_UARCH(arch, cpu, 'C', 0x0A1, NA, NA, "ThunderX 88XX",         UARCH_THUNDERX,     CPU_VENDOR_CAVIUM)
+  CHECK_UARCH(arch, cpu, 'C', 0x0A2, NA, NA, "ThunderX 81XX",         UARCH_THUNDERX,     CPU_VENDOR_CAVIUM)
+  CHECK_UARCH(arch, cpu, 'C', 0x0A3, NA, NA, "ThunderX 81XX",         UARCH_THUNDERX,     CPU_VENDOR_CAVIUM)
+  CHECK_UARCH(arch, cpu, 'C', 0x0AF, NA, NA, "ThunderX2 99XX",        UARCH_THUNDERX2,    CPU_VENDOR_CAVIUM)
+  
+  CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110",          UARCH_TAISHAN_V110, CPU_VENDOR_HUAWUEI) // Kunpeng 920 series
+  CHECK_UARCH(arch, cpu, 'H', 0xD40, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)     // Kirin 980 Big/Medium cores -> Cortex-A76
+  
+  CHECK_UARCH(arch, cpu, 'N', 0x000, NA, NA, "Denver",                UARCH_DENVER,       CPU_VENDOR_NVIDIA)
+  CHECK_UARCH(arch, cpu, 'N', 0x003, NA, NA, "Denver2",               UARCH_DENVER2,      CPU_VENDOR_NVIDIA)
+  CHECK_UARCH(arch, cpu, 'N', 0x004, NA, NA, "Carmel",                UARCH_CARMEL,       CPU_VENDOR_NVIDIA)
+  
+  CHECK_UARCH(arch, cpu, 'P', 0x000, NA, NA, "Xgene",                 UARCH_XGENE,        CPU_VENDOR_APM)
+  
+  CHECK_UARCH(arch, cpu, 'Q', 0x00F, NA, NA, "Scorpion",              UARCH_SCORPION,     CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x02D, NA, NA, "Scorpion",              UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x04D,  1,  0, "Krait 200",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x04D,  1,  4, "Krait 200",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x04D,  2,  0, "Krait 300",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x06F,  0,  1, "Krait 200",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x06F,  0,  2, "Krait 200",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x06F,  1,  0, "Krait 300",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x06F,  2,  0, "Krait 400",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM) // Snapdragon 800 MSMxxxx
+  CHECK_UARCH(arch, cpu, 'Q', 0x06F,  2,  1, "Krait 400",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM) // Snapdragon 801 MSMxxxxPRO
+  CHECK_UARCH(arch, cpu, 'Q', 0x06F,  3,  1, "Krait 450",             UARCH_KRAIT,        CPU_VENDOR_QUALCOMM)
+  CHECK_UARCH(arch, cpu, 'Q', 0x201, NA, NA, "Kryo Silver",           UARCH_KYRO,         CPU_VENDOR_QUALCOMM) // Qualcomm Snapdragon 821: Low-power Kryo "Silver"
+  CHECK_UARCH(arch, cpu, 'Q', 0x205, NA, NA, "Kryo Gold",             UARCH_KYRO,         CPU_VENDOR_QUALCOMM) // Qualcomm Snapdragon 820 & 821: High-performance Kryo "Gold"
+  CHECK_UARCH(arch, cpu, 'Q', 0x211, NA, NA, "Kryo Silver",           UARCH_KYRO,         CPU_VENDOR_QUALCOMM) // Qualcomm Snapdragon 820: Low-power Kryo "Silver"
+  CHECK_UARCH(arch, cpu, 'Q', 0x800, 10, NA, "Kryo 260 / 280 Gold",   UARCH_CORTEX_A73,   CPU_VENDOR_ARM)      // Kryo 260 / Kryo 280 "Gold"
+  CHECK_UARCH(arch, cpu, 'Q', 0x801, 10, NA, "Kryo 260 / 280 Silver", UARCH_CORTEX_A53,   CPU_VENDOR_ARM)      // Kryo 260 / 280 "Silver"
+  CHECK_UARCH(arch, cpu, 'Q', 0x802, NA, NA, "Kryo 385 Gold",         UARCH_CORTEX_A75,   CPU_VENDOR_ARM)      // High-performance Kryo 385 "Gold" -> Cortex-A75
+  CHECK_UARCH(arch, cpu, 'Q', 0x803, NA, NA, "Kryo 385 Silver",       UARCH_CORTEX_A55r0, CPU_VENDOR_ARM)      // Low-power Kryo 385 "Silver" -> Cortex-A55r0
+  CHECK_UARCH(arch, cpu, 'Q', 0x804, NA, NA, "Kryo 485 Gold",         UARCH_CORTEX_A76,   CPU_VENDOR_ARM)      // High-performance Kryo 485 "Gold" / "Gold Prime" -> Cortex-A76
+  CHECK_UARCH(arch, cpu, 'Q', 0x805, NA, NA, "Kryo 485 Silver",       UARCH_CORTEX_A55,   CPU_VENDOR_ARM)      // Low-performance Kryo 485 "Silver" -> Cortex-A55
+  CHECK_UARCH(arch, cpu, 'Q', 0xC00, NA, NA, "Falkor",                UARCH_FALKOR,       CPU_VENDOR_QUALCOMM)      
+  CHECK_UARCH(arch, cpu, 'Q', 0xC01, NA, NA, "Saphira",               UARCH_SAPHIRA,      CPU_VENDOR_QUALCOMM)     
+  
+  CHECK_UARCH(arch, cpu, 'S', 0x001, 1,  NA, "Exynos M1",             UARCH_EXYNOS_M1,    CPU_VENDOR_SAMSUNG)   // Exynos 8890
+  CHECK_UARCH(arch, cpu, 'S', 0x001, 4,  NA, "Exynos M2",             UARCH_EXYNOS_M2,    CPU_VENDOR_SAMSUNG)   // Exynos 8895
+  CHECK_UARCH(arch, cpu, 'S', 0x002, 1,  NA, "Exynos M3",             UARCH_EXYNOS_M3,    CPU_VENDOR_SAMSUNG)   // Exynos 9810
+  CHECK_UARCH(arch, cpu, 'S', 0x003, 1,  NA, "Exynos M4",             UARCH_EXYNOS_M4,    CPU_VENDOR_SAMSUNG)   // Exynos 9820
+  CHECK_UARCH(arch, cpu, 'S', 0x004, 1,  NA, "Exynos M5",             UARCH_EXYNOS_M5,    CPU_VENDOR_SAMSUNG)   // Exynos 9820 (this one looks wrong at uarch.c ...)
+            
+  CHECK_UARCH(arch, cpu, 'V', 0x581, NA, NA, "PJ4",                   UARCH_PJ4,          CPU_VENDOR_MARVELL)
+  CHECK_UARCH(arch, cpu, 'V', 0x584, NA, NA, "PJ4B-MP",               UARCH_PJ4,          CPU_VENDOR_MARVELL)
+  
+  UARCH_END
+  
+  return arch;
+}
+
+char* get_str_uarch(struct cpuInfo* cpu) {
+  return cpu->arch->uarch_str;    
+}
+
+void free_uarch_struct(struct uarch* arch) {    
+  free(arch->uarch_str);
+  free(arch);
+}
+
--- a/src/arm/uarch.h
+++ b/src/arm/uarch.h
@@ -0,0 +1,12 @@
+#ifndef __UARCH__
+#define __UARCH__
+
+#include <stdint.h>
+
+#include "midr.h"
+
+struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu);
+char* get_str_uarch(struct cpuInfo* cpu);
+void free_uarch_struct(struct uarch* arch);
+
+#endif
--- a/src/arm/udev.c
+++ b/src/arm/udev.c
@@ -0,0 +1,162 @@
+#include "udev.h"
+#include "midr.h"
+
+#define _PATH_CPUS_PRESENT           _PATH_SYS_SYSTEM _PATH_SYS_CPU "/present"
+#define _PATH_CPUINFO                "/proc/cpuinfo"
+//#define _PATH_CPUINFO                "cpuinfo_debug"
+
+#define CPUINFO_CPU_IMPLEMENTER_STR  "CPU implementer\t: "
+#define CPUINFO_CPU_ARCHITECTURE_STR "CPU architecture: "
+#define CPUINFO_CPU_VARIANT_STR      "CPU variant\t: "
+#define CPUINFO_CPU_PART_STR         "CPU part\t: "
+#define CPUINFO_CPU_REVISION_STR     "CPU revision\t: "
+#define CPUINFO_HARDWARE_STR         "Hardware\t: "
+
+#define CPUINFO_CPU_STRING "processor"
+
+// https://www.kernel.org/doc/html/latest/core-api/cpu_hotplug.html
+int get_ncores_from_cpuinfo() {
+  // Examples:
+  // 0-271
+  // 0-5
+  // 0-7
+  int filelen;
+  char* buf;
+  if((buf = read_file(_PATH_CPUS_PRESENT, &filelen)) == NULL) {
+    perror("open");
+    return UNKNOWN;    
+  }
+  
+  int ncores = 0;
+  char* tmp1 = strstr(buf, "-") + 1;
+  char* tmp2 = strstr(buf, "\n");
+  char ncores_str[filelen];
+  memset(ncores_str, 0, sizeof(char) * filelen);
+  memcpy(ncores_str, tmp1, tmp2-tmp1);
+  
+  char* end;
+  errno = 0;
+  ncores = strtol(ncores_str, &end, 10) + 1;  
+  if(errno != 0) {
+    perror("strtol");
+    return UNKNOWN;
+  }
+
+  free(buf);
+
+  return ncores;
+}
+
+long parse_cpuinfo_field(char* buf, char* field_str, int field_base) {
+  char* tmp = strstr(buf, field_str);
+  if(tmp == NULL) return -1;
+  tmp += strlen(field_str);
+
+  char* end;
+  errno = 0;
+  long ret = strtol(tmp, &end, field_base);
+  if(errno != 0) {
+    perror("strtol");
+    return -1;
+  }
+
+  return ret;
+}
+// https://developer.arm.com/docs/ddi0595/h/aarch32-system-registers/midr
+// https://static.docs.arm.com/ddi0595/h/SysReg_xml_v86A-2020-06.pdf
+uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success) {
+  int filelen;
+  char* buf;
+  *success = true;
+  if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
+    perror("open");
+    *success = false;     
+    return 0;    
+  }
+
+  char* tmp = strstr(buf, CPUINFO_CPU_STRING);
+  uint32_t current_core = 0;
+  while(core != current_core && tmp != NULL) {
+    tmp++;
+    current_core++;
+    tmp = strstr(tmp, CPUINFO_CPU_STRING);
+  }
+  
+  if(tmp == NULL) {
+    *success = false;    
+    return 0;
+  }
+
+  uint32_t cpu_implementer;
+  uint32_t cpu_architecture;
+  uint32_t cpu_variant;
+  uint32_t cpu_part;
+  uint32_t cpu_revision;
+  uint32_t midr = 0;
+  long ret;
+
+  if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_IMPLEMENTER_STR, 16)) < 0) {
+    printf("Failed parsing cpu_implementer\n");
+    *success = false;    
+    return 0;
+  }
+  cpu_implementer = (uint32_t) ret;
+
+  if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_ARCHITECTURE_STR, 10)) < 0) {
+    printf("Failed parsing cpu_architecture\n");
+    *success = false;    
+    return 0;
+  }
+  cpu_architecture = (uint32_t) 0xF; // Why?
+
+  if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_VARIANT_STR, 16)) < 0) {
+    printf("Failed parsing cpu_variant\n");
+    *success = false;    
+    return 0;
+  }
+  cpu_variant = (uint32_t) ret;
+
+  if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_PART_STR, 16)) < 0) {
+    printf("Failed parsing cpu_part\n");
+    *success = false;    
+    return 0;
+  }
+  cpu_part = (uint32_t) ret;
+
+  if ((ret = parse_cpuinfo_field(tmp, CPUINFO_CPU_REVISION_STR, 10)) < 0) {
+    printf("Failed parsing cpu_revision\n");
+    *success = false;    
+    return 0;
+  }
+  cpu_revision = (uint32_t) ret;
+
+  midr = midr_set_implementer(midr, cpu_implementer);
+  midr = midr_set_variant(midr, cpu_variant);
+  midr = midr_set_architecture(midr, cpu_architecture);
+  midr = midr_set_part(midr, cpu_part);
+  midr = midr_set_revision(midr, cpu_revision);
+
+  return midr;
+}
+
+char* get_hardware_from_cpuinfo() {
+  int filelen;
+  char* buf;
+  if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
+    perror("open");
+    return NULL;    
+  }
+  
+  char* tmp1 = strstr(buf, CPUINFO_HARDWARE_STR);
+  if(tmp1 == NULL) return NULL;
+  tmp1 = tmp1 + strlen(CPUINFO_HARDWARE_STR);
+  char* tmp2 = strstr(tmp1, "\n");
+  
+  int strlen = (1 + (tmp2-tmp1));
+  char* hardware = malloc(sizeof(char) * strlen);
+  memset(hardware, 0, sizeof(char) * strlen);
+  strncpy(hardware, tmp1, tmp2-tmp1);
+  
+  return hardware;
+}
+
--- a/src/arm/udev.h
+++ b/src/arm/udev.h
@@ -0,0 +1,12 @@
+#ifndef __UDEV_ARM__
+#define __UDEV_ARM__
+
+#include "../common/udev.h"
+
+#define UNKNOWN -1
+int get_ncores_from_cpuinfo();
+uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success);
+char* get_hardware_from_cpuinfo();
+
+#endif
+
--- a/src/ascii.h
+++ b/src/ascii.h
@@ -1,51 +0,0 @@
-#ifndef __ASCII__
-#define __ASCII__
-
-#define NUMBER_OF_LINES   20
-#define LINE_SIZE         62
-
-#define AMD_ASCII \
-"                                                              \
-                                                              \
-                                                              \
-                                                              \
-                                                              \
-                                                              \
-     @@@@      @@@       @@@   @@@@@@@@        ############   \
-    @@@@@@     @@@@@    @@@@   @@@    @@@@       ##########   \
-   @@@  @@@    @@@@@@@@@@@@@   @@@      @@      #      ####   \
-  @@@    @@@   @@@  @@@  @@@   @@@      @@@   ###      ####   \
- @@@@@@@@@@@@  @@@       @@@   @@@     @@@   ####    ## ###   \
- @@@      @@@  @@@       @@@   @@@@@@@@@     ########    ##   \
-                                                              \
-                                                              \
-                                                              \
-                                                              \
-                                                              \
-                                                              \
-                                                              \
-                                                            "
-
-#define INTEL_ASCII \
-"                              ################                \
-                      #######                #######          \
-                 ####                              ####       \
-             ###                                     ####     \
-        ###                                             ###   \
-        ###                                             ###   \
-     #                    ###                ###        ###   \
-   ##   ###   #########   ######   ######    ###        ###   \
-  ##    ###   ###    ###  ###    ####  ####  ###        ###   \
- ##     ###   ###    ###  ###    ###    ###  ###       ###    \
-##      ###   ###    ###  ###    ##########  ###     ####     \
-##      ###   ###    ###  ###    ###         ###   #####      \
-##       ##   ###    ###   #####  #########   ##  ###         \
-###                                                           \
- ###                                                          \
- ####                                        ####             \
-   #####                               ##########             \
-     ##########               ################                \
-         ###############################                      \
-                                                            "
-
-#endif
--- a/src/common/args.c
+++ b/src/common/args.c
@@ -0,0 +1,259 @@
+#include <getopt.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include "args.h"
+#include "global.h"
+
+#define COLOR_STR_INTEL "intel"
+#define COLOR_STR_AMD   "amd"
+#define COLOR_STR_ARM   "arm"
+
+static const char *SYTLES_STR_LIST[] = {
+  [STYLE_EMPTY]   = NULL,
+  [STYLE_FANCY]   = "fancy",
+  [STYLE_RETRO]   = "retro",
+  [STYLE_LEGACY]  = "legacy",
+  [STYLE_INVALID] = NULL
+};
+
+enum {
+  ARG_CHAR_STYLE,
+  ARG_CHAR_COLOR,
+  ARG_CHAR_HELP,
+  ARG_CHAR_DEBUG,
+  ARG_CHAR_VERBOSE,
+  ARG_CHAR_VERSION
+};
+
+struct args_struct {
+  bool debug_flag;
+  bool help_flag;
+  bool verbose_flag;
+  bool version_flag;
+  STYLE style;
+  struct colors* colors;
+};
+
+static struct args_struct args;
+
+STYLE get_style() {
+  return args.style;
+}
+
+struct colors* get_colors() {
+  return args.colors;
+}
+
+bool show_help() {
+  return args.help_flag;
+}
+
+bool show_version() {
+  return args.version_flag;
+}
+
+bool show_debug() {
+  return args.debug_flag;
+}
+
+bool verbose_enabled() {
+  return args.verbose_flag;
+}
+
+STYLE parse_style(char* style) {
+  uint8_t i = 0;
+  uint8_t styles_count = sizeof(SYTLES_STR_LIST) / sizeof(SYTLES_STR_LIST[0]);
+  
+  while(i != styles_count && (SYTLES_STR_LIST[i] == NULL || strcmp(SYTLES_STR_LIST[i], style) != 0))
+    i++;
+
+  if(i == styles_count)
+    return STYLE_INVALID;
+  
+  return i;
+}
+
+void free_colors_struct(struct colors* cs) {
+  free(cs->c1);
+  free(cs->c2);
+  free(cs->c3);
+  free(cs->c4);
+  free(cs);
+}
+
+bool parse_color(char* optarg_str, struct colors** cs) {
+  *cs = malloc(sizeof(struct colors));        
+  (*cs)->c1 = malloc(sizeof(struct color));
+  (*cs)->c2 = malloc(sizeof(struct color));
+  (*cs)->c3 = malloc(sizeof(struct color));
+  (*cs)->c4 = malloc(sizeof(struct color));
+  struct color** c1 = &((*cs)->c1);
+  struct color** c2 = &((*cs)->c2);
+  struct color** c3 = &((*cs)->c3);
+  struct color** c4 = &((*cs)->c4);
+  int32_t ret;
+  char* str_to_parse = NULL;
+  bool free_ptr;
+  
+  if(strcmp(optarg_str, COLOR_STR_INTEL) == 0) {
+    str_to_parse = malloc(sizeof(char) * 46);
+    strcpy(str_to_parse, COLOR_DEFAULT_INTEL);
+    free_ptr = true;
+  }
+  else if(strcmp(optarg_str, COLOR_STR_AMD) == 0) {
+    str_to_parse = malloc(sizeof(char) * 44);
+    strcpy(str_to_parse, COLOR_DEFAULT_AMD);  
+    free_ptr = true;
+  }
+  else if(strcmp(optarg_str, COLOR_STR_ARM) == 0) {
+    str_to_parse = malloc(sizeof(char) * 46);
+    strcpy(str_to_parse, COLOR_DEFAULT_ARM);  
+    free_ptr = true;
+  }
+  else {  
+    str_to_parse = optarg_str;
+    free_ptr = false;
+  }
+  
+  ret = sscanf(str_to_parse, "%d,%d,%d:%d,%d,%d:%d,%d,%d:%d,%d,%d", 
+               &(*c1)->R, &(*c1)->G, &(*c1)->B,
+               &(*c2)->R, &(*c2)->G, &(*c2)->B,
+               &(*c3)->R, &(*c3)->G, &(*c3)->B,
+               &(*c4)->R, &(*c4)->G, &(*c4)->B);
+  
+  if(ret != 12) {
+    printErr("Expected to read 12 values for color but read %d", ret);
+    return false;    
+  }
+  
+  //TODO: Refactor c1->R c2->R ... to c[i]->R
+  if((*c1)->R < 0 || (*c1)->R > 255) {
+    printErr("Red in color 1 is invalid. Must be in range (0, 255)");
+    return false;
+  }
+  if((*c1)->G < 0 || (*c1)->G > 255) {
+    printErr("Green in color 1 is invalid. Must be in range (0, 255)");
+    return false;
+  }
+  if((*c1)->B < 0 || (*c1)->B > 255) {
+    printErr("Blue in color 1 is invalid. Must be in range (0, 255)");
+    return false;
+  }
+  if((*c2)->R < 0 || (*c2)->R > 255) {
+    printErr("Red in color 2 is invalid. Must be in range (0, 255)");
+    return false;
+  }
+  if((*c2)->G < 0 || (*c2)->G > 255) {
+    printErr("Green in color 2 is invalid. Must be in range (0, 255)");
+    return false;
+  }
+  if((*c2)->B < 0 || (*c2)->B > 255) {
+    printErr("Blue in color 2 is invalid. Must be in range (0, 255)");
+    return false;
+  }  
+  
+  if(free_ptr) free (str_to_parse);
+  
+  return true;      
+}
+
+bool parse_args(int argc, char* argv[]) {
+  int c;
+  int option_index = 0;  
+  opterr = 0;
+
+  bool color_flag = false;
+  args.debug_flag = false;
+  args.verbose_flag = false;
+  args.help_flag = false;
+  args.style = STYLE_EMPTY;
+  args.colors = NULL;
+
+  static struct option long_options[] = {
+      {"style",    required_argument, 0, ARG_CHAR_STYLE   },
+      {"color",    required_argument, 0, ARG_CHAR_COLOR   },
+      {"help",     no_argument,       0, ARG_CHAR_HELP    },
+      {"debug",    no_argument,       0, ARG_CHAR_DEBUG   },
+      {"verbose",  no_argument,       0, ARG_CHAR_VERBOSE },
+      {"version",  no_argument,       0, ARG_CHAR_VERSION },
+      {0, 0, 0, 0}
+  };
+
+  c = getopt_long(argc, argv, "", long_options, &option_index);
+
+  while (c != -1) {
+     if(c == ARG_CHAR_COLOR) {
+       if(color_flag) {
+         printErr("Color option specified more than once");
+         return false;
+       }
+       color_flag  = true;       
+       if(!parse_color(optarg, &args.colors)) {
+         printErr("Color parsing failed");
+         return false;
+       }
+     }
+     else if(c == ARG_CHAR_STYLE) {
+       if(args.style != STYLE_EMPTY) {
+         printErr("Style option specified more than once");
+         return false;
+       }
+       args.style = parse_style(optarg);
+       if(args.style == STYLE_INVALID) {
+         printErr("Invalid style '%s'",optarg);
+         return false;
+       }
+     }
+     else if(c == ARG_CHAR_HELP) {
+       if(args.help_flag) {
+         printErr("Help option specified more than once");
+         return false;
+       }
+       args.help_flag  = true;
+     }
+     else if(c == ARG_CHAR_VERBOSE) {
+       if(args.verbose_flag) {
+         printErr("Verbose option specified more than once");
+         return false;
+       }
+       args.verbose_flag  = true;
+     }
+     else if(c == ARG_CHAR_DEBUG) {
+       if(args.debug_flag) {
+         printErr("Debug option specified more than once");
+         return false;
+       }
+       args.debug_flag  = true;
+     }
+     else if (c == ARG_CHAR_VERSION) {
+       if(args.version_flag) {
+         printErr("Version option specified more than once");
+         return false;
+       }
+       args.version_flag = true;
+     }
+     else if(c == '?') {
+       printWarn("Invalid options");
+       args.help_flag  = true;
+       break;
+     }
+     else
+      printBug("Bug at line number %d in file %s", __LINE__, __FILE__);
+
+    option_index = 0;
+    c = getopt_long(argc, argv,"",long_options, &option_index);
+  }
+
+  if (optind < argc) {
+    printWarn("Invalid options");
+    args.help_flag  = true;
+  }
+
+  if((args.help_flag + args.version_flag + color_flag) > 1) {
+    printWarn("You should specify just one option");
+    args.help_flag  = true;
+  }
+
+  return true;
+}
--- a/src/common/args.h
+++ b/src/common/args.h
@@ -0,0 +1,40 @@
+#ifndef __ARGS__
+#define __ARGS__
+
+#include <stdbool.h>
+#include <stdint.h>
+
+struct color {
+  int32_t R;
+  int32_t G;
+  int32_t B;
+};
+
+struct colors {
+  struct color* c1;
+  struct color* c2;
+  struct color* c3;
+  struct color* c4;
+};
+
+enum {
+  STYLE_EMPTY,
+  STYLE_FANCY,
+  STYLE_WILD,
+  STYLE_RETRO,
+  STYLE_LEGACY,
+  STYLE_INVALID
+};
+
+#include "printer.h"
+
+bool parse_args(int argc, char* argv[]);
+bool show_help();
+bool show_debug();
+bool show_version();
+bool verbose_enabled();
+void free_colors_struct(struct colors* cs);
+struct colors* get_colors();
+STYLE get_style();
+
+#endif
--- a/src/common/ascii.h
+++ b/src/common/ascii.h
@@ -0,0 +1,208 @@
+#ifndef __ASCII__
+#define __ASCII__
+
+#define NUMBER_OF_LINES   19
+#define LINE_SIZE         62
+
+#define AMD_ASCII \
+"                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+     @@@@      @@@       @@@   @@@@@@@@        ############   \
+    @@@@@@     @@@@@    @@@@   @@@    @@@@       ##########   \
+   @@@  @@@    @@@@@@@@@@@@@   @@@      @@      #      ####   \
+  @@@    @@@   @@@  @@@  @@@   @@@      @@@   ###      ####   \
+ @@@@@@@@@@@@  @@@       @@@   @@@     @@@   ####    ## ###   \
+ @@@      @@@  @@@       @@@   @@@@@@@@@     ########    ##   \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              "
+
+#define INTEL_ASCII \
+"                              ################                \
+                      #######                #######          \
+                 ####                              ####       \
+             ###                                     ####     \
+        ###                                             ###   \
+        ###                                             ###   \
+     #                    ###                ###        ###   \
+   ##   ###   #########   ######   ######    ###        ###   \
+  ##    ###   ###    ###  ###    ####  ####  ###        ###   \
+ ##     ###   ###    ###  ###    ###    ###  ###       ###    \
+##      ###   ###    ###  ###    ##########  ###     ####     \
+##      ###   ###    ###  ###    ###         ###   #####      \
+##       ##   ###    ###   #####  #########   ##  ###         \
+###                                                           \
+ ###                                                          \
+ ####                                        ####             \
+   #####                               ##########             \
+     ##########               ################                \
+         ###############################                      "
+                                                             
+#define SNAPDRAGON_ASCII \
+"                                                              \
+                     @@########                               \
+                  @@@@@###########                            \
+            @@  @@@@@#################                        \
+          @@@@@@@@@@####################                      \
+         @@@@@@@@@@@@#####################                    \
+        @@@@@@@@@@@@@@@####################                   \
+        @@@@@@@@@@@@@@@@@###################                  \
+        @@@@@@@@@@@@@@@@@@@@################                  \
+           @@@@@@@@@@@@@@@@@@@@#############                  \
+              @@@@@@@@@@@@@@@@@@############                  \
+       @          @@@@@@@@@@@@@@@###########                  \
+        @@@@@       @@@@@@@@@@@@@##########                   \
+         @@@@@@@@@   @@@@@@@@@@@@########                     \
+           @@@@@@@@@  @@@@@@@@@@#######                       \
+              @@@@@@@@@@@@@@@@#######                         \
+                  @@@@###########                             \
+                                                              \
+                                                              "
+                                                             
+#define MEDIATEK_ASCII \
+"                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+      ##  ## ######  ######  #     ### @@@@@@ @@@@@@ @@  @@   \
+     ### ### #       #    #  #    ####   @@   @      @@ @@    \
+    ######## # ###   #    #  #   ## ##   @@   @ @@@  @@@@     \
+   ## ### ## #       #    #  #  ##  ##   @@   @      @@ @@    \
+  ##  ##  ## ######  #####   # ##   ##   @@   @@@@@@ @@  @@   \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              "
+
+#define EXYNOS_ASCII \
+"                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                         ##  ##  ##                           \
+                           ##  ##                             \
+                             ##                               \
+                           ##  ##                             \
+                         ##  ##  ##                           \
+                                                              \
+                         SAMSUNG                              \
+                         Exynos                               \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              "
+                                                              
+#define KIRIN_ASCII \
+"                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                   #######                    \
+       #####             ####################                 \
+          ######################################              \
+            #######################################           \
+               #######################################        \
+                 ##############################               \
+                ##########################                    \
+             #########################                        \
+           ########################                           \
+        ########################                              \
+     #########################                                \
+   #########################                                  \
+                                                              \
+                                                              "                                                                                                                           
+                                                              
+#define BROADCOM_ASCII \
+"                                                              \
+                    ################                          \
+               #########################                      \
+            ###############################                   \
+          ################@@@@################                \
+         ################@@@@@@################               \
+        #################@@@@@@################               \
+       #################@@@@@@@@#################             \
+       #################@@@@@@@@#################             \
+      #################@@@@##@@@@################             \
+       ################@@@@##@@@@################             \
+       ###############@@@@####@@@@###############             \
+        @@@@@@@@@@####@@@@####@@@@####@@@@@@@@@@              \
+         ######@@@@@@@@@@######@@@@@@@@@@######               \
+           ##################################                 \
+             ##############################                   \
+                ########################                      \
+                    ###############                           \
+                                                              "
+                                                                                                              
+#define ARM_ASCII \
+"                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+      ############     ##########   ####  ######  ########    \
+   ###############     #########    #######################   \
+  ####        ####     ####         #####   #######   #####   \
+ ####         ####     ####         ####     #####     ####   \
+ ####         ####     ####         ####     ####      ####   \
+  ####       #####     ####         ####     ####      ####   \
+   ###############     ####         ####     ####      ####   \
+    ########  ####     ####         ####     ####      ####   \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              "                                                                                                               
+
+#define UNKNOWN_ASCII \
+"                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              \
+                                                              "
+                                                             
+static const char* ASCII_ARRAY [] = {
+  AMD_ASCII,
+  INTEL_ASCII,
+  ARM_ASCII,
+  SNAPDRAGON_ASCII,
+  MEDIATEK_ASCII,
+  EXYNOS_ASCII,
+  KIRIN_ASCII,
+  BROADCOM_ASCII,
+  UNKNOWN_ASCII
+};                                                             
+
+#endif
--- a/src/common/cpu.c
+++ b/src/common/cpu.c
@@ -0,0 +1,186 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+#include <stdbool.h>
+
+#include "../common/global.h"
+#include "cpu.h"
+
+#ifdef ARCH_X86
+  #include "../x86/uarch.h"
+#elif ARCH_ARM
+  #include "../arm/uarch.h"
+#endif
+
+#define STRING_UNKNOWN    "Unknown"
+#define STRING_YES        "Yes"
+#define STRING_NO         "No"
+#define STRING_NONE       "None"
+#define STRING_MEGAHERZ   "MHz"
+#define STRING_GIGAHERZ   "GHz"
+#define STRING_KILOBYTES  "KB"
+#define STRING_MEGABYTES  "MB"
+
+VENDOR get_cpu_vendor(struct cpuInfo* cpu) {
+  return cpu->cpu_vendor;
+}
+
+int64_t get_freq(struct frequency* freq) {
+  return freq->max;
+}
+
+#ifdef ARCH_X86
+char* get_str_cpu_name(struct cpuInfo* cpu) {
+  return cpu->cpu_name;    
+}
+
+char* get_str_sockets(struct topology* topo) {
+  char* string = malloc(sizeof(char) * 2);
+  int32_t sanity_ret = snprintf(string, 2, "%d", topo->sockets);
+  if(sanity_ret < 0) {
+    printBug("get_str_sockets: snprintf returned a negative value for input: '%d'", topo->sockets);
+    return NULL;
+  }
+  return string;
+}
+
+uint32_t get_nsockets(struct topology* topo) {
+  return topo->sockets;
+}
+#endif
+
+int32_t get_value_as_smallest_unit(char ** str, uint32_t value) {
+  int32_t sanity_ret;
+  *str = malloc(sizeof(char)* 11); //8 for digits, 2 for units
+
+  if(value/1024 >= 1024)
+    sanity_ret = snprintf(*str, 10,"%.4g"STRING_MEGABYTES, (double)value/(1<<20));
+  else
+    sanity_ret = snprintf(*str, 10,"%.4g"STRING_KILOBYTES, (double)value/(1<<10));  
+  
+  return sanity_ret;
+}
+
+// String functions 
+char* get_str_cache_two(int32_t cache_size, uint32_t physical_cores) {
+  // 4 for digits, 2 for units, 2 for ' (', 3 digits, 2 for units and 7 for ' Total)'
+  uint32_t max_size = 4+2 + 2 + 4+2 + 7 + 1;
+  int32_t sanity_ret;
+  char* string = malloc(sizeof(char) * max_size);  
+  char* tmp1;
+  char* tmp2;  
+  int32_t tmp1_len = get_value_as_smallest_unit(&tmp1, cache_size);
+  int32_t tmp2_len = get_value_as_smallest_unit(&tmp2, cache_size * physical_cores);
+  
+  if(tmp1_len < 0) {
+    printBug("get_value_as_smallest_unit: snprintf returned a negative value for input: %d\n", cache_size);
+    return NULL;    
+  }
+  if(tmp2_len < 0) {
+    printBug("get_value_as_smallest_unit: snprintf returned a negative value for input: %d\n", cache_size * physical_cores);
+    return NULL;    
+  }
+    
+  uint32_t size = tmp1_len + 2 + tmp2_len + 7 + 1;
+  sanity_ret = snprintf(string, size, "%s (%s Total)", tmp1, tmp2);  
+  
+  if(sanity_ret < 0) {
+    printBug("get_str_cache_two: snprintf returned a negative value for input: '%s' and '%s'\n", tmp1, tmp2);
+    return NULL;    
+  }
+  
+  free(tmp1);
+  free(tmp2);
+  return string;
+}
+
+char* get_str_cache_one(int32_t cache_size) {
+  // 4 for digits, 2 for units, 2 for ' (', 3 digits, 2 for units and 7 for ' Total)'
+  uint32_t max_size = 4+2 + 1;
+  int32_t sanity_ret;
+  char* string = malloc(sizeof(char) * max_size);  
+  char* tmp;
+  int32_t tmp_len = get_value_as_smallest_unit(&tmp, cache_size);
+  
+  if(tmp_len < 0) {
+    printBug("get_value_as_smallest_unit: snprintf returned a negative value for input: %d", cache_size);
+    return NULL;    
+  }
+      
+  uint32_t size = tmp_len + 1;
+  sanity_ret = snprintf(string, size, "%s", tmp);
+  
+  if(sanity_ret < 0) {
+    printBug("get_str_cache_one: snprintf returned a negative value for input: '%s'", tmp);
+    return NULL;    
+  }
+  free(tmp);
+  return string;
+}
+
+char* get_str_cache(int32_t cache_size, int32_t num_caches) {
+  if(num_caches > 1)
+    return get_str_cache_two(cache_size, num_caches);
+  else
+    return get_str_cache_one(cache_size);
+}
+
+char* get_str_l1i(struct cache* cach) {
+  return get_str_cache(cach->L1i->size, cach->L1i->num_caches);
+}
+
+char* get_str_l1d(struct cache* cach) {
+  return get_str_cache(cach->L1d->size, cach->L1d->num_caches);
+}
+
+char* get_str_l2(struct cache* cach) {
+  assert(cach->L2->exists);
+  return get_str_cache(cach->L2->size, cach->L2->num_caches);
+}
+
+char* get_str_l3(struct cache* cach) {
+  if(!cach->L3->exists)
+    return NULL;  
+  return get_str_cache(cach->L3->size, cach->L3->num_caches);
+}
+
+char* get_str_freq(struct frequency* freq) {
+  //Max 3 digits and 3 for '(M/G)Hz' plus 1 for '\0'
+  uint32_t size = (4+3+1);
+  assert(strlen(STRING_UNKNOWN)+1 <= size);
+  char* string = malloc(sizeof(char)*size);
+  memset(string, 0, sizeof(char)*size);
+  
+  if(freq->max == UNKNOWN_FREQ || freq->max < 0)
+    snprintf(string,strlen(STRING_UNKNOWN)+1,STRING_UNKNOWN);
+  else if(freq->max >= 1000)
+    snprintf(string,size,"%.2f"STRING_GIGAHERZ,(float)(freq->max)/1000);
+  else
+    snprintf(string,size,"%d"STRING_MEGAHERZ,freq->max);
+  
+  return string;
+}
+
+void free_cache_struct(struct cache* cach) {
+  for(int i=0; i < 4; i++) free(cach->cach_arr[i]);
+  free(cach->cach_arr);
+  free(cach);
+}
+
+void free_freq_struct(struct frequency* freq) {
+  free(freq);
+}
+
+void free_hv_struct(struct hypervisor* hv) {
+  free(hv);
+}
+
+void free_cpuinfo_struct(struct cpuInfo* cpu) {
+  free_uarch_struct(cpu->arch);
+  free_hv_struct(cpu->hv);
+  #ifdef ARCH_X86
+  free(cpu->cpu_name);
+  #endif
+  free(cpu);
+}
--- a/src/common/cpu.h
+++ b/src/common/cpu.h
@@ -0,0 +1,158 @@
+#ifndef __CPU__
+#define __CPU__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+enum {
+// ARCH_X86
+  CPU_VENDOR_INTEL,
+  CPU_VENDOR_AMD,
+// ARCH_ARM
+  CPU_VENDOR_ARM,
+  CPU_VENDOR_BROADCOM,
+  CPU_VENDOR_CAVIUM,
+  CPU_VENDOR_NVIDIA,
+  CPU_VENDOR_APM,
+  CPU_VENDOR_QUALCOMM,
+  CPU_VENDOR_HUAWUEI,
+  CPU_VENDOR_SAMSUNG,
+  CPU_VENDOR_MARVELL,
+// OTHERS
+  CPU_VENDOR_UNKNOWN,
+  CPU_VENDOR_INVALID
+};
+
+enum {
+  HV_VENDOR_KVM,
+  HV_VENDOR_QEMU,
+  HV_VENDOR_HYPERV,
+  HV_VENDOR_VMWARE,
+  HV_VENDOR_XEN,
+  HV_VENDOR_PARALLELS,
+  HV_VENDOR_INVALID
+};
+
+#define UNKNOWN_FREQ -1
+#define CPU_NAME_MAX_LENGTH 64
+
+typedef int32_t VENDOR;
+
+struct frequency {
+  int32_t base;
+  int32_t max;
+};
+
+struct hypervisor {
+  bool present;
+  char* hv_name;
+  VENDOR hv_vendor;
+};
+
+struct cach {
+  int32_t size;
+  uint8_t num_caches;
+  bool exists;
+  // plenty of more properties to include in the future...
+};
+
+struct cache {
+  struct cach* L1i;
+  struct cach* L1d;
+  struct cach* L2;
+  struct cach* L3;
+  struct cach** cach_arr;
+
+  uint8_t max_cache_level;
+};
+
+struct topology {
+  int32_t total_cores;  
+  struct cache* cach;
+#ifdef ARCH_X86
+  uint32_t physical_cores;  
+  uint32_t logical_cores;
+  uint32_t smt_available; // Number of SMT that is currently enabled
+  uint32_t smt_supported; // Number of SMT that CPU supports (equal to smt_available if SMT is enabled)
+  uint32_t sockets;
+  struct apic* apic;
+#endif
+};
+
+struct features {
+  bool AES; // Must be the first field of features struct!  
+#ifdef ARCH_X86
+  bool AVX;
+  bool AVX2;
+  bool AVX512;
+  bool SSE;
+  bool SSE2;
+  bool SSE3;
+  bool SSSE3;
+  bool SSE4a;
+  bool SSE4_1;
+  bool SSE4_2;
+  bool FMA3;
+  bool FMA4;
+  bool SHA;  
+#elif ARCH_ARM
+  bool NEON;  
+  bool SHA1;
+  bool SHA2;
+  bool CRC32;
+#endif  
+};
+
+struct cpuInfo {
+  VENDOR cpu_vendor;  
+  struct uarch* arch;
+  struct hypervisor* hv;
+  struct frequency* freq;
+  struct cache* cach;
+  struct topology* topo;
+  struct features* feat;
+  
+#ifdef ARCH_X86
+  // CPU name from model
+  char* cpu_name;
+  //  Max cpuids levels
+  uint32_t maxLevels;
+  // Max cpuids extended levels
+  uint32_t maxExtendedLevels;
+#elif ARCH_ARM
+  // Main ID register
+  uint32_t midr;
+#endif
+
+#ifdef ARCH_ARM
+  struct system_on_chip* soc;
+  // If SoC contains more than one CPU and they
+  // are different, the others will be stored in
+  // the next_cpu field
+  struct cpuInfo* next_cpu;  
+  uint8_t num_cpus;
+#endif
+};
+
+#ifdef ARCH_X86
+char* get_str_cpu_name(struct cpuInfo* cpu);
+char* get_str_sockets(struct topology* topo);
+uint32_t get_nsockets(struct topology* topo);
+#endif
+
+VENDOR get_cpu_vendor(struct cpuInfo* cpu);
+int64_t get_freq(struct frequency* freq);
+
+char* get_str_aes(struct cpuInfo* cpu);
+char* get_str_sha(struct cpuInfo* cpu);
+char* get_str_l1i(struct cache* cach);
+char* get_str_l1d(struct cache* cach);
+char* get_str_l2(struct cache* cach);
+char* get_str_l3(struct cache* cach);
+char* get_str_freq(struct frequency* freq);
+
+void free_cache_struct(struct cache* cach);
+void free_freq_struct(struct frequency* freq);
+void free_cpuinfo_struct(struct cpuInfo* cpu);
+
+#endif
--- a/src/common/global.c
+++ b/src/common/global.c
@@ -16,8 +16,10 @@

 #endif

-#define LOG_LEVEL_NORMAL  0
-#define LOG_LEVEL_VERBOSE 1
+enum {
+  LOG_LEVEL_NORMAL,
+  LOG_LEVEL_VERBOSE
+};

 int LOG_LEVEL;

@@ -51,7 +53,11 @@ void printBug(const char *fmt, ...) {
  vsnprintf(buffer,buffer_size, fmt, args);
  va_end(args);
  fprintf(stderr,RED "[ERROR]: "RESET "%s\n",buffer);
-  fprintf(stderr,"Please, create a new issue with this error message and your CPU in https://github.com/Dr-Noob/cpufetch/issues\n");
+#ifdef ARCH_X86
+  fprintf(stderr,"Please, create a new issue with this error message and the output of 'cpufetch --debug' in https://github.com/Dr-Noob/cpufetch/issues\n");
+#elif ARCH_ARM
+  fprintf(stderr,"Please, create a new issue with this error message, your smartphone/computer model and the output of 'cpufetch --debug' in https://github.com/Dr-Noob/cpufetch/issues\n");
+#endif
 }

 void set_log_level(bool verbose) {
--- a/src/common/global.h
+++ b/src/common/global.h
--- a/src/common/main.c
+++ b/src/common/main.c
@@ -0,0 +1,88 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "args.h"
+#include "printer.h"
+#include "global.h"
+
+#ifdef ARCH_X86
+  static const char* ARCH_STR = "x86_64 build";
+  #include "../x86/cpuid.h"
+#elif ARCH_ARM
+  static const char* ARCH_STR = "ARM build";
+  #include "../arm/midr.h"
+#endif
+
+static const char* VERSION = "0.94";
+
+void print_help(char *argv[]) {
+  printf("Usage: %s [--version] [--help] [--debug] [--style \"fancy\"|\"retro\"|\"legacy\"] [--color \"intel\"|\"amd\"|'R,G,B:R,G,B:R,G,B:R,G,B']\n\n", argv[0]);
+
+  printf("Options: \n\
+  --color       Set the color scheme. By default, cpufetch uses the system color scheme. This option \n\
+                lets the user use different colors to print the CPU art:  \n\
+   * \"intel\":   Use Intel default color scheme \n\
+   * \"amd\":     Use AMD default color scheme \n\
+   * \"arm\":     Use ARM default color scheme \n\
+   * custom:    If color argument do not match \"Intel\", \"AMD\" or \"ARM\", a custom scheme can be specified: \n\
+                4 colors must be given in RGB with the format: R,G,B:R,G,B:... \n\
+                These colors correspond to CPU art color (2 colors) and for the text colors (following 2) \n\
+                For example: --color 239,90,45:210,200,200:100,200,45:0,200,200 \n\n\
+  --style       Set the style of CPU art: \n\
+    * \"fancy\":  Default style      \n\
+    * \"retro\":  Old cpufetch style \n\
+    * \"legacy\": Fallback style for terminals that does not support colors                       \n\n");
+
+#ifdef ARCH_X86
+  printf("  --debug       Prints CPU model and cpuid levels (debug purposes)\n\n");
+#elif ARCH_ARM
+  printf("  --debug       Prints main ID register values for all cores (debug purposes)\n\n");
+#endif
+
+  printf("  --verbose     Prints extra information (if available) about how cpufetch tried fetching information\n\n\
+  --help        Prints this help and exit\n\n\
+  --version     Prints cpufetch version and exit\n\n\
+                                                   \n\
+NOTES: \n\
+  - Bugs or improvements should be submitted to: github.com/Dr-Noob/cpufetch/issues        \n\
+  - Peak performance information is NOT accurate. cpufetch computes peak performance using the max   \n\
+    frequency. However, to properly compute peak performance, you need to know the frequency of the  \n\
+    CPU running AVX code, which is not be fetched by cpufetch since it depends on each specific CPU. \n");
+}
+
+void print_version() {
+  printf("cpufetch v%s (%s)\n",VERSION, ARCH_STR);
+}
+
+int main(int argc, char* argv[]) {
+  if(!parse_args(argc,argv))
+    return EXIT_FAILURE;
+
+  if(show_help()) {
+    print_version();
+    print_help(argv);
+    return EXIT_SUCCESS;
+  }
+
+  if(show_version()) {
+    print_version();
+    return EXIT_SUCCESS;
+  }
+
+  set_log_level(verbose_enabled());
+
+  struct cpuInfo* cpu = get_cpu_info();
+  if(cpu == NULL)
+    return EXIT_FAILURE;
+
+  if(show_debug()) {
+    print_version();
+    print_debug(cpu);
+    return EXIT_SUCCESS;
+  }
+  
+  if(print_cpufetch(cpu, get_style(), get_colors()))
+    return EXIT_SUCCESS;
+  else
+    return EXIT_FAILURE;
+}
--- a/src/common/printer.c
+++ b/src/common/printer.c
@@ -0,0 +1,716 @@
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <stdbool.h>
+
+#include "printer.h"
+#include "ascii.h"
+#include "../common/global.h"
+#include "../common/cpu.h"
+
+#ifdef ARCH_X86
+  #include "../x86/uarch.h"
+  #include "../x86/cpuid.h"
+#else
+  #include "../arm/uarch.h"
+  #include "../arm/midr.h"
+  #include "../arm/soc.h"
+#endif
+
+#ifdef _WIN32
+#define NOMINMAX
+#include <Windows.h>
+#endif
+
+#define max(a,b) (((a)>(b))?(a):(b))
+#define MAX_ATTRIBUTES      100
+
+#define COLOR_NONE       ""
+#define COLOR_FG_BLACK   "\x1b[30;1m"
+#define COLOR_FG_RED     "\x1b[31;1m"
+#define COLOR_FG_GREEN   "\x1b[32;1m"
+#define COLOR_FG_YELLOW  "\x1b[33;1m"
+#define COLOR_FG_BLUE    "\x1b[34;1m"
+#define COLOR_FG_MAGENTA "\x1b[35;1m"
+#define COLOR_FG_CYAN    "\x1b[36;1m"
+#define COLOR_FG_WHITE   "\x1b[37;1m"
+#define COLOR_BG_BLACK   "\x1b[40;1m"
+#define COLOR_BG_RED     "\x1b[41;1m"
+#define COLOR_BG_GREEN   "\x1b[42;1m"
+#define COLOR_BG_YELLOW  "\x1b[43;1m"
+#define COLOR_BG_BLUE    "\x1b[44;1m"
+#define COLOR_BG_MAGENTA "\x1b[45;1m"
+#define COLOR_BG_CYAN    "\x1b[46;1m"
+#define COLOR_BG_WHITE   "\x1b[47;1m"
+#define COLOR_RESET      "\x1b[m"
+
+enum {
+#ifdef ARCH_X86    
+  ATTRIBUTE_NAME,
+#elif ARCH_ARM
+  ATTRIBUTE_SOC,
+  ATTRIBUTE_CPU_NUM,
+#endif
+  ATTRIBUTE_HYPERVISOR,
+  ATTRIBUTE_UARCH,
+  ATTRIBUTE_TECHNOLOGY,
+  ATTRIBUTE_FREQUENCY,
+  ATTRIBUTE_SOCKETS,
+  ATTRIBUTE_NCORES,
+  ATTRIBUTE_NCORES_DUAL,
+#ifdef ARCH_X86
+  ATTRIBUTE_AVX,
+  ATTRIBUTE_FMA,
+#elif ARCH_ARM
+  ATTRIBUTE_FEATURES,
+#endif
+  ATTRIBUTE_L1i,
+  ATTRIBUTE_L1d,
+  ATTRIBUTE_L2,
+  ATTRIBUTE_L3,
+  ATTRIBUTE_PEAK
+};
+
+static const char* ATTRIBUTE_FIELDS [] = {
+#ifdef ARCH_X86    
+  "Name:",
+ #elif ARCH_ARM 
+  "SoC:",
+  "",
+#endif
+  "Hypervisor:",
+  "Microarchitecture:",
+  "Technology:",
+  "Max Frequency:",
+  "Sockets:",
+  "Cores:",
+  "Cores (Total):",
+#ifdef ARCH_X86
+  "AVX:",
+  "FMA:",
+#elif ARCH_ARM
+  "Features: ",  
+#endif
+  "L1i Size:",
+  "L1d Size:",
+  "L2 Size:",
+  "L3 Size:",
+  "Peak Performance:",
+};
+
+struct attribute {
+  int type;
+  char* value;    
+};
+
+struct ascii {
+  char art[NUMBER_OF_LINES][LINE_SIZE+1];
+  char color1_ascii[100];
+  char color2_ascii[100];
+  char color1_text[100];
+  char color2_text[100];
+  char ascii_chars[2];
+  char reset[100];
+  struct attribute** attributes;
+  uint32_t n_attributes_set;
+  uint32_t additional_spaces;
+  VENDOR vendor;
+  STYLE style;
+};
+
+void setAttribute(struct ascii* art, int type, char* value) {
+  art->attributes[art->n_attributes_set]->value = value;
+  art->attributes[art->n_attributes_set]->type = type;
+  art->n_attributes_set++;
+  
+  if(art->n_attributes_set > MAX_ATTRIBUTES) {
+    printBug("Set %d attributes, while max value is %d!", art->n_attributes_set, MAX_ATTRIBUTES);
+  }
+}
+
+char* rgb_to_ansi(struct color* c, bool background, bool bold) {
+  char* str = malloc(sizeof(char) * 100);
+  if(background) {
+    snprintf(str, 44, "\x1b[48;2;%.3d;%.3d;%.3dm", c->R, c->G, c->B);
+  }
+  else {
+    if(bold)
+      snprintf(str, 48, "\x1b[1m\x1b[38;2;%.3d;%.3d;%.3dm", c->R, c->G, c->B);
+    else
+      snprintf(str, 44, "\x1b[38;2;%.3d;%.3d;%.3dm", c->R, c->G, c->B);
+  }
+
+  return str;
+}
+
+struct ascii* set_ascii(VENDOR vendor, STYLE style, struct colors* cs) {
+  char *COL_FANCY_1, *COL_FANCY_2, *COL_FANCY_3, *COL_FANCY_4, *COL_RETRO_1, *COL_RETRO_2, *COL_RETRO_3, *COL_RETRO_4;
+  struct ascii* art = malloc(sizeof(struct ascii));
+  art->n_attributes_set = 0;
+  art->additional_spaces = 0;
+  art->vendor = vendor;
+  art->attributes = malloc(sizeof(struct attribute *) * MAX_ATTRIBUTES);
+  for(uint32_t i=0; i < MAX_ATTRIBUTES; i++) {
+    art->attributes[i] = malloc(sizeof(struct attribute));
+    art->attributes[i]->type = 0;
+    art->attributes[i]->value = NULL;
+  }
+  strcpy(art->reset, COLOR_RESET);
+
+#ifdef ARCH_X86  
+  if(art->vendor == CPU_VENDOR_INTEL) {
+    COL_FANCY_1 = COLOR_BG_CYAN;
+    COL_FANCY_2 = COLOR_BG_WHITE;
+    COL_FANCY_3 = COLOR_FG_CYAN;
+    COL_FANCY_4 = COLOR_FG_WHITE;
+    art->ascii_chars[0] = '#';
+  }
+  else if(art->vendor == CPU_VENDOR_AMD) {
+    COL_FANCY_1 = COLOR_BG_WHITE;
+    COL_FANCY_2 = COLOR_BG_GREEN;
+    COL_FANCY_3 = COLOR_FG_WHITE;
+    COL_FANCY_4 = COLOR_FG_GREEN;    
+    art->ascii_chars[0] = '@';
+  }
+  else {
+    printBug("Invalid CPU vendor in set_ascii (%d)", art->vendor);    
+    return NULL;
+  }
+#elif ARCH_ARM
+  if(art->vendor == SOC_VENDOR_SNAPDRAGON) {
+    COL_FANCY_1 = COLOR_BG_RED;
+    COL_FANCY_2 = COLOR_BG_WHITE;
+    COL_FANCY_3 = COLOR_FG_RED;
+    COL_FANCY_4 = COLOR_FG_WHITE;
+    art->ascii_chars[0] = '@';
+  }
+  else if(art->vendor == SOC_VENDOR_MEDIATEK) {
+    COL_FANCY_1 = COLOR_BG_BLUE;
+    COL_FANCY_2 = COLOR_BG_YELLOW;
+    COL_FANCY_3 = COLOR_FG_WHITE;
+    COL_FANCY_4 = COLOR_FG_BLUE;
+    art->ascii_chars[0] = '@';
+  }
+  else if(art->vendor == SOC_VENDOR_EXYNOS) {
+    COL_FANCY_1 = COLOR_BG_BLUE;
+    COL_FANCY_2 = COLOR_BG_WHITE;
+    COL_FANCY_3 = COLOR_FG_BLUE;
+    COL_FANCY_4 = COLOR_FG_WHITE;
+    art->ascii_chars[0] = '@';
+  }
+  else if(art->vendor == SOC_VENDOR_KIRIN) {
+    COL_FANCY_1 = COLOR_BG_WHITE;
+    COL_FANCY_2 = COLOR_BG_RED;
+    COL_FANCY_3 = COLOR_FG_WHITE;
+    COL_FANCY_4 = COLOR_FG_RED;
+    art->ascii_chars[0] = '@';
+  }
+  else if(art->vendor == SOC_VENDOR_BROADCOM) {
+    COL_FANCY_1 = COLOR_BG_WHITE;
+    COL_FANCY_2 = COLOR_BG_RED;
+    COL_FANCY_3 = COLOR_FG_WHITE;
+    COL_FANCY_4 = COLOR_FG_RED;
+    art->ascii_chars[0] = '@';
+  }
+  else {
+    COL_FANCY_1 = COLOR_BG_CYAN;
+    COL_FANCY_2 = COLOR_BG_CYAN;
+    COL_FANCY_3 = COLOR_FG_WHITE;
+    COL_FANCY_4 = COLOR_FG_CYAN;
+    art->ascii_chars[0] = '#';
+  }
+#endif
+  COL_RETRO_1 = COL_FANCY_3;
+  COL_RETRO_2 = COL_FANCY_4;
+  COL_RETRO_3 = COL_RETRO_1;
+  COL_RETRO_4 = COL_RETRO_2;
+  art->ascii_chars[1] = '#';
+
+  #ifdef _WIN32
+    HANDLE std_handle = GetStdHandle(STD_OUTPUT_HANDLE);
+    DWORD console_mode;
+
+    // Attempt to enable the VT100-processing flag
+    GetConsoleMode(std_handle, &console_mode);
+    SetConsoleMode(std_handle, console_mode | ENABLE_VIRTUAL_TERMINAL_PROCESSING);
+    // Get the console mode flag again, to see if it successfully enabled it
+    GetConsoleMode(std_handle, &console_mode);
+  #endif
+
+  if(style == STYLE_EMPTY) {
+    #ifdef _WIN32
+      // Use fancy style if VT100-processing is enabled,
+      // or legacy style in other case
+      art->style = (console_mode & ENABLE_VIRTUAL_TERMINAL_PROCESSING) ? STYLE_FANCY : STYLE_LEGACY;
+    #else
+      art->style = STYLE_FANCY;
+    #endif
+  }
+  else {
+    art->style = style;
+  }
+
+  switch(art->style) {
+    case STYLE_LEGACY:
+      strcpy(art->color1_ascii, COLOR_NONE);
+      strcpy(art->color2_ascii, COLOR_NONE);
+      strcpy(art->color1_text, COLOR_NONE);
+      strcpy(art->color2_text, COLOR_NONE);
+      art->reset[0] = '\0';
+      break;
+    case STYLE_FANCY:
+      if(cs != NULL) {
+        COL_FANCY_1 = rgb_to_ansi(cs->c1, true, true);
+        COL_FANCY_2 = rgb_to_ansi(cs->c2, true, true);
+        COL_FANCY_3 = rgb_to_ansi(cs->c3, false, true);
+        COL_FANCY_4 = rgb_to_ansi(cs->c4, false, true);
+      }
+      art->ascii_chars[0] = ' ';
+      art->ascii_chars[1] = ' ';
+      strcpy(art->color1_ascii,COL_FANCY_1);
+      strcpy(art->color2_ascii,COL_FANCY_2);
+      strcpy(art->color1_text,COL_FANCY_3);
+      strcpy(art->color2_text,COL_FANCY_4);
+      if(cs != NULL) {
+        free(COL_FANCY_1);
+        free(COL_FANCY_2);
+        free(COL_FANCY_3);
+        free(COL_FANCY_4);
+      }
+      break;
+    case STYLE_RETRO:
+      if(cs != NULL) {
+        COL_RETRO_1 = rgb_to_ansi(cs->c1, false, true);
+        COL_RETRO_2 = rgb_to_ansi(cs->c2, false, true);
+        COL_RETRO_3 = rgb_to_ansi(cs->c3, false, true);
+        COL_RETRO_4 = rgb_to_ansi(cs->c4, false, true);
+      }
+      strcpy(art->color1_ascii,COL_RETRO_1);
+      strcpy(art->color2_ascii,COL_RETRO_2);
+      strcpy(art->color1_text,COL_RETRO_3);
+      strcpy(art->color2_text,COL_RETRO_4);
+      if(cs != NULL) {
+        free(COL_RETRO_1);
+        free(COL_RETRO_2);
+        free(COL_RETRO_3);
+        free(COL_RETRO_4);
+      }
+      break;
+    case STYLE_INVALID:
+    default:
+      printBug("Found invalid style (%d)", art->style);
+      return NULL;
+  }
+
+  char tmp[NUMBER_OF_LINES * LINE_SIZE + 1];
+#ifdef ARCH_X86  
+  if(art->vendor == CPU_VENDOR_INTEL)
+    strcpy(tmp, INTEL_ASCII);
+  else if(art->vendor == CPU_VENDOR_AMD)
+    strcpy(tmp, AMD_ASCII);
+  else
+    strcpy(tmp, UNKNOWN_ASCII);  
+#elif ARCH_ARM  
+  if(art->vendor == SOC_VENDOR_SNAPDRAGON)
+    strcpy(tmp, SNAPDRAGON_ASCII);
+  else if(art->vendor == SOC_VENDOR_MEDIATEK)
+    strcpy(tmp, MEDIATEK_ASCII);
+  else if(art->vendor == SOC_VENDOR_EXYNOS)
+    strcpy(tmp, EXYNOS_ASCII);
+  else if(art->vendor == SOC_VENDOR_KIRIN)
+    strcpy(tmp, KIRIN_ASCII);
+  else if(art->vendor == SOC_VENDOR_BROADCOM)
+    strcpy(tmp, BROADCOM_ASCII);
+  else
+    strcpy(tmp, ARM_ASCII);
+#endif
+
+  for(int i=0; i < NUMBER_OF_LINES; i++)
+    memcpy(art->art[i], tmp + i*LINE_SIZE, LINE_SIZE);
+
+  return art;
+}
+
+uint32_t longest_attribute_length(struct ascii* art) {
+  uint32_t max = 0;
+  uint64_t len = 0;
+
+  for(uint32_t i=0; i < art->n_attributes_set; i++) {
+    if(art->attributes[i]->value != NULL) {
+      len = strlen(ATTRIBUTE_FIELDS[art->attributes[i]->type]);
+      if(len > max) max = len;
+    }
+  }
+
+  return max;
+}
+
+#ifdef ARCH_X86
+void print_algorithm_intel(struct ascii* art, int n, bool* flag) {
+  for(int i=0; i < LINE_SIZE; i++) {
+    if(*flag) {
+      if(art->art[n][i] == ' ') {
+        *flag = false;
+        printf("%s%c%s", art->color2_ascii, art->ascii_chars[1], art->reset);
+      }
+      else {
+        printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
+      }
+    }
+    else {
+      if(art->art[n][i] != ' ' && art->art[n][i] != '\0') {
+        *flag = true;
+        printf("%c",' ');
+      }
+      else {
+        printf("%c",' ');
+      }
+    }
+  }
+}
+
+void print_algorithm_amd(struct ascii* art, int n, bool* flag) {
+  *flag = false; // dummy, just silence compiler error
+  
+  for(int i=0; i < LINE_SIZE; i++) {
+    if(art->art[n][i] == '@')
+      printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
+    else if(art->art[n][i] == '#')
+      printf("%s%c%s", art->color2_ascii, art->ascii_chars[1], art->reset);
+    else
+      printf("%c",art->art[n][i]);
+  }
+}
+
+void print_ascii_x86(struct ascii* art, uint32_t la, void (*callback_print_algorithm)(struct ascii* art, int i, bool* flag)) {  
+  int attr_to_print = 0;
+  int attr_type;
+  char* attr_value;
+  uint32_t space_right;
+  uint32_t space_up = (NUMBER_OF_LINES - art->n_attributes_set)/2;
+  uint32_t space_down = NUMBER_OF_LINES - art->n_attributes_set - space_up;
+  bool flag = false;
+
+  printf("\n");
+  for(uint32_t n=0;n<NUMBER_OF_LINES;n++) {
+    callback_print_algorithm(art, n, &flag);
+
+    if(n > space_up-1 && n < NUMBER_OF_LINES-space_down) {
+      attr_type = art->attributes[attr_to_print]->type;
+      attr_value = art->attributes[attr_to_print]->value;
+      attr_to_print++;
+      
+      space_right = 1 + (la - strlen(ATTRIBUTE_FIELDS[attr_type]));
+      printf("%s%s%s%*s%s%s%s\n", art->color1_text, ATTRIBUTE_FIELDS[attr_type], art->reset, space_right, "", art->color2_text, attr_value, art->reset);
+    }
+    else printf("\n");
+  }
+  printf("\n");
+}
+
+void print_ascii(struct ascii* art) {
+  uint32_t longest_attribute = longest_attribute_length(art);
+  
+  if(art->vendor == CPU_VENDOR_INTEL)
+    print_ascii_x86(art, longest_attribute, &print_algorithm_intel);
+  else if(art->vendor == CPU_VENDOR_AMD)
+    print_ascii_x86(art, longest_attribute, &print_algorithm_amd);
+  else {
+    printBug("Invalid CPU vendor: %d\n", art->vendor);
+  }
+  
+}
+
+bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct colors* cs) {
+  struct ascii* art = set_ascii(get_cpu_vendor(cpu), s, cs);
+  if(art == NULL)
+    return false;  
+  
+  char* uarch = get_str_uarch(cpu);
+  char* manufacturing_process = get_str_process(cpu);
+  char* sockets = get_str_sockets(cpu->topo);
+  char* max_frequency = get_str_freq(cpu->freq);
+  char* n_cores = get_str_topology(cpu, cpu->topo, false);
+  char* n_cores_dual = get_str_topology(cpu, cpu->topo, true);
+  char* cpu_name = get_str_cpu_name(cpu);
+  char* avx = get_str_avx(cpu);
+  char* fma = get_str_fma(cpu);
+
+
+  char* l1i = get_str_l1i(cpu->cach);
+  char* l1d = get_str_l1d(cpu->cach);
+  char* l2 = get_str_l2(cpu->cach);
+  char* l3 = get_str_l3(cpu->cach);
+  char* pp = get_str_peak_performance(cpu,cpu->topo,get_freq(cpu->freq));
+
+  setAttribute(art,ATTRIBUTE_NAME,cpu_name);
+  if(cpu->hv->present) {
+    setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
+  }
+  setAttribute(art,ATTRIBUTE_UARCH,uarch);
+  setAttribute(art,ATTRIBUTE_TECHNOLOGY,manufacturing_process);
+  setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency);
+  uint32_t socket_num = get_nsockets(cpu->topo);
+  if (socket_num > 1) {
+    setAttribute(art, ATTRIBUTE_SOCKETS, sockets);
+    setAttribute(art, ATTRIBUTE_NCORES,n_cores);
+    setAttribute(art, ATTRIBUTE_NCORES_DUAL, n_cores_dual);
+  }
+  else {
+    setAttribute(art,ATTRIBUTE_NCORES,n_cores);
+  }
+  setAttribute(art,ATTRIBUTE_AVX,avx);
+  setAttribute(art,ATTRIBUTE_FMA,fma);  
+  setAttribute(art,ATTRIBUTE_L1i,l1i);
+  setAttribute(art,ATTRIBUTE_L1d,l1d);
+  setAttribute(art,ATTRIBUTE_L2,l2);
+  if(l3 != NULL) {
+    setAttribute(art,ATTRIBUTE_L3,l3);
+  }
+  setAttribute(art,ATTRIBUTE_PEAK,pp);
+  
+  if(art->n_attributes_set > NUMBER_OF_LINES) {
+    printBug("The number of attributes set is bigger than the max that can be displayed");
+    return false;
+  }
+
+  print_ascii(art);
+
+  free(manufacturing_process);
+  free(max_frequency);
+  free(sockets);
+  free(n_cores);
+  free(n_cores_dual);
+  free(avx);
+  free(fma);
+  free(l1i);
+  free(l1d);
+  free(l2);
+  free(l3);
+  free(pp);
+
+  free(art->attributes);
+  free(art);
+
+  if(cs != NULL) free_colors_struct(cs);
+  free_cache_struct(cpu->cach);
+  free_topo_struct(cpu->topo);
+  free_freq_struct(cpu->freq);
+  free_cpuinfo_struct(cpu);
+
+  return true;
+}
+#endif
+
+#ifdef ARCH_ARM
+void print_algorithm_snapd_mtk(struct ascii* art, int n) {
+  for(int i=0; i < LINE_SIZE; i++) {
+    if(art->art[n][i] == '@')
+      printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
+    else if(art->art[n][i] == '#')
+      printf("%s%c%s", art->color2_ascii, art->ascii_chars[1], art->reset);  
+    else
+      printf("%c",art->art[n][i]);    
+  }
+}
+
+void print_algorithm_samsung(struct ascii* art, int n) {
+  int y_margin = 2;
+  int x_margin = 2 * y_margin;
+  
+  for(int i=0; i < LINE_SIZE; i++) {
+    if(art->art[n][i] == '#') {
+      printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
+    }
+    else if((n >= y_margin && n < NUMBER_OF_LINES-y_margin) && (i >= x_margin && i < LINE_SIZE-x_margin)) {
+      if(art->art[n][i] == '#')
+        printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);  
+      else
+        printf("%s%c%s","\x1b[48;2;10;10;10m" COLOR_FG_WHITE, art->art[n][i], art->reset);    
+    }
+    else
+      printf("%c", art->art[n][i]);
+  }
+}
+
+void print_algorithm_arm(struct ascii* art, int n) {
+  for(int i=0; i < LINE_SIZE; i++) {  
+    if(art->art[n][i] == '#')
+      printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);  
+    else
+      printf("%c",art->art[n][i]);    
+  }
+}
+
+void print_ascii_arm(struct ascii* art, uint32_t la, void (*callback_print_algorithm)(struct ascii* art, int n)) {  
+  int attr_to_print = 0;
+  int attr_type;
+  char* attr_value;
+  uint32_t limit_up;
+  uint32_t limit_down;
+  
+  uint32_t space_right;
+  uint32_t space_up = (NUMBER_OF_LINES - art->n_attributes_set)/2;
+  uint32_t space_down = NUMBER_OF_LINES - art->n_attributes_set - space_up;
+  if(art->n_attributes_set > NUMBER_OF_LINES) {
+    limit_up = 0;
+    limit_down = art->n_attributes_set;
+  }
+  else {
+    limit_up = space_up;
+    limit_down = NUMBER_OF_LINES-space_down;
+  }
+  bool add_space = false;
+  uint32_t len = max(art->n_attributes_set, NUMBER_OF_LINES);
+  
+  for(uint32_t n=0; n < len; n++) {
+    if(n >= art->additional_spaces && n < NUMBER_OF_LINES + art->additional_spaces)
+      callback_print_algorithm(art, n - art->additional_spaces);
+    else
+      printf("%*s", LINE_SIZE, "");
+
+    if(n >= limit_up && n < limit_down) {
+      attr_type = art->attributes[attr_to_print]->type;
+      attr_value = art->attributes[attr_to_print]->value;
+      attr_to_print++;
+       
+      if(attr_type == ATTRIBUTE_PEAK) {
+        add_space = false;
+      }
+      if(attr_type == ATTRIBUTE_CPU_NUM) {
+        printf("%s%s%s\n", art->color1_text, attr_value, art->reset);
+        add_space = true;
+      }      
+      else {
+        if(add_space) {
+          space_right = 1 + (la - strlen(ATTRIBUTE_FIELDS[attr_type]));
+          printf("  %s%s%s%*s%s%s%s\n", art->color1_text, ATTRIBUTE_FIELDS[attr_type], art->reset, space_right, "", art->color2_text, attr_value, art->reset);
+        }
+        else {
+          space_right = 2 + 1 + (la - strlen(ATTRIBUTE_FIELDS[attr_type]));
+          printf("%s%s%s%*s%s%s%s\n", art->color1_text, ATTRIBUTE_FIELDS[attr_type], art->reset, space_right, "", art->color2_text, attr_value, art->reset);
+        }
+      }
+    }
+    else printf("\n");
+  }
+
+}
+
+void print_ascii(struct ascii* art) {
+  uint32_t longest_attribute = longest_attribute_length(art);
+  
+  if(art->vendor == SOC_VENDOR_SNAPDRAGON || art->vendor == SOC_VENDOR_MEDIATEK || art->vendor == SOC_VENDOR_KIRIN || art->vendor == SOC_VENDOR_BROADCOM)
+    print_ascii_arm(art, longest_attribute, &print_algorithm_snapd_mtk);      
+  else if(art->vendor == SOC_VENDOR_EXYNOS)
+    print_ascii_arm(art, longest_attribute, &print_algorithm_samsung);      
+  else {
+    if(art->vendor != SOC_VENDOR_UNKNOWN)
+      printWarn("Invalid SOC vendor: %d\n", art->vendor);
+    print_ascii_arm(art, longest_attribute, &print_algorithm_arm);
+  }
+  
+}
+
+bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct colors* cs) {   
+  struct ascii* art = set_ascii(get_soc_vendor(cpu->soc), s, cs);
+  if(art == NULL)
+    return false;  
+  
+  char* manufacturing_process = get_str_process(cpu->soc);
+  char* soc_name = get_soc_name(cpu->soc);
+  char* features = get_str_features(cpu);
+  setAttribute(art,ATTRIBUTE_SOC,soc_name);
+  setAttribute(art,ATTRIBUTE_TECHNOLOGY,manufacturing_process);
+  
+  if(cpu->num_cpus == 1) {
+    char* uarch = get_str_uarch(cpu);
+    char* max_frequency = get_str_freq(cpu->freq);
+    char* n_cores = get_str_topology(cpu, cpu->topo, false);
+    /*
+     * char* l1i = get_str_l1i(cpu->cach);
+     * char* l1d = get_str_l1d(cpu->cach);
+     * char* l2 = get_str_l2(cpu->cach);
+     * char* l3 = get_str_l3(cpu->cach);
+     * Do not setAttribute for caches.
+     * Cache functionality may be implemented
+     * in the future
+    */
+  
+    setAttribute(art,ATTRIBUTE_UARCH,uarch);
+    setAttribute(art,ATTRIBUTE_FREQUENCY,max_frequency);
+    setAttribute(art,ATTRIBUTE_NCORES,n_cores);
+    if(features != NULL) {
+      setAttribute(art, ATTRIBUTE_FEATURES, features);    
+    }    
+  }
+  else {
+    struct cpuInfo* ptr = cpu;    
+    for(int i = 0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
+      char* uarch = get_str_uarch(ptr);
+      char* max_frequency = get_str_freq(ptr->freq);
+      char* n_cores = get_str_topology(ptr, ptr->topo, false);      
+      /*
+       * char* l1i = get_str_l1i(cpu->cach);
+       * char* l1d = get_str_l1d(cpu->cach);
+       * char* l2 = get_str_l2(cpu->cach);
+       * char* l3 = get_str_l3(cpu->cach);
+       * Do not setAttribute for caches.
+       * Cache functionality may be implemented
+       * in the future
+       */
+      
+      char* cpu_num = malloc(sizeof(char) * 9);
+      sprintf(cpu_num, "CPU %d:", i+1);
+      setAttribute(art, ATTRIBUTE_CPU_NUM, cpu_num);
+      setAttribute(art, ATTRIBUTE_UARCH, uarch);
+      setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
+      setAttribute(art, ATTRIBUTE_NCORES, n_cores);
+      if(features != NULL) {
+        setAttribute(art, ATTRIBUTE_FEATURES, features);    
+      }      
+    }
+  }
+  char* pp = get_str_peak_performance(cpu);
+  setAttribute(art,ATTRIBUTE_PEAK,pp);
+  
+  if(art->n_attributes_set > NUMBER_OF_LINES) {    
+    art->additional_spaces = (art->n_attributes_set - NUMBER_OF_LINES) / 2;
+  }
+  if(cpu->hv->present)
+    setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
+
+  print_ascii(art);
+
+  free(manufacturing_process);  
+  free(pp);
+
+  free(art->attributes);
+  free(art);
+
+  if(cs != NULL) free_colors_struct(cs);
+  free_cache_struct(cpu->cach);
+  free_topo_struct(cpu->topo);
+  free_cpuinfo_struct(cpu);
+
+  return true;
+}
+#endif
+
+bool print_cpufetch(struct cpuInfo* cpu, STYLE s, struct colors* cs) {
+  // Sanity check of ASCII arts
+  int len = sizeof(ASCII_ARRAY) / sizeof(ASCII_ARRAY[0]);
+  for(int i=0; i < len; i++) {
+    const char* ascii = ASCII_ARRAY[i];
+    if(strlen(ascii) != (NUMBER_OF_LINES * LINE_SIZE)) {
+      printBug("ASCII art %d is wrong! ASCII length: %d, expected length: %d", i, strlen(ascii), (NUMBER_OF_LINES * LINE_SIZE));
+      return false;
+    }
+  }
+  
+#ifdef ARCH_X86
+  return print_cpufetch_x86(cpu, s, cs);
+#elif ARCH_ARM
+  return print_cpufetch_arm(cpu, s, cs);  
+#endif
+}
--- a/src/common/printer.h
+++ b/src/common/printer.h
@@ -0,0 +1,24 @@
+#ifndef __PRINTER__
+#define __PRINTER__
+
+typedef int STYLE;
+
+#include "args.h"
+
+#ifdef ARCH_X86
+  #include "../x86/cpuid.h"
+#else
+  #include "../arm/midr.h"
+#endif
+
+#define COLOR_DEFAULT_INTEL "15,125,194:230,230,230:40,150,220:230,230,230"
+#define COLOR_DEFAULT_AMD   "250,250,250:0,154,102:250,250,250:0,154,102"
+#define COLOR_DEFAULT_ARM   "0,145,189:0,145,189:240,240,240:0,145,189"
+
+#ifdef ARCH_X86
+void print_levels(struct cpuInfo* cpu);
+#endif
+
+bool print_cpufetch(struct cpuInfo* cpu, STYLE s, struct colors* cs);
+
+#endif
--- a/src/common/udev.c
+++ b/src/common/udev.c
@@ -1,36 +1,18 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <errno.h>
-
+#include "udev.h"
 #include "global.h"
-#include "standart.h"
+#include "cpu.h"

-#define _PATH_SYS_SYSTEM    "/sys/devices/system"
-#define _PATH_SYS_CPU       _PATH_SYS_SYSTEM"/cpu"
-#define _PATH_ONE_CPU       _PATH_SYS_CPU"/cpu0"
-
-#define _PATH_FREQUENCY     _PATH_ONE_CPU"/cpufreq"
-#define _PATH_FREQUENCY_MAX _PATH_FREQUENCY"/cpuinfo_max_freq"
-#define _PATH_FREQUENCY_MIN _PATH_FREQUENCY"/cpuinfo_min_freq"
-
-#define DEFAULT_FILE_SIZE 4096
-
-long get_freq_from_file(char* path) {
+char* read_file(char* path, int* len) {
  int fd = open(path, O_RDONLY);
  
  if(fd == -1) {
-    perror("open");
-    printBug("Could not open '%s'", path);
-    return UNKNOWN;
+    return NULL;
  }

  //File exists, read it
  int bytes_read = 0;
  int offset = 0;
-  int block = 1;
+  int block = 128;
  char* buf = malloc(sizeof(char)*DEFAULT_FILE_SIZE);
  memset(buf, 0, sizeof(char)*DEFAULT_FILE_SIZE);

@@ -38,6 +20,27 @@ long get_freq_from_file(char* path) {
    offset += bytes_read;
  }    
  
+  if (close(fd) == -1) {
+    return NULL;
+  }
+  
+  *len = offset;
+  return buf;
+}
+
+long get_freq_from_file(char* path) {
+  int filelen;
+  char* buf;
+  if((buf = read_file(path, &filelen)) == NULL) {
+  #ifdef ARCH_X86
+    perror("open");
+    printBug("Could not open '%s'", path); 
+  #elif ARCH_ARM
+    printWarn("Could not open '%s'", path); 
+  #endif
+    return UNKNOWN_FREQ;
+  }
+
  char* end;
  errno = 0;
  long ret = strtol(buf, &end, 10);
@@ -45,7 +48,7 @@ long get_freq_from_file(char* path) {
    perror("strtol");
    printBug("Failed parsing '%s' file. Read data was: '%s'", path, buf);
    free(buf);
-    return UNKNOWN;
+    return UNKNOWN_FREQ;
  }
  
  // We will be getting the frequency in KHz
@@ -53,22 +56,22 @@ long get_freq_from_file(char* path) {
  // greater than 10 GHz or less than 100 MHz
  if(ret > 10000 * 1000 || ret <  100 * 1000) {
    printBug("Invalid data was read from file '%s': %ld\n", path, ret);
-    return UNKNOWN;
+    return UNKNOWN_FREQ;
  }
  
  free(buf);
-  if (close(fd) == -1) {
-    perror("close");
-    printErr("Closing '%s' failed\n", path);    
-  }
  
  return ret/1000;
 }

-long get_max_freq_from_file() {
-  return get_freq_from_file(_PATH_FREQUENCY_MAX);
+long get_max_freq_from_file(uint32_t core) {
+  char path[_PATH_FREQUENCY_MAX_LEN];
+  sprintf(path, "%s%s/cpu%d%s%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_FREQUENCY, _PATH_FREQUENCY_MAX);
+  return get_freq_from_file(path);
 }

-long get_min_freq_from_file() {
-  return get_freq_from_file(_PATH_FREQUENCY_MIN);
+long get_min_freq_from_file(uint32_t core) {
+  char path[_PATH_FREQUENCY_MAX_LEN];
+  sprintf(path, "%s%s/cpu%d%s%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_FREQUENCY, _PATH_FREQUENCY_MIN);
+  return get_freq_from_file(path);
 }
--- a/src/common/udev.h
+++ b/src/common/udev.h
@@ -0,0 +1,26 @@
+#ifndef __UDEV__
+#define __UDEV__
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#define _PATH_SYS_SYSTEM        "/sys/devices/system"
+#define _PATH_SYS_CPU           "/cpu"
+#define _PATH_FREQUENCY         "/cpufreq"
+#define _PATH_FREQUENCY_MAX     "/cpuinfo_max_freq"
+#define _PATH_FREQUENCY_MIN     "/cpuinfo_min_freq"
+
+#define _PATH_FREQUENCY_MAX_LEN 100
+#define DEFAULT_FILE_SIZE       4096
+
+char* read_file(char* path, int* len);
+long get_max_freq_from_file(uint32_t core);
+long get_min_freq_from_file(uint32_t core);
+
+#endif
--- a/src/extended.c
+++ b/src/extended.c
@@ -1,96 +0,0 @@
-#include <stdio.h>
-#include <string.h>
-#include "extended.h"
-
-char* get_str_cpu_name() {
-  uint32_t eax = 0;
-  uint32_t ebx = 0;
-  uint32_t ecx = 0;
-  uint32_t edx = 0;
-  
-  char *name = malloc(sizeof(char)*64);
-  memset(name, 0, 64);
-
-  //First, check we can use extended
-  eax = 0x80000000;
-  cpuid(&eax, &ebx, &ecx, &edx);
-  if(eax < 0x80000001) {
-    char* none = malloc(sizeof(char)*64);
-    sprintf(none,"Unknown");
-    return none;
-  }
-
-  //We can, fetch name
-  eax = 0x80000002;
-  cpuid(&eax, &ebx, &ecx, &edx);
-
-  name[__COUNTER__] = eax       & MASK;
-  name[__COUNTER__] = (eax>>8)  & MASK;
-  name[__COUNTER__] = (eax>>16) & MASK;
-  name[__COUNTER__] = (eax>>24) & MASK;
-  name[__COUNTER__] = ebx       & MASK;
-  name[__COUNTER__] = (ebx>>8)  & MASK;
-  name[__COUNTER__] = (ebx>>16) & MASK;
-  name[__COUNTER__] = (ebx>>24) & MASK;
-  name[__COUNTER__] = ecx       & MASK;
-  name[__COUNTER__] = (ecx>>8)  & MASK;
-  name[__COUNTER__] = (ecx>>16) & MASK;
-  name[__COUNTER__] = (ecx>>24) & MASK;
-  name[__COUNTER__] = edx       & MASK;
-  name[__COUNTER__] = (edx>>8)  & MASK;
-  name[__COUNTER__] = (edx>>16) & MASK;
-  name[__COUNTER__] = (edx>>24) & MASK;
-
-  eax = 0x80000003;
-  cpuid(&eax, &ebx, &ecx, &edx);
-
-  name[__COUNTER__] = eax       & MASK;
-  name[__COUNTER__] = (eax>>8)  & MASK;
-  name[__COUNTER__] = (eax>>16) & MASK;
-  name[__COUNTER__] = (eax>>24) & MASK;
-  name[__COUNTER__] = ebx       & MASK;
-  name[__COUNTER__] = (ebx>>8)  & MASK;
-  name[__COUNTER__] = (ebx>>16) & MASK;
-  name[__COUNTER__] = (ebx>>24) & MASK;
-  name[__COUNTER__] = ecx       & MASK;
-  name[__COUNTER__] = (ecx>>8)  & MASK;
-  name[__COUNTER__] = (ecx>>16) & MASK;
-  name[__COUNTER__] = (ecx>>24) & MASK;
-  name[__COUNTER__] = edx       & MASK;
-  name[__COUNTER__] = (edx>>8)  & MASK;
-  name[__COUNTER__] = (edx>>16) & MASK;
-  name[__COUNTER__] = (edx>>24) & MASK;
-
-  eax = 0x80000004;
-  cpuid(&eax, &ebx, &ecx, &edx);
-
-  name[__COUNTER__] = eax       & MASK;
-  name[__COUNTER__] = (eax>>8)  & MASK;
-  name[__COUNTER__] = (eax>>16) & MASK;
-  name[__COUNTER__] = (eax>>24) & MASK;
-  name[__COUNTER__] = ebx       & MASK;
-  name[__COUNTER__] = (ebx>>8)  & MASK;
-  name[__COUNTER__] = (ebx>>16) & MASK;
-  name[__COUNTER__] = (ebx>>24) & MASK;
-  name[__COUNTER__] = ecx       & MASK;
-  name[__COUNTER__] = (ecx>>8)  & MASK;
-  name[__COUNTER__] = (ecx>>16) & MASK;
-  name[__COUNTER__] = (ecx>>24) & MASK;
-  name[__COUNTER__] = edx       & MASK;
-  name[__COUNTER__] = (edx>>8)  & MASK;
-  name[__COUNTER__] = (edx>>16) & MASK;
-  name[__COUNTER__] = (edx>>24) & MASK;
-
-  name[__COUNTER__] = '\0';
-
-  //Remove unused characters  
-  char *str = name;
-  char *dest = name;
-  while (*str != '\0') {
-    while (*str == ' ' && *(str + 1) == ' ') str++;
-    *dest++ = *str++;
-  }
-  *dest = '\0';
-  
-  return name;
-}
--- a/src/extended.h
+++ b/src/extended.h
@@ -1,11 +0,0 @@
-#ifndef __EXTENDED__
-#define __EXTENDED__
-
-#define MASK 0xFF
-#include "cpuid.h"
-#include <stdint.h>
-#include <stdlib.h>
-
-char* get_str_cpu_name();
-
-#endif
--- a/src/main.c
+++ b/src/main.c
@@ -1,129 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-
-#include "args.h"
-#include "printer.h"
-#include "standart.h"
-#include "extended.h"
-#include "global.h"
-
-/***
-SAMPLE OUTPUT
-
-Name:        Intel Core i7-4790K
-Frequency:   4.0 GHz
-NºCores:     4 cores(8 threads)
-AXV:         AVX,AVX2
-SSE:         SSE,SSE2,SSE4.1,SSE4.2
-FMA:         FMA3
-AES:         Yes
-SHA:         No
-L1 Size:     32KB(Data)32KB(Instructions)
-L2 Size:     512KB
-L3 Size:     8MB
-Peak FLOPS:  512 GFLOP/s(in simple precision)
-
-***/
-
-static const char* VERSION = "0.47";
-
-void print_help(int argc, char *argv[]) {
-  printf("Usage: %s [--version] [--help] [--style STYLE]\n\
-Options: \n\
-  --style    Set logo style color\n\
-    default:   Default style color\n\
-    dark:      Dark style color\n\
-    none:      Don't use colors\n\
-  --help     Print this help and exit\n\
-  --version  Print cpufetch version and exit\n",
-  argv[0]);
-}
-
-void print_version() {
-  printf("cpufetch v%s\n",VERSION);
-}
-
-int main(int argc, char* argv[]) {
-  if(!parseArgs(argc,argv))
-    return EXIT_FAILURE;
-
-  if(showHelp()) {
-    print_help(argc, argv);
-    return EXIT_SUCCESS;
-  }
-
-  if(showVersion()) {
-    print_version();
-    return EXIT_SUCCESS;
-  }
-  
-  set_log_level(verbose_enabled());
-
-  struct cpuInfo* cpu = get_cpu_info();
-  if(cpu == NULL)
-    return EXIT_FAILURE;
-
-  struct cache* cach = get_cache_info(cpu);
-  if(cach == NULL)
-    return EXIT_FAILURE;
-  
-  struct frequency* freq = get_frequency_info(cpu);
-  if(freq == NULL)
-    return EXIT_FAILURE;
-  
-  struct topology* topo = get_topology_info(cpu);
-  if(topo == NULL)
-    return EXIT_FAILURE;
-  
-  struct ascii* art = set_ascii(get_cpu_vendor(cpu),getStyle());
-  if(art == NULL)
-    return EXIT_FAILURE;
-
-  char* cpuName = get_str_cpu_name();
-  char* maxFrequency = get_str_freq(freq);
-  char* nCores = get_str_topology(topo);
-  char* avx = get_str_avx(cpu);
-  char* sse = get_str_sse(cpu);
-  char* fma = get_str_fma(cpu);
-  char* aes = get_str_aes(cpu);
-  char* sha = get_str_sha(cpu);
-  char* l1 = get_str_l1(cach);
-  char* l2 = get_str_l2(cach);
-  char* l3 = get_str_l3(cach);
-  char* pp = get_str_peak_performance(cpu,topo,get_freq(freq));
-
-  setAttribute(art,ATTRIBUTE_NAME,cpuName);
-  setAttribute(art,ATTRIBUTE_FREQUENCY,maxFrequency);
-  setAttribute(art,ATTRIBUTE_NCORES,nCores);
-  setAttribute(art,ATTRIBUTE_AVX,avx);
-  setAttribute(art,ATTRIBUTE_SSE,sse);
-  setAttribute(art,ATTRIBUTE_FMA,fma);
-  setAttribute(art,ATTRIBUTE_AES,aes);
-  setAttribute(art,ATTRIBUTE_SHA,sha);
-  setAttribute(art,ATTRIBUTE_L1,l1);
-  setAttribute(art,ATTRIBUTE_L2,l2);
-  setAttribute(art,ATTRIBUTE_L3,l3);
-  setAttribute(art,ATTRIBUTE_PEAK,pp);
-
-  print_ascii(art);
-
-  free(cpuName);
-  free(maxFrequency);
-  free(nCores);
-  free(avx);
-  free(sse);
-  free(fma);
-  free(aes);
-  free(sha);
-  free(l1);
-  free(l2);
-  free(l3);
-  free(pp);
-
-  free(cpu);
-  free(art);
-  free_cache_struct(cach);
-  free_freq_struct(freq);
-
-  return EXIT_SUCCESS;
-}
--- a/src/printer.c
+++ b/src/printer.c
@@ -1,187 +0,0 @@
-#include <stdlib.h>
-#include <string.h>
-#include <stdio.h>
-#include <stdbool.h>
-
-#include "printer.h"
-#include "ascii.h"
-#include "global.h"
-
-#define COL_NONE            ""
-#define COL_INTEL_DEFAULT_1 "\x1b[36;1m"
-#define COL_INTEL_DEFAULT_2 "\x1b[37;1m"
-#define COL_INTEL_DARK_1    "\x1b[34;1m"
-#define COL_INTEL_DARK_2    "\x1b[30m"
-#define COL_AMD_DEFAULT_1   "\x1b[37;1m"
-#define COL_AMD_DEFAULT_2   "\x1b[31;1m"
-#define COL_AMD_DARK_1      "\x1b[30;1m"
-#define COL_AMD_DARK_2      "\x1b[32;1m"
-#define RESET               "\x1b[0m"
-
-#define TITLE_NAME      "Name:       "
-#define TITLE_FREQUENCY "Frequency:  "
-#define TITLE_NCORES    "N.Cores:    "
-#define TITLE_AVX       "AVX:        "
-#define TITLE_SSE       "SSE:        "
-#define TITLE_FMA       "FMA:        "
-#define TITLE_AES       "AES:        "
-#define TITLE_SHA       "SHA:        "
-#define TITLE_L1        "L1 Size:    "
-#define TITLE_L2        "L2 Size:    "
-#define TITLE_L3        "L3 Size:    "
-#define TITLE_PEAK      "Peak FLOPS: "
-
-/*** CENTER TEXT ***/
-#define LINES_SPACE_UP   4
-#define LINES_SPACE_DOWN 4
-
-static const char* ATTRIBUTE_FIELDS [ATTRIBUTE_COUNT] =  {  TITLE_NAME, TITLE_FREQUENCY,
-                                                            TITLE_NCORES, TITLE_AVX, TITLE_SSE,
-                                                            TITLE_FMA, TITLE_AES, TITLE_SHA,
-                                                            TITLE_L1, TITLE_L2, TITLE_L3,
-                                                            TITLE_PEAK };
-
-static const int ATTRIBUTE_LIST[ATTRIBUTE_COUNT] =  { ATTRIBUTE_NAME, ATTRIBUTE_FREQUENCY,
-                                                        ATTRIBUTE_NCORES, ATTRIBUTE_AVX, ATTRIBUTE_SSE,
-                                                        ATTRIBUTE_FMA, ATTRIBUTE_AES, ATTRIBUTE_SHA,
-                                                        ATTRIBUTE_L1, ATTRIBUTE_L2, ATTRIBUTE_L3,
-                                                        ATTRIBUTE_PEAK };
-
-struct ascii {
-  char art[NUMBER_OF_LINES][LINE_SIZE];
-  char color1[10];
-  char color2[10];
-  char reset[10];
-  char* atributes[ATTRIBUTE_COUNT];
-  VENDOR vendor;
-};
-
-void setAttribute(struct ascii* art, int type, char* value) {
-  int i = 0;
-  while(i < ATTRIBUTE_COUNT && type != ATTRIBUTE_LIST[i])
-    i++;
-  if(i != ATTRIBUTE_COUNT)
-    art->atributes[i] = value;
-  else
-    printBug("Setting attribute failed because it was not found");
-}
-
-struct ascii* set_ascii(VENDOR cpuVendor, STYLE style) {
-  /*** Check that number of lines of ascii art matches the number
-  of spaces plus the number of lines filled with text ***/
-  if(LINES_SPACE_UP+LINES_SPACE_DOWN+ATTRIBUTE_COUNT != NUMBER_OF_LINES) {
-    printBug("Number of lines do not match (%d vs %d)",LINES_SPACE_UP+LINES_SPACE_DOWN+ATTRIBUTE_COUNT,NUMBER_OF_LINES);
-    return NULL;
-  }
-
-  char *COL_DEFAULT_1, *COL_DEFAULT_2, *COL_DARK_1, *COL_DARK_2;
-  struct ascii* art = malloc(sizeof(struct ascii));
-  art->vendor = cpuVendor;
-  strcpy(art->reset,RESET);
-  
-  if(cpuVendor == VENDOR_INTEL) {
-    COL_DEFAULT_1 = COL_INTEL_DEFAULT_1;
-    COL_DEFAULT_2 = COL_INTEL_DEFAULT_2;
-    COL_DARK_1 = COL_INTEL_DARK_1;
-    COL_DARK_2 = COL_INTEL_DARK_2;
-  }
-  else {
-    COL_DEFAULT_1 = COL_AMD_DEFAULT_1;
-    COL_DEFAULT_2 = COL_AMD_DEFAULT_2;
-    COL_DARK_1 = COL_AMD_DARK_1;
-    COL_DARK_2 = COL_AMD_DARK_2;    
-  }
-  
-  switch(style) {
-    case STYLE_NONE:
-        strcpy(art->color1,COL_NONE);
-        strcpy(art->color2,COL_NONE);
-        break; 
-    case STYLE_EMPTY:
-      #ifdef _WIN32
-        strcpy(art->color1,COL_NONE);
-        strcpy(art->color2,COL_NONE);  
-        art->reset[0] = '\0';
-        break;
-      #endif
-    case STYLE_DEFAULT:
-      strcpy(art->color1,COL_DEFAULT_1);
-      strcpy(art->color2,COL_DEFAULT_2);
-      break;
-    case STYLE_DARK:
-      strcpy(art->color1,COL_DARK_1);
-      strcpy(art->color2,COL_DARK_2);
-      break;
-    default:
-      printBug("Found invalid style (%d)",style);
-      return NULL;    
-  }
-  
-  char tmp[NUMBER_OF_LINES*LINE_SIZE];
-  if(cpuVendor == VENDOR_INTEL) strcpy(tmp, INTEL_ASCII);    
-  else strcpy(tmp, AMD_ASCII);    
-    for(int i=0; i < NUMBER_OF_LINES; i++)
-      strncpy(art->art[i], tmp + i*LINE_SIZE, LINE_SIZE); 
-    
-  return art;
-}
-
-void print_ascii_intel(struct ascii* art) {
-  bool flag = false;
-
-  for(int n=0;n<NUMBER_OF_LINES;n++) {
-
-    /*** PRINT ASCII-ART ***/
-    for(int i=0;i<LINE_SIZE;i++) {
-      if(flag) {
-        if(art->art[n][i] == ' ') {
-          flag = false;
-          printf("%c",art->art[n][i]);
-        }
-        else
-          printf("%s%c%s", art->color1, art->art[n][i], art->reset);
-      }
-      else {
-        if(art->art[n][i] != ' ') {
-          flag = true;
-          printf("%s%c%s", art->color2, art->art[n][i], art->reset);
-        }
-        else
-          printf("%c",art->art[n][i]);
-      }
-    }
-
-    /*** PRINT ATTRIBUTE ***/
-    if(n>LINES_SPACE_UP-1 && n<NUMBER_OF_LINES-LINES_SPACE_DOWN)
-      printf("%s%s%s%s%s\n",art->color1,ATTRIBUTE_FIELDS[n-LINES_SPACE_UP],art->color2,art->atributes[n-LINES_SPACE_UP],art->reset);
-    else printf("\n");
-  }
-}
-
-void print_ascii_amd(struct ascii* art) {
-
-  for(int n=0;n<NUMBER_OF_LINES;n++) {
-    /*** PRINT ASCII-ART ***/
-    for(int i=0;i<LINE_SIZE;i++) {
-      if(art->art[n][i] == '@')
-        printf("%s%c%s", art->color1, art->art[n][i], art->reset);
-      else if(art->art[n][i] == '#')
-        printf("%s%c%s", art->color2, art->art[n][i], art->reset);
-      else
-        printf("%c",art->art[n][i]);
-    }
-
-    /*** PRINT ATTRIBUTE ***/
-    if(n>LINES_SPACE_UP-1 && n<NUMBER_OF_LINES-LINES_SPACE_DOWN)
-      printf("%s%s%s%s%s\n",art->color1,ATTRIBUTE_FIELDS[n-LINES_SPACE_UP],art->color2,art->atributes[n-LINES_SPACE_UP], art->reset);
-    else printf("\n");
-  }
-
-}
-
-void print_ascii(struct ascii* art) {
-  if(art->vendor == VENDOR_INTEL)
-    print_ascii_intel(art);
-  else
-    print_ascii_amd(art);
-}
--- a/src/printer.h
+++ b/src/printer.h
@@ -1,37 +0,0 @@
-#ifndef __PRINTER__
-#define __PRINTER__
-
-#include "standart.h"
-#include "ascii.h"
-
-#define ATTRIBUTE_COUNT    12
-#define ATTRIBUTE_NAME      0
-#define ATTRIBUTE_FREQUENCY 1
-#define ATTRIBUTE_NCORES    2
-#define ATTRIBUTE_AVX       3
-#define ATTRIBUTE_SSE       4
-#define ATTRIBUTE_FMA       5
-#define ATTRIBUTE_AES       6
-#define ATTRIBUTE_SHA       7
-#define ATTRIBUTE_L1        8
-#define ATTRIBUTE_L2        9
-#define ATTRIBUTE_L3        10
-#define ATTRIBUTE_PEAK      11
-
-typedef int STYLE;
-#define STYLES_COUNT 3
-
-#define STYLE_EMPTY   -2
-#define STYLE_INVALID -1
-#define STYLE_DEFAULT  0
-#define STYLE_DARK     1
-#define STYLE_NONE     2
-
-struct ascii;
-
-static const int STYLES_CODE_LIST [STYLES_COUNT] = {STYLE_DEFAULT, STYLE_DARK};
-struct ascii* set_ascii(VENDOR cpuVendor, STYLE style);
-void print_ascii(struct ascii* art);
-void setAttribute(struct ascii* art, int type, char* value);
-
-#endif
--- a/src/standart.c
+++ b/src/standart.c
@@ -1,668 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <string.h>
-#include <assert.h>
-#include <stdbool.h>
-
-#include "standart.h"
-#include "cpuid.h"
-#include "global.h"
-
-#ifndef _WIN32
-#include "udev.h"
-#endif
-
-#define VENDOR_INTEL_STRING "GenuineIntel"
-#define VENDOR_AMD_STRING   "AuthenticAMD"
-
-#define STRING_YES        "Yes"
-#define STRING_NO         "No"
-#define STRING_UNKNOWN    "Unknown"
-#define STRING_NONE       "None"
-#define STRING_MEGAHERZ   "MHz"
-#define STRING_GIGAHERZ   "GHz"
-#define STRING_KILOBYTES  "KB"
-#define STRING_MEGABYTES  "MB"
-
-#define MASK 0xFF
-
-/*
- * cpuid reference: http://www.sandpile.org/x86/cpuid.htm
- */
-
-struct cpuInfo {
-  bool AVX;
-  bool AVX2;
-  bool AVX512;
-  bool SSE;
-  bool SSE2;
-  bool SSE3;
-  bool SSSE3;
-  bool SSE4a;
-  bool SSE4_1;
-  bool SSE4_2;
-  bool FMA3;
-  bool FMA4;
-  bool AES;
-  bool SHA;
-
-  VENDOR cpu_vendor;
-  
-  //  Max cpuids levels
-  uint32_t maxLevels;
-  // Max cpuids extended levels
-  uint32_t maxExtendedLevels;
-};
-
-struct cache {
-  int32_t L1i;
-  int32_t L1d;
-  int32_t L2;
-  int32_t L3;
-};
-
-struct frequency {
-  int64_t base;
-  int64_t max;
-};
-
-struct topology {
-  uint32_t physical_cores;
-  uint32_t logical_cores;
-  uint32_t smt;
-  bool ht;
-};
-
-void init_cpu_info(struct cpuInfo* cpu) {
-  cpu->AVX    = false;
-  cpu->AVX2   = false;
-  cpu->AVX512 = false;
-  cpu->SSE    = false;
-  cpu->SSE2   = false;
-  cpu->SSE3   = false;
-  cpu->SSSE3  = false;
-  cpu->SSE4a  = false;
-  cpu->SSE4_1 = false;
-  cpu->SSE4_2 = false;
-  cpu->FMA3   = false;
-  cpu->FMA4   = false;
-  cpu->AES    = false;
-  cpu->SHA    = false;
-}
-
-void get_cpu_vendor_internal(char* name, uint32_t eax,uint32_t ebx,uint32_t ecx,uint32_t edx) {
-  name[__COUNTER__] = ebx       & MASK;
-  name[__COUNTER__] = (ebx>>8)  & MASK;
-  name[__COUNTER__] = (ebx>>16) & MASK;
-  name[__COUNTER__] = (ebx>>24) & MASK;
-
-  name[__COUNTER__] = edx       & MASK;
-  name[__COUNTER__] = (edx>>8)  & MASK;
-  name[__COUNTER__] = (edx>>16) & MASK;
-  name[__COUNTER__] = (edx>>24) & MASK;
-
-  name[__COUNTER__] = ecx       & MASK;
-  name[__COUNTER__] = (ecx>>8)  & MASK;
-  name[__COUNTER__] = (ecx>>16) & MASK;
-  name[__COUNTER__] = (ecx>>24) & MASK;
-}
-
-struct cpuInfo* get_cpu_info() {
-  struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
-  init_cpu_info(cpu);
-  uint32_t eax = 0;
-  uint32_t ebx = 0;
-  uint32_t ecx = 0;
-  uint32_t edx = 0;
-
-  //Get max cpuid level
-  cpuid(&eax, &ebx, &ecx, &edx);
-  cpu->maxLevels = eax;
-
-  //Fill vendor
-  char name[13];
-  memset(name,0,13);
-  get_cpu_vendor_internal(name, eax,ebx,ecx,edx);
-  
-  if(strcmp(VENDOR_INTEL_STRING,name) == 0)
-    cpu->cpu_vendor = VENDOR_INTEL;
-  else if (strcmp(VENDOR_AMD_STRING,name) == 0)
-    cpu->cpu_vendor = VENDOR_AMD;  
-  else {
-    cpu->cpu_vendor = VENDOR_INVALID;
-    printErr("Unknown CPU vendor: %s", name);
-    return NULL;
-  }
-
-  //Get max extended level
-  eax = 0x80000000;
-  ebx = 0;
-  ecx = 0;
-  edx = 0;
-  cpuid(&eax, &ebx, &ecx, &edx);
-  cpu->maxExtendedLevels = eax;  
-
-  //Fill instructions support
-  if (cpu->maxLevels >= 0x00000001){
-    eax = 0x00000001;
-    cpuid(&eax, &ebx, &ecx, &edx);
-    cpu->SSE    = (edx & ((int)1 << 25)) != 0;
-    cpu->SSE2   = (edx & ((int)1 << 26)) != 0;
-    cpu->SSE3   = (ecx & ((int)1 <<  0)) != 0;
-
-    cpu->SSSE3  = (ecx & ((int)1 <<  9)) != 0;
-    cpu->SSE4_1 = (ecx & ((int)1 << 19)) != 0;
-    cpu->SSE4_2 = (ecx & ((int)1 << 20)) != 0;
-
-    cpu->AES    = (ecx & ((int)1 << 25)) != 0;
-
-    cpu->AVX    = (ecx & ((int)1 << 28)) != 0;
-    cpu->FMA3   = (ecx & ((int)1 << 12)) != 0;
-  }
-  else {
-    printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
-  }
-  
-  if (cpu->maxLevels >= 0x00000007){
-    eax = 0x00000007;
-    ecx = 0x00000000;
-    cpuid(&eax, &ebx, &ecx, &edx);
-    cpu->AVX2         = (ebx & ((int)1 <<  5)) != 0;
-    cpu->SHA          = (ebx & ((int)1 << 29)) != 0;
-    cpu->AVX512       = (((ebx & ((int)1 << 16)) != 0) ||
-                        ((ebx & ((int)1 << 28)) != 0)  ||
-                        ((ebx & ((int)1 << 26)) != 0)  ||
-                        ((ebx & ((int)1 << 27)) != 0)  ||
-                        ((ebx & ((int)1 << 31)) != 0)  ||
-                        ((ebx & ((int)1 << 30)) != 0)  ||
-                        ((ebx & ((int)1 << 17)) != 0)  ||
-                        ((ebx & ((int)1 << 21)) != 0));
-  }
-  else {
-    printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000007, cpu->maxLevels);    
-  }
-  
-  if (cpu->maxExtendedLevels >= 0x80000001){
-      eax = 0x80000001;
-      cpuid(&eax, &ebx, &ecx, &edx);
-      cpu->SSE4a = (ecx & ((int)1 <<  6)) != 0;
-      cpu->FMA4  = (ecx & ((int)1 << 16)) != 0;
-  }
-  else {
-    printWarn("Can't read features information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000001, cpu->maxExtendedLevels);        
-  }
-
-  return cpu;
-}
-
-struct topology* get_topology_info(struct cpuInfo* cpu) {
-  struct topology* topo = malloc(sizeof(struct cache));
-  uint32_t eax = 0;
-  uint32_t ebx = 0;
-  uint32_t ecx = 0;
-  uint32_t edx = 0;
-  int32_t type;
-  
-  if (cpu->maxLevels >= 0x00000001) {
-    eax = 0x00000001;
-    cpuid(&eax, &ebx, &ecx, &edx);
-    topo->ht = edx & (1 << 28);
-  }
-  else {
-    printWarn("Can't read HT information from cpuid (needed level is 0x%.8X, max is 0x%.8X). Assuming HT is disabled", 0x00000001, cpu->maxLevels); 
-    topo->ht = false;
-  }
-    
-  switch(cpu->cpu_vendor) {
-    case VENDOR_INTEL:  
-      if (cpu->maxLevels >= 0x0000000B) {
-        //TODO: This idea only works with no NUMA systems  
-        eax = 0x0000000B;
-        ecx = 0x00000000;
-        cpuid(&eax, &ebx, &ecx, &edx);
-        type = (ecx >> 8) & 0xFF;
-        if (type != 1) {
-          printBug("Unexpected type in cpuid 0x0000000B (expected 1, got %d)", type);     
-          return NULL;
-        }        
-        topo->smt = ebx & 0xFFFF;
-                
-  
-        eax = 0x0000000B;
-        ecx = 0x00000001;
-        cpuid(&eax, &ebx, &ecx, &edx); 
-        type = (ecx >> 8) & 0xFF;
-        if (type < 2) {       
-          printBug("Unexpected type in cpuid 0x0000000B (expected < 2, got %d)", type);     
-          return NULL;
-        }
-        topo->logical_cores = ebx & 0xFFFF;
-        topo->physical_cores = topo->logical_cores / topo->smt;
-      }
-      else {
-        printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x0000000B, cpu->maxLevels); 
-        topo->physical_cores = 1;
-        topo->logical_cores = 1;
-        topo->smt = 1;
-      }
-      break;
-    case VENDOR_AMD:  
-      printBug("Unimplemented!");  
-      break;
-    default:
-      printBug("Cant get topology because VENDOR is empty");
-      return NULL;
-  }
-  
-  return topo;
-}
-
-// see https://stackoverflow.com/questions/12594208/c-program-to-determine-levels-size-of-cache
-struct cache* get_cache_info(struct cpuInfo* cpu) {
-  struct cache* cach = malloc(sizeof(struct cache));    
-  uint32_t eax = 0;
-  uint32_t ebx = 0;
-  uint32_t ecx = 0;
-  uint32_t edx = 0;
-  
-  // We suppose there are 4 caches (at most)
-  for(int i=0; i < 4; i++) {
-    eax = 4; // get cache info
-    ebx = 0;
-    ecx = i; // cache id
-    edx = 0;
-      
-    cpuid(&eax, &ebx, &ecx, &edx); 
-      
-    int32_t cache_type = eax & 0x1F;
-      
-    // If its 0, we tried fetching a non existing cache
-    if (cache_type > 0) {
-      int32_t cache_level = (eax >>= 5) & 0x7;
-      int32_t cache_is_self_initializing = (eax >>= 3) & 0x1; // does not need SW initialization
-      int32_t cache_is_fully_associative = (eax >>= 1) & 0x1;
-      uint32_t cache_sets = ecx + 1;
-      uint32_t cache_coherency_line_size = (ebx & 0xFFF) + 1;
-      uint32_t cache_physical_line_partitions = ((ebx >>= 12) & 0x3FF) + 1;
-      uint32_t cache_ways_of_associativity = ((ebx >>= 10) & 0x3FF) + 1;
-        
-      int32_t cache_total_size = cache_ways_of_associativity * cache_physical_line_partitions * cache_coherency_line_size * cache_sets;  
-        
-      switch (cache_type) {
-        case 1: // Data Cache (We assume this is L1d)
-          if(cache_level != 1) {
-            printBug("Found data cache at level %d (expected 1)", cache_level);
-            return NULL;
-          }
-          cach->L1d = cache_total_size; 
-          break;
-            
-        case 2: // Instruction Cache (We assume this is L1i)
-          if(cache_level != 1) {
-            printBug("Found instruction cache at level %d (expected 1)", cache_level);
-            return NULL;
-          }
-          cach->L1i = cache_total_size;
-          break;
-          
-        case 3: // Unified Cache (This may be L2 or L3)
-          if(cache_level == 2) cach->L2 = cache_total_size;
-          else if(cache_level == 3) cach->L3 = cache_total_size;
-          else {
-            printBug("Found unified cache at level %d (expected == 2 or 3)", cache_level);
-            return NULL;
-          }
-          break;
-          
-        default: // Unknown Type Cache
-          printBug("Unknown Type Cache found at ID %d", i);
-          return NULL;
-      }
-    }    
-    else if(i == 2) cach->L2 = UNKNOWN;
-    else if(i == 3) cach->L3 = UNKNOWN; 
-    else {
-      printBug("Could not find cache ID %d", i);
-      return NULL;    
-    }    
-  }
-  
-  // Sanity checks. If we read values greater than this, they can't be valid ones
-  // The values were chosen by me
-  if(cach->L1i > 64 * 1024) {
-    printBug("Invalid L1i size: %dKB\n", cach->L1i/1024);
-    return NULL;
-  }
-  if(cach->L1d > 64 * 1024) {
-    printBug("Invalid L1d size: %dKB\n", cach->L1d/1024);
-    return NULL;
-  }
-  if(cach->L2 != UNKNOWN && cach->L2 > 2 * 1048576) {
-    printBug("Invalid L2 size: %dMB\n", cach->L2/(1048576));
-    return NULL;
-  }
-  if(cach->L3 != UNKNOWN && cach->L3 > 100 * 1048576) {
-    printBug("Invalid L3 size: %dMB\n", cach->L3/(1048576));
-    return NULL;
-  }
-  
-  return cach;
-}
-
-struct frequency* get_frequency_info(struct cpuInfo* cpu) {
-  struct frequency* freq = malloc(sizeof(struct frequency));
-  
-  if(cpu->maxLevels < 0x16) {
-    #ifdef _WIN32
-      printErr("Can't read frequency information from cpuid (needed level is %d, max is %d)", 0x16, cpu->maxLevels);
-      freq->base = UNKNOWN;
-      freq->max = UNKNOWN;
-    #else
-      printWarn("Can't read frequency information from cpuid (needed level is %d, max is %d). Using udev", 0x16, cpu->maxLevels);
-      freq->base = UNKNOWN;
-      freq->max = get_max_freq_from_file();
-    #endif
-  }
-  else {
-    uint32_t eax = 0x16;
-    uint32_t ebx = 0;
-    uint32_t ecx = 0;
-    uint32_t edx = 0;
-    
-    cpuid(&eax, &ebx, &ecx, &edx);
-    
-    freq->base = eax;
-    freq->max = ebx;    
-  }
-  
-  return freq;
-}
-
-int64_t get_freq(struct frequency* freq) {
-  return freq->max;
-}
-
-VENDOR get_cpu_vendor(struct cpuInfo* cpu) {
-  return cpu->cpu_vendor;
-}
-
-void debug_cpu_info(struct cpuInfo* cpu) {
-  printf("AVX=%s\n", cpu->AVX ? "true" : "false");
-  printf("AVX2=%s\n", cpu->AVX2 ? "true" : "false");
-  printf("AVX512=%s\n\n", cpu->AVX512 ? "true" : "false");
-
-  printf("SSE=%s\n", cpu->SSE ? "true" : "false");
-  printf("SSE2=%s\n", cpu->SSE2 ? "true" : "false");
-  printf("SSE3=%s\n", cpu->SSE3 ? "true" : "false");
-  printf("SSSE3=%s\n", cpu->SSSE3 ? "true" : "false");
-  printf("SSE4a=%s\n", cpu->SSE4a ? "true" : "false");
-  printf("SSE4_1=%s\n", cpu->SSE4_1 ? "true" : "false");
-  printf("SSE4_2=%s\n\n", cpu->SSE4_2 ? "true" : "false");
-
-  printf("FMA3=%s\n", cpu->FMA3 ? "true" : "false");
-  printf("FMA4=%s\n\n", cpu->FMA4 ? "true" : "false");
-
-  printf("AES=%s\n", cpu->AES ? "true" : "false");
-  printf("SHA=%s\n", cpu->SHA ? "true" : "false");
-}
-
-void debug_cache(struct cache* cach) {
-  printf("L1i=%dB\n",cach->L1i);
-  printf("L1d=%dB\n",cach->L1d);
-  printf("L2=%dB\n",cach->L2);
-  printf("L3=%dB\n",cach->L3);
-}
-
-void debug_frequency(struct frequency* freq) {
-  #ifdef _WIN32
-    printf("maxf=%I64d Mhz\n",freq->max);
-    printf("basef=%I64d Mhz\n",freq->base);
-  #else
-    printf("maxf=%ld Mhz\n",freq->max);
-    printf("basef=%ld Mhz\n",freq->base);
-  #endif
-}
-
-/*** STRING FUNCTIONS ***/
-
-char* get_str_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t freq) {
-  /***
-  PP = PeakPerformance
-  SP = SinglePrecision
-
-  PP(SP) =
-  N_CORES                             *
-  FREQUENCY                           *
-  2(Two vector units)                 *
-  2(If cpu has fma)                   *
-  16(If AVX512), 8(If AVX), 4(If SSE) *
-
-  ***/
-
-  //7 for GFLOP/s and 6 for digits,eg 412.14
-  uint32_t size = 7+6+1+1;
-  assert(strlen(STRING_UNKNOWN)+1 <= size);
-  char* string = malloc(sizeof(char)*size);
-
-  //First check we have consistent data
-  if(freq == UNKNOWN) {
-    snprintf(string,strlen(STRING_UNKNOWN)+1,STRING_UNKNOWN);
-    return string;
-  }
-
-  double flops = topo->physical_cores*(freq*1000000);
-  
-  // Intel USUALLY has two VPUs. I have never seen an AMD 
-  // with two VPUs.
-  if(cpu->cpu_vendor == VENDOR_INTEL) flops = flops * 2; 
-
-  if(cpu->FMA3 || cpu->FMA4)
-    flops = flops*2;
-
-  if(cpu->AVX512)
-    flops = flops*16;
-  else if(cpu->AVX || cpu->AVX2)
-    flops = flops*8;
-  else if(cpu->SSE)
-    flops = flops*4;
-
-  if(flops >= (double)1000000000000.0)
-    snprintf(string,size,"%.2f TFLOP/s",flops/1000000000000);
-  else if(flops >= 1000000000.0)
-    snprintf(string,size,"%.2f GFLOP/s",flops/1000000000);
-  else
-    snprintf(string,size,"%.2f MFLOP/s",flops/1000000);
-  return string;
-}
-
-char* get_str_topology(struct topology* topo) {
-  char* string;
-  if(topo->smt > 1) {
-    //3 for digits, 8 for ' cores (', 3 for digits, 9 for ' threads)'
-    uint32_t size = 3+8+3+9+1;
-    string = malloc(sizeof(char)*size);
-    snprintf(string, size, "%d cores (%d threads)",topo->physical_cores,topo->logical_cores);
-  }
-  else {
-    uint32_t size = 3+7+1;
-    string = malloc(sizeof(char)*size);
-    snprintf(string, size, "%d cores",topo->physical_cores);
-  }
-  return string;
-}
-
-char* get_str_avx(struct cpuInfo* cpu) {
-  //If all AVX are available, it will use up to 15
-  char* string = malloc(sizeof(char)*15+1);
-  if(!cpu->AVX)
-    snprintf(string,2+1,"No");
-  else if(!cpu->AVX2)
-    snprintf(string,3+1,"AVX");
-  else if(!cpu->AVX512)
-    snprintf(string,8+1,"AVX,AVX2");
-  else
-    snprintf(string,15+1,"AVX,AVX2,AVX512");
-
-  return string;
-}
-
-char* get_str_sse(struct cpuInfo* cpu) {
-  uint32_t last = 0;
-  uint32_t SSE_sl = 4;
-  uint32_t SSE2_sl = 5;
-  uint32_t SSE3_sl = 5;
-  uint32_t SSSE3_sl = 6;
-  uint32_t SSE4a_sl = 6;
-  uint32_t SSE4_1_sl = 7;
-  uint32_t SSE4_2_sl = 7;
-  char* string = malloc(sizeof(char)*SSE_sl+SSE2_sl+SSE3_sl+SSSE3_sl+SSE4a_sl+SSE4_1_sl+SSE4_2_sl+1);
-
-  if(cpu->SSE) {
-      snprintf(string+last,SSE_sl+1,"SSE,");
-      last+=SSE_sl;
-  }
-  if(cpu->SSE2) {
-      snprintf(string+last,SSE2_sl+1,"SSE2,");
-      last+=SSE2_sl;
-  }
-  if(cpu->SSE3) {
-      snprintf(string+last,SSE3_sl+1,"SSE3,");
-      last+=SSE3_sl;
-  }
-  if(cpu->SSSE3) {
-      snprintf(string+last,SSSE3_sl+1,"SSSE3,");
-      last+=SSSE3_sl;
-  }
-  if(cpu->SSE4a) {
-      snprintf(string+last,SSE4a_sl+1,"SSE4a,");
-      last+=SSE4a_sl;
-  }
-  if(cpu->SSE4_1) {
-      snprintf(string+last,SSE4_1_sl+1,"SSE4_1,");
-      last+=SSE4_1_sl;
-  }
-  if(cpu->SSE4_2) {
-      snprintf(string+last,SSE4_2_sl+1,"SSE4_2,");
-      last+=SSE4_2_sl;
-  }
-
-  //Purge last comma
-  string[last-1] = '\0';
-  return string;
-}
-
-char* get_str_fma(struct cpuInfo* cpu) {
-  char* string = malloc(sizeof(char)*9+1);
-  if(!cpu->FMA3)
-    snprintf(string,2+1,"No");
-  else if(!cpu->FMA4)
-    snprintf(string,4+1,"FMA3");
-  else
-    snprintf(string,9+1,"FMA3,FMA4");
-
-  return string;
-}
-
-char* get_str_aes(struct cpuInfo* cpu) {
-  char* string = malloc(sizeof(char)*3+1);
-  if(cpu->AES)
-    snprintf(string,3+1,STRING_YES);
-  else
-    snprintf(string,2+1,STRING_NO);
-  return string;
-}
-
-char* get_str_sha(struct cpuInfo* cpu) {
-  char* string = malloc(sizeof(char)*3+1);
-  if(cpu->SHA)
-    snprintf(string,3+1,STRING_YES);
-  else
-    snprintf(string,2+1,STRING_NO);
-  return string;
-}
-
-// String functions
-char* get_str_l1(struct cache* cach) {
-  // 2*2 for digits, 4 for two 'KB' and 6 for '(D)' and '(I)'
-  uint32_t size = (2*2+4+6+1);
-  int32_t sanity_ret;
-  char* string = malloc(sizeof(char)*size);
-  sanity_ret = snprintf(string,size,"%d"STRING_KILOBYTES"(D)%d"STRING_KILOBYTES"(I)",cach->L1d/1024,cach->L1i/1024);
-  assert(sanity_ret > 0);
-  return string;
-}
-
-char* get_str_l2(struct cache* cach) {
-  if(cach->L2 == UNKNOWN) {
-    char* string = malloc(sizeof(char) * 5);
-    snprintf(string, 5, STRING_NONE);
-    return string;
-  }
-  else {
-    int32_t sanity_ret;  
-    char* string;
-    if(cach->L2/1024 >= 1024) {
-      //1 for digit, 2 for 'MB'
-      uint32_t size = (1+2+1);    
-      string = malloc(sizeof(char)*size);
-      sanity_ret = snprintf(string,size,"%d"STRING_MEGABYTES,cach->L2/(1048576));    
-    }
-    else {
-      //4 for digits, 2 for 'KB'
-      uint32_t size = (4+2+1);    
-      string = malloc(sizeof(char)*size);
-      sanity_ret = snprintf(string,size,"%d"STRING_KILOBYTES,cach->L2/1024);  
-    }    
-    assert(sanity_ret > 0);    
-    return string;
-  }
-}
-
-char* get_str_l3(struct cache* cach) {
-  if(cach->L3 == UNKNOWN) {
-    char* string = malloc(sizeof(char) * 5);
-    snprintf(string, 5, STRING_NONE);
-    return string;
-  }
-  else {
-    int32_t sanity_ret;  
-    char* string;
-    if(cach->L3/1024 >= 1024) {
-      //1 for digit, 2 for 'MB'
-      uint32_t size = (1+2+1);    
-      string = malloc(sizeof(char)*size);
-      sanity_ret = snprintf(string,size,"%d"STRING_MEGABYTES,cach->L3/(1048576));    
-    }
-    else {
-      //4 for digits, 2 for 'KB'
-      uint32_t size = (4+2+1);    
-      string = malloc(sizeof(char)*size);
-      sanity_ret = snprintf(string,size,"%d"STRING_KILOBYTES,cach->L3/1024);  
-    }    
-    assert(sanity_ret > 0);    
-    return string;
-  }
-}
-
-char* get_str_freq(struct frequency* freq) {
-  //Max 3 digits and 3 for '(M/G)Hz' plus 1 for '\0'
-  uint32_t size = (4+3+1);
-  assert(strlen(STRING_UNKNOWN)+1 <= size);
-  char* string = malloc(sizeof(char)*size);
-  if(freq->max == UNKNOWN)
-    snprintf(string,strlen(STRING_UNKNOWN)+1,STRING_UNKNOWN);
-  else if(freq->max >= 1000)
-    snprintf(string,size,"%.2f"STRING_GIGAHERZ,(float)(freq->max)/1000);
-  else
-    snprintf(string,size,"%.2f"STRING_MEGAHERZ,(float)(freq->max));
-  return string;
-}
-
-void free_cache_struct(struct cache* cach) {
-  free(cach);
-}
-
-void free_freq_struct(struct frequency* freq) {
-  free(freq);
-}
--- a/src/standart.h
+++ b/src/standart.h
@@ -1,52 +0,0 @@
-#ifndef __01h__
-#define __01h__
-
-#include <stdint.h>
-
-#define VENDOR_EMPTY   0
-#define VENDOR_INTEL   1
-#define VENDOR_AMD     2
-#define VENDOR_INVALID 3
-
-#define UNKNOWN -1
-
-struct cpuInfo;
-struct frequency;
-struct cache;
-struct topology;
-
-typedef int32_t VENDOR;
-
-struct cpuInfo* get_cpu_info();
-VENDOR get_cpu_vendor(struct cpuInfo* cpu);
-int64_t get_freq(struct frequency* freq);
-struct cache* get_cache_info(struct cpuInfo* cpu);
-struct frequency* get_frequency_info(struct cpuInfo* cpu);
-struct topology* get_topology_info(struct cpuInfo* cpu);
-
-char* get_str_ncores(struct cpuInfo* cpu);
-char* get_str_avx(struct cpuInfo* cpu);
-char* get_str_sse(struct cpuInfo* cpu);
-char* get_str_fma(struct cpuInfo* cpu);
-char* get_str_aes(struct cpuInfo* cpu);
-char* get_str_sha(struct cpuInfo* cpu);
-
-char* get_str_l1(struct cache* cach);
-char* get_str_l2(struct cache* cach);
-char* get_str_l3(struct cache* cach);
-
-char* get_str_freq(struct frequency* freq);
-
-char* get_str_topology(struct topology* topo);
-
-char* get_str_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t freq);
-
-void free_cpuinfo_struct(struct cpuInfo* cpu);
-void free_cache_struct(struct cache* cach);
-void free_freq_struct(struct frequency* freq);
-
-void debug_cpu_info(struct cpuInfo* cpu);
-void debug_cache(struct cache* cach);
-void debug_frequency(struct frequency* freq);
-
-#endif
--- a/src/udev.h
+++ b/src/udev.h
@@ -1,7 +0,0 @@
-#ifndef __UDEV__
-#define __UDEV__
-
-long get_max_freq_from_file();
-long get_min_freq_from_file();
-
-#endif
--- a/src/x86/apic.c
+++ b/src/x86/apic.c
@@ -0,0 +1,352 @@
+#ifdef _WIN32
+#include <windows.h>
+#else
+#define _GNU_SOURCE
+#include <sched.h>
+#endif
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+
+#include "apic.h"
+#include "cpuid_asm.h"
+#include "../common/global.h"
+
+/*
+ * bit_scan_reverse and create_mask code taken from:
+ * https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html
+ */
+unsigned char bit_scan_reverse(uint32_t* index, uint64_t mask) {
+  for(uint64_t i = (8 * sizeof(uint64_t)); i > 0; i--) {
+    if((mask & (1LL << (i-1))) != 0) {
+      *index = (uint64_t) (i-1);
+      break;
+    }
+  }
+  return (unsigned char) (mask != 0);
+}
+
+uint32_t create_mask(uint32_t num_entries, uint32_t *mask_width) {
+  uint32_t i = 0;
+  uint64_t k = 0;
+
+  // NearestPo2(numEntries) is the nearest power of 2 integer that is not less than numEntries
+  // The most significant bit of (numEntries * 2 -1) matches the above definition
+
+  k = (uint64_t)(num_entries) * 2 -1;
+
+  if (bit_scan_reverse(&i, k) == 0) {
+    if (mask_width) *mask_width = 0;
+    return 0;
+  }
+
+  if (mask_width) *mask_width = i;
+  if (i == 31) return (uint32_t ) -1;
+
+  return (1 << i) -1;
+}
+
+uint32_t get_apic_id(bool x2apic_id) {
+  uint32_t eax = 0;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+  
+  if(x2apic_id) {
+    eax = 0x0000000B;
+    cpuid(&eax, &ebx, &ecx, &edx);
+    return edx;
+  }
+  else {
+    eax = 0x00000001;
+    cpuid(&eax, &ebx, &ecx, &edx);
+    return (ebx >> 24);
+  }
+}
+
+bool bind_to_cpu(int cpu_id) {
+  #ifdef _WIN32
+    HANDLE process = GetCurrentProcess();
+    DWORD_PTR processAffinityMask = 1 << cpu_id;
+    return SetProcessAffinityMask(process, processAffinityMask);
+  #else    
+    cpu_set_t currentCPU;
+    CPU_ZERO(&currentCPU);
+    CPU_SET(cpu_id, &currentCPU);
+    if (sched_setaffinity (0, sizeof(currentCPU), &currentCPU) == -1) {
+      perror("sched_setaffinity");
+      return false;
+    }
+    return true;
+  #endif  
+}
+
+bool fill_topo_masks_apic(struct topology* topo) {
+  uint32_t eax = 0x00000001;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+  uint32_t core_plus_smt_id_max_cnt;
+  uint32_t core_id_max_cnt;
+  uint32_t smt_id_per_core_max_cnt;
+  
+  cpuid(&eax, &ebx, &ecx, &edx);
+  
+  core_plus_smt_id_max_cnt = (ebx >> 16) & 0xFF;
+  
+  eax = 0x00000004;
+  ecx = 0;
+  cpuid(&eax, &ebx, &ecx, &edx);
+  
+  core_id_max_cnt = (eax >> 26) + 1;
+  smt_id_per_core_max_cnt = core_plus_smt_id_max_cnt / core_id_max_cnt; 
+            
+  topo->apic->smt_mask = create_mask(smt_id_per_core_max_cnt, &(topo->apic->smt_mask_width));    
+  topo->apic->core_mask = create_mask(core_id_max_cnt,&(topo->apic->pkg_mask_shift));
+  topo->apic->pkg_mask_shift += topo->apic->smt_mask_width;
+  topo->apic->core_mask <<= topo->apic->smt_mask_width;
+  topo->apic->pkg_mask = (-1) ^ (topo->apic->core_mask | topo->apic->smt_mask);
+  
+  return true;
+}
+
+bool fill_topo_masks_x2apic(struct topology* topo) {
+  int32_t level_type;
+  int32_t level_shift;
+  
+  int32_t coreplus_smt_mask = 0;
+  bool level2 = false;
+  bool level1 = false;
+  
+  uint32_t eax = 0;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+  uint32_t i = 0;
+  
+  while(true) {
+    eax = 0x0000000B;
+    ecx = i;
+    cpuid(&eax, &ebx, &ecx, &edx);
+    if(ebx == 0) break;
+    
+    level_type = (ecx >> 8) & 0xFF;
+    level_shift = eax & 0xFFF; 
+    
+    switch(level_type) {      
+      case 1: // SMT
+        topo->apic->smt_mask = ~(0xFFFFFFFF << level_shift);
+        topo->apic->smt_mask_width = level_shift;
+        topo->smt_supported = ebx & 0xFFFF;
+        level1 = true;
+        break;
+      case 2: // Core
+        coreplus_smt_mask = ~(0xFFFFFFFF << level_shift);
+        topo->apic->pkg_mask_shift =  level_shift;
+        topo->apic->pkg_mask = (-1) ^ coreplus_smt_mask;
+        level2 = true;
+        break;
+      default:
+        printErr("Found invalid level when querying topology: %d", level_type);
+        break;
+    }
+    
+    i++; // sublevel to query
+  }
+  
+  if (level1 && level2) {
+    topo->apic->core_mask = coreplus_smt_mask ^ topo->apic->smt_mask;
+  }
+  else if (!level2 && level1) {
+    topo->apic->core_mask = 0;
+    topo->apic->pkg_mask_shift = topo->apic->smt_mask_width;
+    topo->apic->pkg_mask =  (-1) ^ topo->apic->smt_mask;
+  }
+  else {
+    printErr("SMT level was not found when querying topology");
+    return false;
+  }
+
+  return true;
+}
+
+// Not a very elegant solution. The width should always be as long
+// as the number of cores, but in the case of Xeon Phi KNL it is not
+uint32_t max_apic_id_size(uint32_t** cache_id_apic, struct topology* topo) {
+  uint32_t max = 0;
+  
+  for(int i=0; i < topo->cach->max_cache_level; i++) {
+    for(int j=0; j < topo->total_cores; j++) {          
+      if(cache_id_apic[j][i] > max) max = cache_id_apic[j][i];
+    }
+  }
+  
+  max++;
+  if(max > (uint32_t) topo->total_cores) return max;
+  return topo->total_cores;
+}
+
+bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cache_id_apic, struct topology* topo) {
+  uint32_t size = max_apic_id_size(cache_id_apic, topo);
+  uint32_t* sockets = malloc(sizeof(uint32_t) * size);
+  uint32_t* smt = malloc(sizeof(uint32_t) * size);
+  uint32_t* apic_id = malloc(sizeof(uint32_t) * size);
+  uint32_t num_caches = 0;
+  
+  memset(sockets, 0, sizeof(uint32_t) * size);
+  memset(smt, 0, sizeof(uint32_t) * size);  
+  memset(apic_id, 0, sizeof(uint32_t) * size);  
+  
+  // System topology
+  for(int i=0; i < topo->total_cores; i++) {
+    sockets[apic_pkg[i]] = 1;
+    smt[apic_smt[i]] = 1;
+  }
+  for(int i=0; i < topo->total_cores; i++) {
+    if(sockets[i] != 0)
+      topo->sockets++;
+    if(smt[i] != 0)
+      topo->smt_available++;
+  }
+  
+  topo->logical_cores = topo->total_cores / topo->sockets;
+  topo->physical_cores = topo->logical_cores / topo->smt_available;
+  
+  // Cache topology
+  for(int i=0; i < topo->cach->max_cache_level; i++) {
+    num_caches = 0;
+    memset(apic_id, 0, sizeof(uint32_t) * size);
+    
+    for(int c=0; c < topo->total_cores; c++) {      
+      apic_id[cache_id_apic[c][i]]++;
+    }
+    for(uint32_t c=0; c < size; c++) {      
+      if(apic_id[c] > 0) num_caches++;
+    }
+    
+    topo->cach->cach_arr[i]->num_caches = num_caches;
+  }
+  
+  free(sockets);
+  free(smt);
+  free(apic_id);
+  
+  return true;
+}
+
+void get_cache_topology_from_apic(struct topology* topo) {  
+  uint32_t eax = 0x00000004;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+     
+  for(int i=0; i < topo->cach->max_cache_level; i++) { 
+    eax = 0x00000004;
+    ecx = i;
+    
+    cpuid(&eax, &ebx, &ecx, &edx);
+  
+    uint32_t SMTMaxCntPerEachCache = ((eax >> 14) & 0x7FF) + 1;
+    uint32_t dummy;
+    topo->apic->cache_select_mask[i] = create_mask(SMTMaxCntPerEachCache,&dummy);
+  }
+}
+
+bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) { 
+  uint32_t apic_id;
+  uint32_t* apic_pkg = malloc(sizeof(uint32_t) * topo->total_cores);
+  uint32_t* apic_core = malloc(sizeof(uint32_t) * topo->total_cores);
+  uint32_t* apic_smt = malloc(sizeof(uint32_t) * topo->total_cores);
+  uint32_t** cache_smt_id_apic = malloc(sizeof(uint32_t*) * topo->total_cores);
+  uint32_t** cache_id_apic = malloc(sizeof(uint32_t*) * topo->total_cores);
+  bool x2apic_id = cpu->maxLevels >= 0x0000000B;
+  
+  for(int i=0; i < topo->total_cores; i++) {
+    cache_smt_id_apic[i] = malloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
+    cache_id_apic[i] = malloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
+  }
+  topo->apic->cache_select_mask = malloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
+  topo->apic->cache_id_apic = malloc(sizeof(uint32_t) * (topo->cach->max_cache_level));
+  
+  if(x2apic_id) {
+    if(!fill_topo_masks_x2apic(topo))
+      return false;
+  }
+  else {
+    if(!fill_topo_masks_apic(topo))
+      return false;    
+  }
+  
+  get_cache_topology_from_apic(topo);  
+  
+  for(int i=0; i < topo->total_cores; i++) {
+    if(!bind_to_cpu(i)) {
+      printErr("Failed binding to CPU %d", i);
+      return false;
+    }
+    apic_id = get_apic_id(x2apic_id);
+    
+    apic_pkg[i] = (apic_id & topo->apic->pkg_mask) >> topo->apic->pkg_mask_shift;
+    apic_core[i] = (apic_id & topo->apic->core_mask) >> topo->apic->smt_mask_width;
+    apic_smt[i] = apic_id & topo->apic->smt_mask;
+    
+    for(int c=0; c < topo->cach->max_cache_level; c++) {
+      cache_smt_id_apic[i][c] = apic_id & topo->apic->cache_select_mask[c];
+      cache_id_apic[i][c] = apic_id & (-1 ^ topo->apic->cache_select_mask[c]);
+    }
+  }
+  
+  /* DEBUG
+  for(int i=0; i < topo->cach->max_cache_level; i++) {
+    printf("[CACH %1d]", i);
+    for(int j=0; j < topo->total_cores; j++)
+      printf("[%03d]", cache_id_apic[j][i]);
+    printf("\n");
+  }  
+  for(int i=0; i < topo->total_cores; i++)
+    printf("[%2d] 0x%.8X\n", i, apic_pkg[i]);
+  printf("\n");
+  for(int i=0; i < topo->total_cores; i++)
+    printf("[%2d] 0x%.8X\n", i, apic_core[i]);
+  printf("\n");
+  for(int i=0; i < topo->total_cores; i++)
+    printf("[%2d] 0x%.8X\n", i, apic_smt[i]);*/
+    
+  
+  bool ret = build_topo_from_apic(apic_pkg, apic_smt, cache_id_apic, topo);
+  
+  // Assumption: If we cant get smt_available, we assume it is equal to smt_supported...
+  if (!x2apic_id) {
+    printWarn("Can't read SMT from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x0000000B, cpu->maxLevels); 
+    topo->smt_supported = topo->smt_available;
+  }
+  
+  free(apic_pkg);
+  free(apic_core);
+  free(apic_smt);
+  for(int i=0; i < topo->total_cores; i++) {
+    free(cache_smt_id_apic[i]);
+    free(cache_id_apic[i]);
+  }
+  free(cache_smt_id_apic);
+  free(cache_id_apic);
+    
+  return ret;
+} 
+
+uint32_t is_smt_enabled_amd(struct topology* topo) {
+  uint32_t id;
+  
+  for(int i = 0; i < topo->total_cores; i++) {
+    if(!bind_to_cpu(i)) {
+      printErr("Failed binding to CPU %d", i);
+      return false;
+    }
+    id = get_apic_id(false) & 1; // get the last bit
+    if(id == 1) return 2; // We assume there isn't any AMD CPU with more than 2th per core.
+  }
+  
+  return 1;  
+}
--- a/src/x86/apic.h
+++ b/src/x86/apic.h
@@ -0,0 +1,20 @@
+#ifndef __APIC__
+#define __APIC__
+
+#include <stdbool.h>
+#include "cpuid.h"
+
+struct apic {
+  uint32_t pkg_mask;
+  uint32_t pkg_mask_shift;
+  uint32_t core_mask;
+  uint32_t smt_mask_width;
+  uint32_t smt_mask;
+  uint32_t* cache_select_mask;
+  uint32_t* cache_id_apic;
+};
+
+bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo);
+uint32_t is_smt_enabled_amd(struct topology* topo);
+
+#endif
--- a/src/x86/cpuid.c
+++ b/src/x86/cpuid.c
@@ -0,0 +1,884 @@
+#ifdef _WIN32
+  #include <windows.h>
+#else
+  #include "../common/udev.h"
+  #include <unistd.h>
+#endif
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+#include <stdbool.h>
+
+#include "cpuid.h"
+#include "cpuid_asm.h"
+#include "../common/global.h"
+#include "apic.h"
+#include "uarch.h"
+
+#define CPU_VENDOR_INTEL_STRING "GenuineIntel"
+#define CPU_VENDOR_AMD_STRING   "AuthenticAMD"
+
+static const char *hv_vendors_string[] = {
+  [HV_VENDOR_KVM]       = "KVMKVMKVM",
+  [HV_VENDOR_QEMU]      = "TCGTCGTCGTCG",
+  [HV_VENDOR_HYPERV]    = "Microsoft Hv",
+  [HV_VENDOR_VMWARE]    = "VMwareVMware",
+  [HV_VENDOR_XEN]       = "XenVMMXenVMM",
+  [HV_VENDOR_PARALLELS] = "lrpepyh vr",
+  [HV_VENDOR_INVALID]   = NULL
+};
+
+static char *hv_vendors_name[] = {
+  [HV_VENDOR_KVM]       = "KVM",
+  [HV_VENDOR_QEMU]      = "QEMU",
+  [HV_VENDOR_HYPERV]    = "Microsoft Hyper-V",
+  [HV_VENDOR_VMWARE]    = "VMware",
+  [HV_VENDOR_XEN]       = "Xen",
+  [HV_VENDOR_PARALLELS] = "Parallels",
+  [HV_VENDOR_INVALID]   = "Unknown"
+};
+
+#define STRING_UNKNOWN    "Unknown"
+
+#define HYPERVISOR_NAME_MAX_LENGTH 17
+
+#define MASK 0xFF
+
+/*
+ * cpuid reference: http://www.sandpile.org/x86/cpuid.htm
+ * cpuid amd: https://www.amd.com/system/files/TechDocs/25481.pdf
+ */
+
+void init_topology_struct(struct topology* topo, struct cache* cach) {
+  topo->total_cores = 0;
+  topo->physical_cores = 0;
+  topo->logical_cores = 0;
+  topo->smt_available = 0;
+  topo->smt_supported = 0;
+  topo->sockets = 0;
+  topo->apic = malloc(sizeof(struct apic));
+  topo->cach = cach;
+}
+
+void init_cache_struct(struct cache* cach) {
+  cach->L1i = malloc(sizeof(struct cach));
+  cach->L1d = malloc(sizeof(struct cach));
+  cach->L2 = malloc(sizeof(struct cach));
+  cach->L3 = malloc(sizeof(struct cach));
+  
+  cach->cach_arr = malloc(sizeof(struct cach*) * 4);
+  cach->cach_arr[0] = cach->L1i;
+  cach->cach_arr[1] = cach->L1d;
+  cach->cach_arr[2] = cach->L2;
+  cach->cach_arr[3] = cach->L3;
+  
+  cach->max_cache_level = 0;
+  cach->L1i->exists = false;
+  cach->L1d->exists = false;
+  cach->L2->exists = false;
+  cach->L3->exists = false;
+}
+
+void get_name_cpuid(char* name, uint32_t reg1, uint32_t reg2, uint32_t reg3) {
+  uint32_t c = 0;
+  
+  name[c++] = reg1       & MASK;
+  name[c++] = (reg1>>8)  & MASK;
+  name[c++] = (reg1>>16) & MASK;
+  name[c++] = (reg1>>24) & MASK;
+
+  name[c++] = reg2       & MASK;
+  name[c++] = (reg2>>8)  & MASK;
+  name[c++] = (reg2>>16) & MASK;
+  name[c++] = (reg2>>24) & MASK;
+
+  name[c++] = reg3       & MASK;
+  name[c++] = (reg3>>8)  & MASK;
+  name[c++] = (reg3>>16) & MASK;
+  name[c++] = (reg3>>24) & MASK;
+}
+
+char* get_str_cpu_name_internal() {
+  uint32_t eax = 0;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+  uint32_t c = 0;
+  
+  char * name = malloc(sizeof(char) * CPU_NAME_MAX_LENGTH);
+  memset(name, 0, CPU_NAME_MAX_LENGTH);
+  
+  for(int i=0; i < 3; i++) {    
+    eax = 0x80000002 + i;
+    cpuid(&eax, &ebx, &ecx, &edx);
+  
+    name[c++] = eax       & MASK;
+    name[c++] = (eax>>8)  & MASK;
+    name[c++] = (eax>>16) & MASK;
+    name[c++] = (eax>>24) & MASK;
+    name[c++] = ebx       & MASK;
+    name[c++] = (ebx>>8)  & MASK;
+    name[c++] = (ebx>>16) & MASK;
+    name[c++] = (ebx>>24) & MASK;
+    name[c++] = ecx       & MASK;
+    name[c++] = (ecx>>8)  & MASK;
+    name[c++] = (ecx>>16) & MASK;
+    name[c++] = (ecx>>24) & MASK;
+    name[c++] = edx       & MASK;
+    name[c++] = (edx>>8)  & MASK;
+    name[c++] = (edx>>16) & MASK;
+    name[c++] = (edx>>24) & MASK;        
+  }
+  name[c] = '\0';
+  
+  //Remove unused characters  
+  char *str = name;
+  char *dest = name;
+  // Remove spaces before name
+  while (*str != '\0' && *str == ' ')str++; 
+  // Remove spaces between the name and after it
+  while (*str != '\0') {
+    while (*str == ' ' && *(str + 1) == ' ') str++;
+    *dest++ = *str++;
+  }
+  *dest = '\0';
+  
+  return name;
+}
+
+struct uarch* get_cpu_uarch(struct cpuInfo* cpu) {
+  uint32_t eax = 0x00000001;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+  
+  cpuid(&eax, &ebx, &ecx, &edx);
+   
+  uint32_t stepping = eax & 0xF;
+  uint32_t model = (eax >> 4) & 0xF;
+  uint32_t emodel = (eax >> 16) & 0xF;
+  uint32_t family = (eax >> 8) & 0xF;
+  uint32_t efamily = (eax >> 20) & 0xFF;
+  
+  return get_uarch_from_cpuid(cpu, efamily, family, emodel, model, (int)stepping);
+}
+
+struct hypervisor* get_hp_info(bool hv_present) {
+  struct hypervisor* hv = malloc(sizeof(struct hypervisor));
+  if(!hv_present) {
+    hv->present = false;
+    return hv;    
+  }
+  
+  hv->present = true; 
+  
+  uint32_t eax = 0x40000000;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+
+  cpuid(&eax, &ebx, &ecx, &edx);
+
+  char name[13];
+  memset(name, 0, 13);
+  get_name_cpuid(name, ebx, ecx, edx);
+  
+  bool found = false;
+  uint8_t len = sizeof(hv_vendors_string) / sizeof(hv_vendors_string[0]);
+  
+  for(uint8_t v=0; v < len && !found; v++) {
+    if(strcmp(hv_vendors_string[v], name) == 0) {
+      hv->hv_vendor = v;
+      found = true;    
+    }
+  }
+  
+  if(!found) {
+    hv->hv_vendor = HV_VENDOR_INVALID;
+    printWarn("Unknown hypervisor vendor: %s", name);    
+  }
+  
+  hv->hv_name = hv_vendors_name[hv->hv_vendor];
+  
+  return hv;
+}
+
+struct cpuInfo* get_cpu_info() {
+  struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
+  struct features* feat = malloc(sizeof(struct features));
+  cpu->feat = feat;
+  
+  bool *ptr = &(feat->AES);
+  for(uint32_t i = 0; i < sizeof(struct features)/sizeof(bool); i++, ptr++) {
+    *ptr = false;
+  }
+  
+  uint32_t eax = 0;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+
+  //Get max cpuid level
+  cpuid(&eax, &ebx, &ecx, &edx);
+  cpu->maxLevels = eax;
+
+  //Fill vendor
+  char name[13];
+  memset(name,0,13);
+  get_name_cpuid(name, ebx, edx, ecx);
+  
+  if(strcmp(CPU_VENDOR_INTEL_STRING,name) == 0)
+    cpu->cpu_vendor = CPU_VENDOR_INTEL;
+  else if (strcmp(CPU_VENDOR_AMD_STRING,name) == 0)
+    cpu->cpu_vendor = CPU_VENDOR_AMD;  
+  else {
+    cpu->cpu_vendor = CPU_VENDOR_INVALID;
+    printErr("Unknown CPU vendor: %s", name);
+    return NULL;
+  }
+
+  //Get max extended level
+  eax = 0x80000000;
+  ebx = 0;
+  ecx = 0;
+  edx = 0;
+  cpuid(&eax, &ebx, &ecx, &edx);
+  cpu->maxExtendedLevels = eax;  
+
+  //Fill instructions support
+  if (cpu->maxLevels >= 0x00000001){
+    eax = 0x00000001;
+    cpuid(&eax, &ebx, &ecx, &edx);
+    feat->SSE    = (edx & ((int)1 << 25)) != 0;
+    feat->SSE2   = (edx & ((int)1 << 26)) != 0;
+    feat->SSE3   = (ecx & ((int)1 <<  0)) != 0;
+
+    feat->SSSE3  = (ecx & ((int)1 <<  9)) != 0;
+    feat->SSE4_1 = (ecx & ((int)1 << 19)) != 0;
+    feat->SSE4_2 = (ecx & ((int)1 << 20)) != 0;
+
+    feat->AES    = (ecx & ((int)1 << 25)) != 0;
+
+    feat->AVX    = (ecx & ((int)1 << 28)) != 0;
+    feat->FMA3   = (ecx & ((int)1 << 12)) != 0;
+    
+    bool hv_present = (ecx & ((int)1 << 31)) != 0;    
+    if((cpu->hv = get_hp_info(hv_present)) == NULL)
+      return NULL;
+  }
+  else {
+    printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
+  }
+  
+  if (cpu->maxLevels >= 0x00000007){
+    eax = 0x00000007;
+    ecx = 0x00000000;
+    cpuid(&eax, &ebx, &ecx, &edx);
+    feat->AVX2         = (ebx & ((int)1 <<  5)) != 0;
+    feat->SHA          = (ebx & ((int)1 << 29)) != 0;
+    feat->AVX512       = (((ebx & ((int)1 << 16)) != 0) ||
+                        ((ebx & ((int)1 << 28)) != 0)  ||
+                        ((ebx & ((int)1 << 26)) != 0)  ||
+                        ((ebx & ((int)1 << 27)) != 0)  ||
+                        ((ebx & ((int)1 << 31)) != 0)  ||
+                        ((ebx & ((int)1 << 30)) != 0)  ||
+                        ((ebx & ((int)1 << 17)) != 0)  ||
+                        ((ebx & ((int)1 << 21)) != 0));
+  }
+  else {
+    printWarn("Can't read features information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000007, cpu->maxLevels);    
+  }
+  
+  if (cpu->maxExtendedLevels >= 0x80000001){
+    eax = 0x80000001;
+    cpuid(&eax, &ebx, &ecx, &edx);
+    feat->SSE4a = (ecx & ((int)1 <<  6)) != 0;
+    feat->FMA4  = (ecx & ((int)1 << 16)) != 0;
+  }
+  else {
+    printWarn("Can't read features information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000001, cpu->maxExtendedLevels);        
+  }
+  
+  if (cpu->maxExtendedLevels >= 0x80000004){
+    cpu->cpu_name = get_str_cpu_name_internal();
+  }
+  else {    
+    cpu->cpu_name = malloc(sizeof(char)*8);
+    sprintf(cpu->cpu_name,"Unknown");
+    printWarn("Can't read cpu name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);        
+  }
+  
+  cpu->arch = get_cpu_uarch(cpu);
+  cpu->freq = get_frequency_info(cpu);
+  cpu->cach = get_cache_info(cpu);
+  cpu->topo = get_topology_info(cpu, cpu->cach);
+  
+  return cpu;
+}
+
+bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {    
+  if(cpu->maxExtendedLevels >= 0x8000001D) {  
+    uint32_t i, eax, ebx, ecx, edx, num_sharing_cache, cache_type, cache_level;
+    
+    i = 0;
+    do {
+      eax = 0x8000001D;
+      ebx = 0;
+      ecx = i; // cache id
+      edx = 0;
+      
+      cpuid(&eax, &ebx, &ecx, &edx); 
+      
+      cache_type = eax & 0x1F;            
+      
+      if(cache_type > 0) {
+        num_sharing_cache = ((eax >> 14) & 0xFFF) + 1;  
+        cache_level = (eax >>= 5) & 0x7;            
+        
+        switch (cache_type) {                
+          case 1: // Data Cache (We assume this is L1d)
+            if(cache_level != 1) {
+              printBug("Found data cache at level %d (expected 1)", cache_level);
+              return false;
+            }
+            topo->cach->L1d->num_caches = topo->logical_cores / num_sharing_cache;
+            break;
+          
+          case 2: // Instruction Cache (We assume this is L1i)
+            if(cache_level != 1) {
+              printBug("Found instruction cache at level %d (expected 1)", cache_level);
+              return false;
+            }
+            topo->cach->L1i->num_caches = topo->logical_cores / num_sharing_cache;
+            break;
+          
+          case 3: // Unified Cache (This may be L2 or L3)
+            if(cache_level == 2) { 
+              topo->cach->L2->num_caches = topo->logical_cores / num_sharing_cache;
+            }
+            else if(cache_level == 3) {
+              topo->cach->L3->num_caches = topo->logical_cores / num_sharing_cache;
+            }
+            else {
+              printBug("Found unified cache at level %d (expected == 2 or 3)", cache_level);
+              return false;
+            }
+            break;
+          
+          default: // Unknown Type Cache
+            printBug("Unknown Type Cache found at ID %d", i);
+            return false; 
+        }   
+      }
+      
+      i++;
+    } while (cache_type > 0);        
+  }
+  else {
+    printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X). Guessing cache sizes", 0x8000001D, cpu->maxExtendedLevels); 
+    topo->cach->L1i->num_caches = topo->physical_cores;
+    topo->cach->L1d->num_caches = topo->physical_cores;
+    
+    if(topo->cach->L3->exists) {
+      topo->cach->L2->num_caches = topo->physical_cores;
+      topo->cach->L3->num_caches = 1;    
+    }
+    else {
+      topo->cach->L2->num_caches = 1;        
+    }
+  }
+  
+  return true;
+}
+
+// Main reference: https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html
+// Very interesting resource: https://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
+struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach) {
+  struct topology* topo = malloc(sizeof(struct topology));  
+  init_topology_struct(topo, cach);
+  
+  uint32_t eax = 0;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+  
+  // Ask the OS the total number of cores it sees
+  // If we have one socket, it will be same as the cpuid,
+  // but in dual socket it will not!
+  // TODO: Replace by apic?
+  #ifdef _WIN32
+    SYSTEM_INFO info;
+    GetSystemInfo(&info);
+    topo->total_cores = info.dwNumberOfProcessors;
+  #else
+    if((topo->total_cores = sysconf(_SC_NPROCESSORS_ONLN)) == -1) {
+      perror("sysconf");
+      topo->total_cores = topo->logical_cores; // fallback
+    }    
+  #endif 
+  
+  switch(cpu->cpu_vendor) {
+    case CPU_VENDOR_INTEL:
+      if (cpu->maxLevels >= 0x00000004) { 
+        get_topology_from_apic(cpu, topo);
+      }
+      else {                
+        printErr("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels); 
+        topo->physical_cores = 1;
+        topo->logical_cores = 1;
+        topo->smt_available = 1;
+        topo->smt_supported = 1;
+      }      
+      break;
+    case CPU_VENDOR_AMD:       
+      if (cpu->maxExtendedLevels >= 0x80000008) {
+        eax = 0x80000008;  
+        cpuid(&eax, &ebx, &ecx, &edx);        
+        topo->logical_cores = (ecx & 0xFF) + 1;
+ 
+        if (cpu->maxExtendedLevels >= 0x8000001E) {
+          eax = 0x8000001E;  
+          cpuid(&eax, &ebx, &ecx, &edx);
+          topo->smt_supported = ((ebx >> 8) & 0x03) + 1;          
+        }
+        else {
+          printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x8000001E, cpu->maxExtendedLevels); 
+          topo->smt_supported = 1;       
+        }        
+      }
+      else {
+        printErr("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000008, cpu->maxExtendedLevels); 
+        topo->physical_cores = 1;
+        topo->logical_cores = 1;
+        topo->smt_supported = 1;         
+      }
+      
+      if (cpu->maxLevels >= 0x00000001) {
+        if(topo->smt_supported > 1)
+          topo->smt_available = is_smt_enabled_amd(topo);
+        else
+          topo->smt_available = 1;
+      }
+      else {
+        printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x0000000B, cpu->maxLevels);   
+        topo->smt_available = 1;
+      }
+      topo->physical_cores = topo->logical_cores / topo->smt_available;
+      
+      if(topo->smt_supported > 1)
+        topo->sockets = topo->total_cores / topo->smt_supported / topo->physical_cores; // Idea borrowed from lscpu
+      else
+        topo->sockets = topo->total_cores / topo->physical_cores;    
+      
+      get_cache_topology_amd(cpu, topo);      
+      
+      break;
+      
+    default:
+      printBug("Cant get topology because VENDOR is empty");
+      return NULL;
+  }
+    
+  return topo;
+}
+
+struct cache* get_cache_info_amd_fallback(struct cache* cach) {
+  uint32_t eax = 0x80000005;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+  cpuid(&eax, &ebx, &ecx, &edx);
+  
+  cach->L1d->size = (ecx >> 24) * 1024;
+  cach->L1i->size = (edx >> 24) * 1024;
+  
+  eax = 0x80000006;
+  cpuid(&eax, &ebx, &ecx, &edx);
+  
+  cach->L2->size = (ecx >> 16) * 1024;
+  cach->L3->size = (edx >> 18) * 512 * 1024;
+
+  cach->L1i->exists = cach->L1i->size > 0;
+  cach->L1d->exists = cach->L1d->size > 0;
+  cach->L2->exists = cach->L2->size > 0;
+  cach->L3->exists = cach->L3->size > 0;
+
+  if(cach->L3->exists)
+   cach->max_cache_level = 4;
+  else
+   cach->max_cache_level = 3;
+
+  return cach;
+}
+
+struct cache* get_cache_info_general(struct cache* cach, uint32_t level) {
+  uint32_t eax = 0;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+  int i=0;
+  int32_t cache_type;
+  
+  do {
+    eax = level; // get cache info
+    ebx = 0;
+    ecx = i; // cache id
+    edx = 0;
+      
+    cpuid(&eax, &ebx, &ecx, &edx); 
+      
+    cache_type = eax & 0x1F;
+      
+    // If its 0, we tried fetching a non existing cache
+    if (cache_type > 0) {
+      int32_t cache_level = (eax >>= 5) & 0x7;
+      uint32_t cache_sets = ecx + 1;
+      uint32_t cache_coherency_line_size = (ebx & 0xFFF) + 1;
+      uint32_t cache_physical_line_partitions = ((ebx >>= 12) & 0x3FF) + 1;
+      uint32_t cache_ways_of_associativity = ((ebx >>= 10) & 0x3FF) + 1;
+        
+      int32_t cache_total_size = cache_ways_of_associativity * cache_physical_line_partitions * cache_coherency_line_size * cache_sets;  
+      cach->max_cache_level++;
+      
+      switch (cache_type) {                
+        case 1: // Data Cache (We assume this is L1d)
+          if(cache_level != 1) {
+            printBug("Found data cache at level %d (expected 1)", cache_level);
+            return NULL;
+          }
+          cach->L1d->size = cache_total_size;
+          cach->L1d->exists = true;
+          break;
+            
+        case 2: // Instruction Cache (We assume this is L1i)
+          if(cache_level != 1) {
+            printBug("Found instruction cache at level %d (expected 1)", cache_level);
+            return NULL;
+          }
+          cach->L1i->size = cache_total_size;
+          cach->L1i->exists = true;
+          break;
+          
+        case 3: // Unified Cache (This may be L2 or L3)
+          if(cache_level == 2) { 
+            cach->L2->size = cache_total_size;
+            cach->L2->exists = true;
+          }
+          else if(cache_level == 3) {
+            cach->L3->size = cache_total_size;
+            cach->L3->exists = true;
+          }
+          else {
+            printBug("Found unified cache at level %d (expected == 2 or 3)", cache_level);
+            return NULL;
+          }
+          break;
+          
+        default: // Unknown Type Cache
+          printBug("Unknown Type Cache found at ID %d", i);
+          return NULL;                  
+      }
+    }    
+    
+    i++;
+  } while (cache_type > 0);
+  
+  return cach;
+}
+
+struct cache* get_cache_info(struct cpuInfo* cpu) {  
+  struct cache* cach = malloc(sizeof(struct cache));
+  init_cache_struct(cach);
+
+  uint32_t level;
+
+  // We use standart 0x00000004 for Intel
+  // We use extended 0x8000001D for AMD
+  // or 0x80000005/6 for old AMD
+  if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
+    level = 0x00000004;    
+    if(cpu->maxLevels < level) {
+      printErr("Can't read cache information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", level, cpu->maxLevels);    
+      return NULL;
+    }
+    else {
+      cach = get_cache_info_general(cach, level);
+    }
+  }
+  else {
+    level = 0x8000001D;
+    if(cpu->maxExtendedLevels < level) {
+      printWarn("Can't read cache information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", level, cpu->maxExtendedLevels);
+      level = 0x80000006;
+      if(cpu->maxExtendedLevels < level) {
+        printErr("Can't read cache information from cpuid using old method (needed extended level is 0x%.8X, max is 0x%.8X)", level, cpu->maxExtendedLevels);    
+        return NULL;
+      }
+      printWarn("Fallback to old method using 0x%.8X and 0x%.8X", level-1, level);
+      cach = get_cache_info_amd_fallback(cach);
+    }
+    else {
+      cach = get_cache_info_general(cach, level);    
+    }
+  }
+  
+  // Sanity checks. If we read values greater than this, they can't be valid ones
+  // The values were chosen by me
+  if(cach->L1i->size > 64 * 1024) {
+    printBug("Invalid L1i size: %dKB", cach->L1i->size/1024);
+    return NULL;
+  }
+  if(cach->L1d->size > 64 * 1024) {
+    printBug("Invalid L1d size: %dKB", cach->L1d->size/1024);
+    return NULL;
+  }
+  if(cach->L2->exists) {
+    if(cach->L3->exists && cach->L2->size > 2 * 1048576) {
+      printBug("Invalid L2 size: %dMB", cach->L2->size/(1048576));
+      return NULL;
+    }
+    else if(cach->L2->size > 100 * 1048576) {
+      printBug("Invalid L2 size: %dMB", cach->L2->size/(1048576));
+      return NULL;
+    }
+  }
+  if(cach->L3->exists && cach->L3->size > 100 * 1048576) {
+    printBug("Invalid L3 size: %dMB", cach->L3->size/(1048576));
+    return NULL;
+  }
+  if(!cach->L2->exists) {
+    printBug("Could not find L2 cache");
+    return NULL;    
+  }
+  
+  return cach;
+}
+
+struct frequency* get_frequency_info(struct cpuInfo* cpu) {
+  struct frequency* freq = malloc(sizeof(struct frequency));
+  
+  if(cpu->maxLevels < 0x00000016) {
+    #ifdef _WIN32
+      printErr("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000016, cpu->maxLevels);
+      freq->base = UNKNOWN_FREQ;
+      freq->max = UNKNOWN_FREQ;
+    #else
+      printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X). Using udev", 0x00000016, cpu->maxLevels);
+      freq->base = UNKNOWN_FREQ;
+      freq->max = get_max_freq_from_file(0);
+    #endif
+  }
+  else {
+    uint32_t eax = 0x00000016;
+    uint32_t ebx = 0;
+    uint32_t ecx = 0;
+    uint32_t edx = 0;
+    
+    cpuid(&eax, &ebx, &ecx, &edx);
+    
+    freq->base = eax;
+    freq->max = ebx;    
+    
+    if(freq->base == 0) {
+      printWarn("Read base CPU frequency and got 0 MHz");
+      freq->base = UNKNOWN_FREQ;
+    }
+    if(freq->max == 0) {
+      printWarn("Read max CPU frequency and got 0 MHz");
+      freq->max = UNKNOWN_FREQ;
+    }
+  }
+  
+  return freq;
+}
+
+/*** STRING FUNCTIONS ***/
+
+char* get_str_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t freq) {
+  /***
+  PP = PeakPerformance
+  SP = SinglePrecision
+
+  PP(SP) =
+  N_CORES                             *
+  FREQUENCY                           *
+  2(Two vector units)                 *
+  2(If cpu has fma)                   *
+  16(If AVX512), 8(If AVX), 4(If SSE) *
+
+  ***/
+
+  //7 for GFLOP/s and 6 for digits,eg 412.14
+  uint32_t size = 7+6+1+1;
+  assert(strlen(STRING_UNKNOWN)+1 <= size);
+  char* string = malloc(sizeof(char)*size);
+
+  //First check we have consistent data
+  if(freq == UNKNOWN_FREQ) {
+    snprintf(string,strlen(STRING_UNKNOWN)+1,STRING_UNKNOWN);
+    return string;
+  }
+
+  struct features* feat = cpu->feat;
+  double flops = topo->physical_cores * topo->sockets * (freq*1000000);
+  int vpus = get_number_of_vpus(cpu);
+  
+  flops = flops * vpus; 
+
+  if(feat->FMA3 || feat->FMA4)
+    flops = flops*2;
+
+  // Ice Lake has AVX512, but it has 1 VPU for AVX512, while
+  // it has 2 for AVX2. If this is a Ice Lake CPU, we are computing
+  // the peak performance supposing AVX2, not AVX512
+  if(feat->AVX512 && vpus_are_AVX512(cpu))
+    flops = flops*16;
+  else if(feat->AVX || feat->AVX2)
+    flops = flops*8;
+  else if(feat->SSE)
+    flops = flops*4;
+  
+  // See https://sites.utexas.edu/jdm4372/2018/01/22/a-peculiar-
+  // throughput-limitation-on-intels-xeon-phi-x200-knights-landing/
+  if(is_knights_landing(cpu))
+    flops = flops * 6 / 7; 
+
+  if(flops >= (double)1000000000000.0)
+    snprintf(string,size,"%.2f TFLOP/s",flops/1000000000000);
+  else if(flops >= 1000000000.0)
+    snprintf(string,size,"%.2f GFLOP/s",flops/1000000000);
+  else
+    snprintf(string,size,"%.2f MFLOP/s",flops/1000000);
+  
+  return string;
+}
+
+// TODO: Refactoring
+char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket) {
+  char* string;
+  if(topo->smt_supported > 1) {
+    //3 for digits, 21 for ' cores (SMT disabled)' which is the longest possible output
+    uint32_t size = 3+21+1;
+    string = malloc(sizeof(char)*size);
+    if(dual_socket) {
+      if(topo->smt_available > 1)
+        snprintf(string, size, "%d cores (%d threads)",topo->physical_cores * topo->sockets, topo->logical_cores * topo->sockets);
+      else {
+        if(cpu->cpu_vendor == CPU_VENDOR_AMD)
+          snprintf(string, size, "%d cores (SMT disabled)",topo->physical_cores * topo->sockets);
+        else
+          snprintf(string, size, "%d cores (HT disabled)",topo->physical_cores * topo->sockets);
+      }
+    }
+    else {
+      if(topo->smt_available > 1)
+        snprintf(string, size, "%d cores (%d threads)",topo->physical_cores,topo->logical_cores);
+      else {
+        if(cpu->cpu_vendor == CPU_VENDOR_AMD)
+          snprintf(string, size, "%d cores (SMT disabled)",topo->physical_cores);
+        else
+          snprintf(string, size, "%d cores (HT disabled)",topo->physical_cores);
+      }
+    }
+  }
+  else {
+    uint32_t size = 3+7+1;
+    string = malloc(sizeof(char)*size);
+    if(dual_socket)
+      snprintf(string, size, "%d cores",topo->physical_cores * topo->sockets);
+    else
+      snprintf(string, size, "%d cores",topo->physical_cores);
+  }
+  return string;
+}
+
+char* get_str_avx(struct cpuInfo* cpu) {
+  //If all AVX are available, it will use up to 15
+  char* string = malloc(sizeof(char)*17+1);
+  if(!cpu->feat->AVX)
+    snprintf(string,2+1,"No");
+  else if(!cpu->feat->AVX2)
+    snprintf(string,3+1,"AVX");
+  else if(!cpu->feat->AVX512)
+    snprintf(string,8+1,"AVX,AVX2");
+  else
+    snprintf(string,15+1,"AVX,AVX2,AVX512");
+
+  return string;
+}
+
+char* get_str_sse(struct cpuInfo* cpu) {
+  uint32_t last = 0;
+  uint32_t SSE_sl = 4;
+  uint32_t SSE2_sl = 5;
+  uint32_t SSE3_sl = 5;
+  uint32_t SSSE3_sl = 6;
+  uint32_t SSE4a_sl = 6;
+  uint32_t SSE4_1_sl = 7;
+  uint32_t SSE4_2_sl = 7;
+  char* string = malloc(sizeof(char)*SSE_sl+SSE2_sl+SSE3_sl+SSSE3_sl+SSE4a_sl+SSE4_1_sl+SSE4_2_sl+1);
+
+  if(cpu->feat->SSE) {
+      snprintf(string+last,SSE_sl+1,"SSE,");
+      last+=SSE_sl;
+  }
+  if(cpu->feat->SSE2) {
+      snprintf(string+last,SSE2_sl+1,"SSE2,");
+      last+=SSE2_sl;
+  }
+  if(cpu->feat->SSE3) {
+      snprintf(string+last,SSE3_sl+1,"SSE3,");
+      last+=SSE3_sl;
+  }
+  if(cpu->feat->SSSE3) {
+      snprintf(string+last,SSSE3_sl+1,"SSSE3,");
+      last+=SSSE3_sl;
+  }
+  if(cpu->feat->SSE4a) {
+      snprintf(string+last,SSE4a_sl+1,"SSE4a,");
+      last+=SSE4a_sl;
+  }
+  if(cpu->feat->SSE4_1) {
+      snprintf(string+last,SSE4_1_sl+1,"SSE4.1,");
+      last+=SSE4_1_sl;
+  }
+  if(cpu->feat->SSE4_2) {
+      snprintf(string+last,SSE4_2_sl+1,"SSE4.2,");
+      last+=SSE4_2_sl;
+  }
+
+  //Purge last comma
+  string[last-1] = '\0';
+  return string;
+}
+
+char* get_str_fma(struct cpuInfo* cpu) {
+  char* string = malloc(sizeof(char)*9+1);
+  if(!cpu->feat->FMA3)
+    snprintf(string,2+1,"No");
+  else if(!cpu->feat->FMA4)
+    snprintf(string,4+1,"FMA3");
+  else
+    snprintf(string,9+1,"FMA3,FMA4");
+
+  return string;
+}
+
+/*** DEBUG ***/
+
+void print_debug(struct cpuInfo* cpu) {
+  printf("%s\n", cpu->cpu_name);
+  printf("- Max standart level: 0x%.8X\n", cpu->maxLevels);
+  printf("- Max extended level: 0x%.8X\n", cpu->maxExtendedLevels);
+
+  free_cpuinfo_struct(cpu);
+}
+
+void free_topo_struct(struct topology* topo) {
+  free(topo->apic->cache_select_mask);
+  free(topo->apic->cache_id_apic);
+  free(topo->apic);
+  free(topo);
+}
--- a/src/x86/cpuid.h
+++ b/src/x86/cpuid.h
@@ -0,0 +1,21 @@
+#ifndef __CPUID__
+#define __CPUID__
+
+#include "../common/cpu.h"
+
+struct cpuInfo* get_cpu_info();
+struct cache* get_cache_info(struct cpuInfo* cpu);
+struct frequency* get_frequency_info(struct cpuInfo* cpu);
+struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach);
+
+char* get_str_avx(struct cpuInfo* cpu);
+char* get_str_sse(struct cpuInfo* cpu);
+char* get_str_fma(struct cpuInfo* cpu);
+char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket);
+char* get_str_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t freq);
+
+void print_debug(struct cpuInfo* cpu);
+
+void free_topo_struct(struct topology* topo);
+
+#endif
--- a/src/x86/cpuid_asm.c
+++ b/src/x86/cpuid_asm.c
@@ -1,4 +1,4 @@
-#include "cpuid.h"
+#include "cpuid_asm.h"

 void cpuid(uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) {
        __asm volatile("cpuid"
--- a/src/x86/cpuid_asm.h
+++ b/src/x86/cpuid_asm.h
@@ -1,5 +1,5 @@
-#ifndef __CPUID__
-#define __CPUID__
+#ifndef __CPUID_ASM__
+#define __CPUID_ASM__

 #include <stdint.h>

--- a/src/x86/uarch.c
+++ b/src/x86/uarch.c
@@ -0,0 +1,405 @@
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "uarch.h"
+#include "../common/global.h"
+
+/*
+ * - cpuid codes are based on Todd Allen's cpuid program
+ *   http://www.etallen.com/cpuid.html
+ * - This should be updated from time to time, to support newer CPUs. A good reference to look at:
+ *   https://en.wikichip.org/
+ */
+
+// From Todd Allen:
+//
+// MSR_CPUID_table* is a table that appears in Intel document 325462, "Intel 64
+// and IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A,
+// 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4" (the name changes from version to version
+// as more volumes are added).  The table moves around from version to version,
+// but in version 071US, was in "Volume 4: Model-Specific Registers", Table 2-1:
+// "CPUID Signature Values of DisplayFamily_DisplayModel".
+
+// MRG* is a table that forms the bulk of Intel Microcode Revision Guidance (or
+// Microcode Update Guidance).  Its purpose is not to list CPUID values, but
+// it does so, and sometimes lists values that appear nowhere else.
+
+// LX* indicates features that I have seen no documentation for, but which are
+// used by the Linux kernel (which is good evidence that they're correct).
+// The "hook" to find these generally is an X86_FEATURE_* flag in:
+//    arch/x86/include/asm/cpufeatures.h
+// For (synth) and (uarch synth) decoding, it often indicates
+// family/model/stepping value which are documented nowhere else.  These usually
+// can be found in:
+//    arch/x86/include/asm/intel-family.h
+
+typedef uint32_t MICROARCH;
+
+// Data not available
+#define NA                   -1
+
+// Unknown manufacturing process
+#define UNK                  -1
+
+enum {
+  UARCH_UNKNOWN,
+  // INTEL //
+  UARCH_P5,
+  UARCH_P6,
+  UARCH_DOTHAN,
+  UARCH_YONAH,
+  UARCH_MEROM,
+  UARCH_PENYR,
+  UARCH_NEHALEM,
+  UARCH_WESTMERE,
+  UARCH_BONNELL,
+  UARCH_SALTWELL,
+  UARCH_SANDY_BRIDGE,
+  UARCH_SILVERMONT,
+  UARCH_IVY_BRIDGE,
+  UARCH_HASWELL,
+  UARCH_BROADWELL,
+  UARCH_AIRMONT,
+  UARCH_KABY_LAKE,
+  UARCH_SKYLAKE,
+  UARCH_CASCADE_LAKE,
+  UARCH_COOPER_LAKE,
+  UARCH_KNIGHTS_LANDING,
+  UARCH_KNIGHTS_MILL,
+  UARCH_GOLDMONT,
+  UARCH_PALM_COVE,
+  UARCH_SUNNY_COVE,
+  UARCH_GOLDMONT_PLUS,
+  UARCH_TREMONT,
+  UARCH_WILLOW_COVE,
+  UARCH_COFFE_LAKE,
+  UARCH_ITANIUM,
+  UARCH_KNIGHTS_FERRY,
+  UARCH_KNIGHTS_CORNER,
+  UARCH_WILLAMETTE,
+  UARCH_NORTHWOOD,
+  UARCH_PRESCOTT,
+  UARCH_CEDAR_MILL,
+  UARCH_ITANIUM2,
+  UARCH_ICE_LAKE,
+  // AMD //
+  UARCH_AM486,
+  UARCH_AM5X86,
+  UARCH_K6,
+  UARCH_K7,
+  UARCH_K8,
+  UARCH_K10,
+  UARCH_PUMA_2008,
+  UARCH_BOBCAT,
+  UARCH_BULLDOZER,
+  UARCH_PILEDRIVER,
+  UARCH_STEAMROLLER,
+  UARCH_EXCAVATOR,
+  UARCH_JAGUAR,
+  UARCH_PUMA_2014,
+  UARCH_ZEN,
+  UARCH_ZEN_PLUS,
+  UARCH_ZEN2,
+  UARCH_ZEN3
+};
+
+struct uarch {
+  MICROARCH uarch;
+  char* uarch_str;
+  int32_t process; // measured in nanometers
+};
+
+#define UARCH_START if (false) {}
+#define CHECK_UARCH(arch, ef_, f_, em_, m_, s_, str, uarch, process) \
+   else if (ef_ == ef && f_ == f && (em_ == NA || em_ == em) && (m_ == NA || m_ == m) && (s_ == NA || s_ == s)) fill_uarch(arch, str, uarch, process);
+#define UARCH_END else { printBug("Unknown microarchitecture detected: M=0x%.8X EM=0x%.8X F=0x%.8X EF=0x%.8X S=0x%.8X", m, em, f, ef, s); fill_uarch(arch, "Unknown", UARCH_UNKNOWN, 0); }
+
+void fill_uarch(struct uarch* arch, char* str, MICROARCH u, uint32_t process) {
+  arch->uarch_str = malloc(sizeof(char) * (strlen(str)+1));
+  strcpy(arch->uarch_str, str);
+  arch->uarch = u;
+  arch->process= process;
+}
+
+// iNApired in Todd Allen's decode_uarch_intel
+struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
+  struct uarch* arch = malloc(sizeof(struct uarch));
+  
+  // EF: Extended Family                                                           //
+  // F:  Family                                                                    //
+  // EM: Extended Model                                                            //
+  // M: Model                                                                      //
+  // S: Stepping                                                                   //
+  // ----------------------------------------------------------------------------- //
+  //                EF  F  EM   M   S                                              //
+  UARCH_START  
+  CHECK_UARCH(arch, 0,  5,  0,  0, NA, "P5",              UARCH_P5,              800)
+  CHECK_UARCH(arch, 0,  5,  0,  1, NA, "P5",              UARCH_P5,              800)
+  CHECK_UARCH(arch, 0,  5,  0,  2, NA, "P5",              UARCH_P5,              UNK)
+  CHECK_UARCH(arch, 0,  5,  0,  3, NA, "P5",              UARCH_P5,              600)
+  CHECK_UARCH(arch, 0,  5,  0,  4, NA, "P5 MMX",          UARCH_P5,              UNK)
+  CHECK_UARCH(arch, 0,  5,  0,  7, NA, "P5 MMX",          UARCH_P5,              UNK)
+  CHECK_UARCH(arch, 0,  5,  0,  8, NA, "P5 MMX",          UARCH_P5,              250)
+  CHECK_UARCH(arch, 0,  5,  0,  9, NA, "P5 MMX",          UARCH_P5,              UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  0, NA, "P6 Pentium II",   UARCH_P6,              UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  1, NA, "P6 Pentium II",   UARCH_P6,              UNK) // process depends on core
+  CHECK_UARCH(arch, 0,  6,  0,  2, NA, "P6 Pentium II",   UARCH_P6,              UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  3, NA, "P6 Pentium II",   UARCH_P6,              350)
+  CHECK_UARCH(arch, 0,  6,  0,  4, NA, "P6 Pentium II",   UARCH_P6,              UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  5, NA, "P6 Pentium II",   UARCH_P6,              250)
+  CHECK_UARCH(arch, 0,  6,  0,  6, NA, "P6 Pentium II",   UARCH_P6,              UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  7, NA, "P6 Pentium III",  UARCH_P6,              250)
+  CHECK_UARCH(arch, 0,  6,  0,  8, NA, "P6 Pentium III",  UARCH_P6,              180)
+  CHECK_UARCH(arch, 0,  6,  0,  9, NA, "P6 Pentium M",    UARCH_P6,              130)
+  CHECK_UARCH(arch, 0,  6,  0, 10, NA, "P6 Pentium III",  UARCH_P6,              180)
+  CHECK_UARCH(arch, 0,  6,  0, 11, NA, "P6 Pentium III",  UARCH_P6,              130)
+  CHECK_UARCH(arch, 0,  6,  0, 13, NA, "Dothan",          UARCH_DOTHAN,          UNK)  // process depends on core
+  CHECK_UARCH(arch, 0,  6,  0, 14, NA, "Yonah",           UARCH_YONAH,            65)
+  CHECK_UARCH(arch, 0,  6,  0, 15, NA, "Merom",           UARCH_MEROM,            65)
+  CHECK_UARCH(arch, 0,  6,  1,  5, NA, "Dothan",          UARCH_DOTHAN,           90)
+  CHECK_UARCH(arch, 0,  6,  1,  6, NA, "Merom",           UARCH_MEROM,            65)
+  CHECK_UARCH(arch, 0,  6,  1,  7, NA, "Penryn",          UARCH_PENYR,            45)
+  CHECK_UARCH(arch, 0,  6,  1, 10, NA, "Nehalem",         UARCH_NEHALEM,          45)
+  CHECK_UARCH(arch, 0,  6,  1, 12, NA, "Bonnell",         UARCH_BONNELL,          45)
+  CHECK_UARCH(arch, 0,  6,  1, 13, NA, "Penryn",          UARCH_PENYR,            45)
+  CHECK_UARCH(arch, 0,  6,  1, 14, NA, "Nehalem",         UARCH_NEHALEM,          45)
+  CHECK_UARCH(arch, 0,  6,  1, 15, NA, "Nehalem",         UARCH_NEHALEM,          45)
+  CHECK_UARCH(arch, 0,  6,  2,  5, NA, "Westmere",        UARCH_WESTMERE,         32)
+  CHECK_UARCH(arch, 0,  6,  2 , 6, NA, "Bonnell",         UARCH_BONNELL,          45)
+  CHECK_UARCH(arch, 0,  6,  2,  7, NA, "Saltwell",        UARCH_SALTWELL,         32)
+  CHECK_UARCH(arch, 0,  6,  2, 10, NA, "Sandy Bridge",    UARCH_SANDY_BRIDGE,     32)
+  CHECK_UARCH(arch, 0,  6,  2, 12, NA, "Westmere",        UARCH_WESTMERE,         32)
+  CHECK_UARCH(arch, 0,  6,  2, 13, NA, "Sandy Bridge",    UARCH_SANDY_BRIDGE,     32)
+  CHECK_UARCH(arch, 0,  6,  2, 14, NA, "Nehalem",         UARCH_NEHALEM,          45)
+  CHECK_UARCH(arch, 0,  6,  2, 15, NA, "Westmere",        UARCH_WESTMERE,         32)
+  CHECK_UARCH(arch, 0,  6,  3,  5, NA, "Saltwell",        UARCH_SALTWELL,         14)
+  CHECK_UARCH(arch, 0,  6,  3,  6, NA, "Saltwell",        UARCH_SALTWELL,         32)
+  CHECK_UARCH(arch, 0,  6,  3,  7, NA, "Silvermont",      UARCH_SILVERMONT,       22)
+  CHECK_UARCH(arch, 0,  6,  3, 10, NA, "Ivy Bridge",      UARCH_IVY_BRIDGE,       22)
+  CHECK_UARCH(arch, 0,  6,  3, 12, NA, "Haswell",         UARCH_HASWELL,          22)
+  CHECK_UARCH(arch, 0,  6,  3, 13, NA, "Broadwell",       UARCH_BROADWELL,        14)
+  CHECK_UARCH(arch, 0,  6,  3, 14, NA, "Ivy Bridge",      UARCH_IVY_BRIDGE,       22)
+  CHECK_UARCH(arch, 0,  6,  3, 15, NA, "Haswell",         UARCH_HASWELL,          22)
+  CHECK_UARCH(arch, 0,  6,  4,  5, NA, "Haswell",         UARCH_HASWELL,          22)
+  CHECK_UARCH(arch, 0,  6,  4,  6, NA, "Haswell",         UARCH_HASWELL,          22)
+  CHECK_UARCH(arch, 0,  6,  4,  7, NA, "Broadwell",       UARCH_BROADWELL,        14)
+  CHECK_UARCH(arch, 0,  6,  4, 10, NA, "Silvermont",      UARCH_SILVERMONT,       22) // no docs, but /proc/cpuinfo seen in wild
+  CHECK_UARCH(arch, 0,  6,  4, 12, NA, "Airmont",         UARCH_AIRMONT,          14)
+  CHECK_UARCH(arch, 0,  6,  4, 13, NA, "Silvermont",      UARCH_SILVERMONT,       22)
+  CHECK_UARCH(arch, 0,  6,  4, 14,  8, "Kaby Lake",       UARCH_KABY_LAKE,        14)
+  CHECK_UARCH(arch, 0,  6,  4, 14, NA, "Skylake",         UARCH_SKYLAKE,          14)
+  CHECK_UARCH(arch, 0,  6,  4, 15, NA, "Broadwell",       UARCH_BROADWELL,        14)
+  CHECK_UARCH(arch, 0,  6,  5,  5,  6, "Cascade Lake",    UARCH_CASCADE_LAKE,     14) // no docs, but example from Greg Stewart
+  CHECK_UARCH(arch, 0,  6,  5,  5,  7, "Cascade Lake",    UARCH_CASCADE_LAKE,     14)
+  CHECK_UARCH(arch, 0,  6,  5,  5, 10, "Cooper Lake",     UARCH_COOPER_LAKE,      14)
+  CHECK_UARCH(arch, 0,  6,  5,  5, NA, "Skylake",         UARCH_SKYLAKE,          14)
+  CHECK_UARCH(arch, 0,  6,  5,  6, NA, "Broadwell",       UARCH_BROADWELL,        14)
+  CHECK_UARCH(arch, 0,  6,  5,  7, NA, "Knights Landing", UARCH_KNIGHTS_LANDING,  14)
+  CHECK_UARCH(arch, 0,  6,  5, 10, NA, "Silvermont",      UARCH_SILVERMONT,       22) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  5, 12, NA, "Goldmont",        UARCH_GOLDMONT,         14)
+  CHECK_UARCH(arch, 0,  6,  5, 13, NA, "Silvermont",      UARCH_SILVERMONT,       22) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  5, 14,  8, "Kaby Lake",       UARCH_KABY_LAKE,        14)
+  CHECK_UARCH(arch, 0,  6,  5, 14, NA, "Skylake",         UARCH_SKYLAKE,          14)
+  CHECK_UARCH(arch, 0,  6,  5, 15, NA, "Goldmont",        UARCH_GOLDMONT,         14)
+  CHECK_UARCH(arch, 0,  6,  6,  6, NA, "Palm Cove",       UARCH_PALM_COVE,        10) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  6, 10, NA, "Sunny Cove",      UARCH_SUNNY_COVE,       10) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  6, 12, NA, "Sunny Cove",      UARCH_SUNNY_COVE,       10) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  7,  5, NA, "Airmont",         UARCH_AIRMONT,          14) // no spec update; whispers & rumors
+  CHECK_UARCH(arch, 0,  6,  7, 10, NA, "Goldmont Plus",   UARCH_GOLDMONT_PLUS,    14)
+  CHECK_UARCH(arch, 0,  6,  7, 13, NA, "Sunny Cove",      UARCH_SUNNY_COVE,       10) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  7, 14, NA, "Ice Lake",        UARCH_ICE_LAKE,         10)
+  CHECK_UARCH(arch, 0,  6,  8,  5, NA, "Knights Mill",    UARCH_KNIGHTS_MILL,     14) // no spec update; only MSR_CPUID_table* so far
+  CHECK_UARCH(arch, 0,  6,  8,  6, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
+  CHECK_UARCH(arch, 0,  6,  8, 10, NA, "Tremont",         UARCH_TREMONT,          10) // no spec update; only geekbench.com example
+  CHECK_UARCH(arch, 0,  6,  8, 12, NA, "Willow Cove",     UARCH_WILLOW_COVE,      10) // found only on en.wikichip.org
+  CHECK_UARCH(arch, 0,  6,  8, 13, NA, "Willow Cove",     UARCH_WILLOW_COVE,      10) // LX*
+  CHECK_UARCH(arch, 0,  6,  8, 14, NA, "Kaby Lake",       UARCH_KABY_LAKE,        14)
+  CHECK_UARCH(arch, 0,  6,  9,  6, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
+  CHECK_UARCH(arch, 0,  6,  9, 12, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
+  CHECK_UARCH(arch, 0,  6,  9, 13, NA, "Sunny Cove",      UARCH_SUNNY_COVE,       10) // LX*
+  CHECK_UARCH(arch, 0,  6,  9, 14,  9, "Kaby Lake",       UARCH_KABY_LAKE,        14)
+  CHECK_UARCH(arch, 0,  6,  9, 14, 10, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
+  CHECK_UARCH(arch, 0,  6,  9, 14, 11, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
+  CHECK_UARCH(arch, 0,  6,  9, 14, 12, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
+  CHECK_UARCH(arch, 0,  6,  9, 14, 13, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
+  CHECK_UARCH(arch, 0,  6, 10,  5, NA, "Kaby Lake",       UARCH_KABY_LAKE,        14) // LX*
+  CHECK_UARCH(arch, 0,  6, 10,  6, NA, "Kaby Lake",       UARCH_KABY_LAKE,        14) // no spec update; only iNAtlatx64 example
+  CHECK_UARCH(arch, 0, 11,  0,  0, NA, "Knights Ferry",   UARCH_KNIGHTS_FERRY,    45) // found only on en.wikichip.org
+  CHECK_UARCH(arch, 0, 11,  0,  1, NA, "Knights Corner",  UARCH_KNIGHTS_CORNER,   22)
+  CHECK_UARCH(arch, 0, 15,  0,  0, NA, "Willamette",      UARCH_WILLAMETTE,      180)
+  CHECK_UARCH(arch, 0, 15,  0,  1, NA, "Willamette",      UARCH_WILLAMETTE,      180)
+  CHECK_UARCH(arch, 0, 15,  0,  2, NA, "Northwood",       UARCH_NORTHWOOD,       130)
+  CHECK_UARCH(arch, 0, 15,  0,  3, NA, "Prescott",        UARCH_PRESCOTT,         90)
+  CHECK_UARCH(arch, 0, 15,  0,  4, NA, "Prescott",        UARCH_PRESCOTT,         90)
+  CHECK_UARCH(arch, 0, 15,  0,  6, NA, "Cedar Mill",      UARCH_CEDAR_MILL,       65)
+  CHECK_UARCH(arch, 1, 15,  0,  0, NA, "Itanium2",        UARCH_ITANIUM2,        180)
+  CHECK_UARCH(arch, 1, 15,  0,  1, NA, "Itanium2",        UARCH_ITANIUM2,        130)
+  CHECK_UARCH(arch, 1, 15,  0,  2, NA, "Itanium2",        UARCH_ITANIUM2,        130)
+  UARCH_END
+    
+  return arch;
+}
+
+// iNApired in Todd Allen's decode_uarch_amd
+struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
+  struct uarch* arch = malloc(sizeof(struct uarch));
+  
+  // EF: Extended Family                                                           //
+  // F:  Family                                                                    //
+  // EM: Extended Model                                                            //
+  // M: Model                                                                      //
+  // S: Stepping                                                                   //
+  // ----------------------------------------------------------------------------- //
+  //                 EF  F  EM   M   S                                             //
+  UARCH_START  
+  CHECK_UARCH(arch,  0,  4,  0,  3, NA, "Am486",       UARCH_AM486,      UNK)
+  CHECK_UARCH(arch,  0,  4,  0,  7, NA, "Am486",       UARCH_AM486,      UNK)
+  CHECK_UARCH(arch,  0,  4,  0,  8, NA, "Am486",       UARCH_AM486,      UNK)
+  CHECK_UARCH(arch,  0,  4,  0,  9, NA, "Am486",       UARCH_AM486,      UNK)
+  CHECK_UARCH(arch,  0,  4, NA, NA, NA, "Am5x86",      UARCH_AM5X86,     UNK)
+  CHECK_UARCH(arch,  0,  5,  0,  6, NA, "K6",          UARCH_K6,         300)
+  CHECK_UARCH(arch,  0,  5,  0,  7, NA, "K6",          UARCH_K6,         250) // *p from sandpile.org
+  CHECK_UARCH(arch,  0,  5,  0, 13, NA, "K6",          UARCH_K6,         80)  // *p from sandpile.org
+  CHECK_UARCH(arch,  0,  5, NA, NA, NA, "K6",          UARCH_K6,         UNK)
+  CHECK_UARCH(arch,  0,  6,  0,  1, NA, "K7",          UARCH_K7,         250)
+  CHECK_UARCH(arch,  0,  6,  0,  2, NA, "K7",          UARCH_K7,         180)
+  CHECK_UARCH(arch,  0,  6, NA, NA, NA, "K7",          UARCH_K7,         UNK)
+  CHECK_UARCH(arch,  0, 15,  0,  4,  8, "K8",          UARCH_K8,         130)
+  CHECK_UARCH(arch,  0, 15,  0,  4, NA, "K8",          UARCH_K8,         130)
+  CHECK_UARCH(arch,  0, 15,  0,  5, NA, "K8",          UARCH_K8,         130)
+  CHECK_UARCH(arch,  0, 15,  0,  7, NA, "K8",          UARCH_K8,         130)
+  CHECK_UARCH(arch,  0, 15,  0,  8, NA, "K8",          UARCH_K8,         130)
+  CHECK_UARCH(arch,  0, 15,  0, 11, NA, "K8",          UARCH_K8,         130)
+  CHECK_UARCH(arch,  0, 15,  0, 12, NA, "K8",          UARCH_K8,         130)
+  CHECK_UARCH(arch,  0, 15,  0, 14, NA, "K8",          UARCH_K8,         130)
+  CHECK_UARCH(arch,  0, 15,  0, 15, NA, "K8",          UARCH_K8,         130)
+  CHECK_UARCH(arch,  0, 15,  1,  4, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  1,  5, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  1,  7, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  1,  8, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  1, 11, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  1, 12, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  1, 15, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  2,  1, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  2,  3, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  2,  4, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  2,  5, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  2,  7, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  2, 11, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  2, 12, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  2, 15, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  4,  1, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  4,  3, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  4,  8, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  4, 11, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  4, 12, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  4, 15, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  5, 13, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  5, 15, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  0, 15,  6,  8, NA, "K8",          UARCH_K8,          65)
+  CHECK_UARCH(arch,  0, 15,  6, 11, NA, "K8",          UARCH_K8,          65)
+  CHECK_UARCH(arch,  0, 15,  6, 12, NA, "K8",          UARCH_K8,          65)
+  CHECK_UARCH(arch,  0, 15,  6, 15, NA, "K8",          UARCH_K8,          65)
+  CHECK_UARCH(arch,  0, 15,  7, 12, NA, "K8",          UARCH_K8,          65)
+  CHECK_UARCH(arch,  0, 15,  7, 15, NA, "K8",          UARCH_K8,          65)
+  CHECK_UARCH(arch,  0, 15, 12,  1, NA, "K8",          UARCH_K8,          90)
+  CHECK_UARCH(arch,  1, 15,  0,  0, NA, "K10",         UARCH_K10,         65) // sandpile.org
+  CHECK_UARCH(arch,  1, 15,  0,  2, NA, "K10",         UARCH_K10,         65)
+  CHECK_UARCH(arch,  1, 15,  0,  4, NA, "K10",         UARCH_K10,         45)
+  CHECK_UARCH(arch,  1, 15,  0,  5, NA, "K10",         UARCH_K10,         45)
+  CHECK_UARCH(arch,  1, 15,  0,  6, NA, "K10",         UARCH_K10,         45)
+  CHECK_UARCH(arch,  1, 15,  0,  8, NA, "K10",         UARCH_K10,         45)
+  CHECK_UARCH(arch,  1, 15,  0,  9, NA, "K10",         UARCH_K10,         45)
+  CHECK_UARCH(arch,  1, 15,  0, 10, NA, "K10",         UARCH_K10,         45)
+  CHECK_UARCH(arch,  2, 15, NA, NA, NA, "Puma 2008",   UARCH_PUMA_2008,   65)
+  CHECK_UARCH(arch,  3, 15, NA, NA, NA, "K10",         UARCH_K10,         32)
+  CHECK_UARCH(arch,  5, 15, NA, NA, NA, "Bobcat",      UARCH_BOBCAT,      40)
+  CHECK_UARCH(arch,  6, 15,  0,  0, NA, "Bulldozer",   UARCH_BULLDOZER,   32) // iNAtlatx64 engr sample
+  CHECK_UARCH(arch,  6, 15,  0,  1, NA, "Bulldozer",   UARCH_BULLDOZER,   32)
+  CHECK_UARCH(arch,  6, 15,  0,  2, NA, "Piledriver",  UARCH_PILEDRIVER,  32)
+  CHECK_UARCH(arch,  6, 15,  1,  0, NA, "Piledriver",  UARCH_PILEDRIVER,  32)
+  CHECK_UARCH(arch,  6, 15,  1,  3, NA, "Piledriver",  UARCH_PILEDRIVER,  32)
+  CHECK_UARCH(arch,  6, 15,  3,  0, NA, "Steamroller", UARCH_STEAMROLLER, 28)
+  CHECK_UARCH(arch,  6, 15,  3,  8, NA, "Steamroller", UARCH_STEAMROLLER, 28)
+  CHECK_UARCH(arch,  6, 15,  4,  0, NA, "Steamroller", UARCH_STEAMROLLER, 28) // Software Optimization Guide (15h) says it has the same iNAt latencies as (6,15),(3,x).
+  CHECK_UARCH(arch,  6, 15,  6,  0, NA, "Excavator",   UARCH_EXCAVATOR,   28) // undocumented, but iNAtlatx64 samples
+  CHECK_UARCH(arch,  6, 15,  6,  5, NA, "Excavator",   UARCH_EXCAVATOR,   28) // undocumented, but sample from Alexandros Couloumbis
+  CHECK_UARCH(arch,  6, 15,  7,  0, NA, "Excavator",   UARCH_EXCAVATOR,   28)
+  CHECK_UARCH(arch,  7, 15,  0,  0, NA, "Jaguar",      UARCH_JAGUAR,      28)
+  CHECK_UARCH(arch,  7, 15,  3,  0, NA, "Puma 2014",   UARCH_PUMA_2014,   28)
+  CHECK_UARCH(arch,  8, 15,  0,  0, NA, "Zen",         UARCH_ZEN,         14) // iNAtlatx64 engr sample
+  CHECK_UARCH(arch,  8, 15,  0,  1, NA, "Zen",         UARCH_ZEN,         14)
+  CHECK_UARCH(arch,  8, 15,  0,  8, NA, "Zen+",        UARCH_ZEN_PLUS,    12)
+  CHECK_UARCH(arch,  8, 15,  1,  1, NA, "Zen",         UARCH_ZEN,         14) // found only on en.wikichip.org & iNAtlatx64 examples
+  CHECK_UARCH(arch,  8, 15,  1,  8, NA, "Zen+",        UARCH_ZEN_PLUS,    12) // found only on en.wikichip.org
+  CHECK_UARCH(arch,  8, 15,  3,  1, NA, "Zen 2",       UARCH_ZEN2,         7) // found only on en.wikichip.org
+  CHECK_UARCH(arch,  8, 15,  6,  0, NA, "Zen 2",       UARCH_ZEN2,         7) // undocumented, geekbench.com example
+  CHECK_UARCH(arch,  8, 15,  7,  1, NA, "Zen 2",       UARCH_ZEN2,         7) // undocumented, but samples from Steven Noonan
+  CHECK_UARCH(arch, 10, 15, NA, NA, NA, "Zen 3",       UARCH_ZEN3,         7) // undocumented, LX*
+  UARCH_END
+    
+  return arch;
+}
+
+struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
+  if(cpu->cpu_vendor == CPU_VENDOR_INTEL)
+    return get_uarch_from_cpuid_intel(ef, f, em, m, s);
+  else 
+    return get_uarch_from_cpuid_amd(ef, f, em, m, s);
+}
+
+bool vpus_are_AVX512(struct cpuInfo* cpu) {
+  return cpu->arch->uarch != UARCH_ICE_LAKE;    
+  return cpu->arch->uarch != UARCH_ICE_LAKE;
+}
+
+bool is_knights_landing(struct cpuInfo* cpu) {
+  return cpu->arch->uarch == UARCH_KNIGHTS_LANDING;  
+}
+
+int get_number_of_vpus(struct cpuInfo* cpu) {
+  if(cpu->cpu_vendor == CPU_VENDOR_AMD)
+    return 1;
+  
+  switch(cpu->arch->uarch) {
+      case UARCH_HASWELL:
+      case UARCH_BROADWELL:
+          
+      case UARCH_SKYLAKE:
+      case UARCH_CASCADE_LAKE:                    
+      case UARCH_KABY_LAKE:
+      case UARCH_COFFE_LAKE:
+      case UARCH_PALM_COVE:    
+      
+      case UARCH_KNIGHTS_LANDING:
+      case UARCH_KNIGHTS_MILL:
+          
+      case UARCH_ICE_LAKE:      
+        return 2;
+      default:
+        return 1;
+  }
+}
+
+char* get_str_uarch(struct cpuInfo* cpu) {
+  return cpu->arch->uarch_str;    
+}
+
+char* get_str_process(struct cpuInfo* cpu) {
+  char* str = malloc(sizeof(char) * (4+2+1));
+  uint32_t process = cpu->arch->process;
+  
+  if(process > 100)    
+    sprintf(str, "%.2fum", (double)process/100);
+  else
+    sprintf(str, "%dnm", process);
+  
+  return str;
+}
+
+void free_uarch_struct(struct uarch* arch) {    
+  free(arch->uarch_str);
+  free(arch);
+}
--- a/src/x86/uarch.h
+++ b/src/x86/uarch.h
@@ -0,0 +1,18 @@
+#ifndef __UARCH__
+#define __UARCH__
+
+#include <stdint.h>
+
+#include "cpuid.h"
+
+struct uarch;
+
+struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s);
+bool vpus_are_AVX512(struct cpuInfo* cpu);
+bool is_knights_landing(struct cpuInfo* cpu);
+int get_number_of_vpus(struct cpuInfo* cpu);
+char* get_str_uarch(struct cpuInfo* cpu);
+char* get_str_process(struct cpuInfo* cpu);
+void free_uarch_struct(struct uarch* arch);
+
+#endif
Author	SHA1	Message	Date
Dr-Noob	fce0bbf012	[v0.94][ARM] Do not print cache sizes	2020-12-08 18:33:42 +01:00
Dr-Noob	2939d5b352	[v0.94] When SoC string is not matched against any SoC is not considered a bug anymore	2020-12-08 18:04:13 +01:00
Dr-Noob	7e532d57a6	[v0.94] Add reminder in Qualcomm SoCs, that need more time to work properly	2020-12-08 18:01:26 +01:00
Dr-Noob	a96d95eba1	[v0.94] Reviewed MTK SoCs	2020-12-08 15:56:13 +01:00
Dr-Noob	5b9a9e90d0	[v0.94] Fix compilation issues	2020-12-05 11:56:40 +01:00
Dr-Noob	f68c81395b	[v0.94] Reviewed snapdragon 6XX, 7XX and 8XX (some SoC models needs more work)	2020-12-05 11:10:15 +01:00
Dr-Noob	4971774ce4	[v0.94] Reviewed snapdragon 2XX and 4XX	2020-12-04 20:23:48 +01:00
Dr-Noob	ea5d07504c	[v0.94] Fix snapdragon SoC models	2020-12-04 15:41:33 +01:00
Dr-Noob	c111eb9a41	[v0.94] SoC detection stores the exact SoC model	2020-12-04 10:11:07 +01:00
Dr-Noob	01e22b8090	[v0.94] Fix compilation issues	2020-12-01 16:13:38 +01:00
Dr-Noob	b1f3196e0d	[v0.94] Refactor CPU features in a separate struct. Remove x86 debug functions	2020-12-01 12:16:12 +01:00
Dr-Noob	d04d535807	[v0.94][ARM] Add CPU feature detection, such as NEON, AES, SHA... Take into account NEON capabilities for PP computation	2020-12-01 11:40:09 +01:00
Dr-Noob	35c2aa7e6f	[v0.94][ARM] Add Kirin and Broadcom ASCII arts. Fix Broadcom SoCs detection	2020-11-28 13:51:20 +01:00
Dr-Noob	fd898331f8	[v0.93][ARM] Tune Exynos ASCII art algorithm	2020-11-28 12:39:25 +01:00
Dr-Noob	532a65e35d	[v0.93][ARM] Refactoring in ARM printer	2020-11-28 12:31:08 +01:00
Dr-Noob	1d58b1808d	[v0.93][ARM] Support printing ASCII on chips that have lots of attributes (if they have more than 2 different CPUs). Fix all ASCII arts (they were missing the last empty character)	2020-11-28 12:24:13 +01:00
Dr-Noob	7d7af00e68	Add Samsung Exynos ASCII art. Add experimental exynos printer algorithm	2020-11-28 11:09:25 +01:00
Dr-Noob	84fb38a507	[v0.93][ARM] Add Kirin and Broadcom SoC detection. Add function for special SoC strings detection	2020-11-28 10:02:25 +01:00
Dr-Noob	ccfcab88d3	[v0.92][ARM] Add MediaTek ASCII art	2020-11-26 20:33:35 +01:00
Dr-Noob	e5d5e5ef92	[v0.92][Refactoring] Refactor Intel and AMD printer code into algorithms	2020-11-26 18:45:33 +01:00
Dr-Noob	ff92107d7c	[v0.92] Fix previous commit (I forgot to add the file)	2020-11-26 18:35:29 +01:00
Dr-Noob	b9e96baf91	[v0.92] Add printer algorithms. This approach allows more flexibility in the printer. Improve Snapdragon ASCII	2020-11-26 18:30:39 +01:00
Dr-Noob	c62a63f539	[v0.92][ARM] Print ACII art based on SoC instead of CPU vendor. Add snapdragon ASCII art. Refactor printer to save some lines of code	2020-11-26 16:42:36 +01:00
Dr-Noob	89e5e30e53	[v0.91][X86][BUGFIX] Fix annoying compilation issue	2020-11-26 13:05:14 +01:00
Dr-Noob	7c2463eb8f	[v0.91][ARM] New experimental way of matching SoC names	2020-11-26 12:41:41 +01:00
Dr-Noob	b4b693a11e	[v0.91][ARM][BUGFIX] Do not print error message if frequency file does not exist in ARM. Fix arm udev file (I uploaded my debug udev by mistake)	2020-11-26 12:15:07 +01:00
Dr-Noob	ff032efb28	[v0.91][ARM] Fix for snapdragon chips reporting name in lowercase	2020-11-26 11:51:06 +01:00
Dr-Noob	da94c7ee18	[v0.91][ARM] Add Exynos SoCs	2020-11-26 11:30:14 +01:00
Dr-Noob	4c36e4c5e5	[v0.91][ARM] Print manufacturing process from SoC information	2020-11-26 10:52:44 +01:00
Dr-Noob	20dbc3be27	[v0.90][ARM] Print bug message if SoC string is found but not detected. This is maybe too verbose, but I would like to increase the support for more ARM SoC, and I hope this message is useful for this purpose	2020-11-26 10:43:42 +01:00
Dr-Noob	53b4ff5793	[v0.90][ARM] Add MediaTek SoCs	2020-11-26 09:53:53 +01:00
Dr-Noob	4f1dd82bba	[v0.90][ARM] Add most of Qualcomm SoCs	2020-11-25 11:34:49 +01:00
Dr-Noob	37e849978a	[v0.90][ARM] Print right number of cores and frequency for each CPU	2020-11-24 16:17:53 +01:00
Dr-Noob	233565c052	[v0.89][ARM][BUGFIX] Fix uarch detection for Kryo 260 / 280	2020-11-24 16:16:22 +01:00
Dr-Noob	5d168f5707	[v0.89][ARM][BUGFIX] Fix obscure bug where cpufetch failed if cpuinfo did not start with "processor" string	2020-11-24 15:20:07 +01:00
Dr-Noob	0bc978564e	[v0.89][ARM][BUGFIX] Two CPUs are equal when Main ID Register AND frequency are equal, not just when Main ID register are equal	2020-11-24 13:21:27 +01:00
Dr-Noob	fbea497740	[v0.89] Change freq from int64 to int32, which fixes a compilation issue. Fix Makefile in Windows	2020-11-24 12:52:42 +01:00
Dr-Noob	8645b54b58	[v0.89][ARM] Separate udev for ARM in a different file, since there are many functions that are ARM only. Refactoring of file reading code	2020-11-24 12:32:38 +01:00
Dr-Noob	220dd02abd	[v0.89][ARM] Add very basic SoC parsing from cpuinfo/android strings. Only detects two SoCs, but allows debugging	2020-11-24 11:44:24 +01:00
Dr-Noob	685e78f2b7	[v0.88][ARM][BUGFIX] Fix bugs in single CPU SoCs and small bugs related to strings	2020-11-24 10:27:33 +01:00
Dr-Noob	71d660d7b1	[v0.88][ARM] Fetch raw soc name from cpuinfo or android (if supported)	2020-11-24 10:03:21 +01:00
Dr-Noob	bb05a4d577	[v0.88][ARM][BUGFIX] Fix some compilation issues	2020-11-23 18:45:42 +01:00
Dr-Noob	eaa86522a4	[v0.88][ARM] Add very basic SoC detection (Android only)	2020-11-23 18:30:00 +01:00
Dr-Noob	8927048c95	[v0.88] Reorganize files and documentation. Remove ascii directory (it was useless)	2020-11-23 16:15:46 +01:00
Dr-Noob	093222d533	[v0.88][DOC] Update documentation and divide it in two files, one for each architecture	2020-11-23 16:11:54 +01:00
Dr-Noob	716706d0a7	[v0.88][ARM][BUGFIX] Fetch number of cores from /sys/devices/system/cpu/present file, instead of /proc/cpuinfo. Pay attention to cases where frequency and/or MIDR can not be fetched from cpuinfo. This happens when the CPU has offline cores	2020-11-22 15:18:15 +01:00
Dr-Noob	fcb2c716db	[v0.87][FREQ] Frequency in udev is now fetched as a per core basis. Before this commit, freq was always fetched from core 0. This allows ARM do detect the max frequency of each of the cores (which may or may not be the same in all of them)	2020-11-22 10:23:02 +01:00
Dr-Noob	0875c4d425	[v0.87][ARM] cpuInfo now holds all the structs (freq, cache, etc), instead of having them separated. This allows ARM to represent a single CPU, because from its pointer, it is able to access the specific frequency, cache, etc	2020-11-22 09:57:50 +01:00
Dr-Noob	f5ec566577	[v0.87][DOC] Explain commit #42ade63 in documentation. Add Android information in README	2020-11-22 09:20:35 +01:00
Dr-Noob	5b0cbd622f	[v0.87][BUGFIX] Add checks to detect wrong ASCII arts. Fix ARM ASCII art	2020-11-21 19:21:19 +01:00
Dr-Noob	0b9f0e860c	[v0.87][PRINTER] ASCII art attributes are no longer fixed in a given position, and are not fixed in length (max length is now 100). Added different algorithms for printing ASCII art for X86 and ARM, which allows ARM to show each CPU inside a SoC	2020-11-21 19:04:57 +01:00
Dr-Noob	50931ee94d	[v0.86][BUGFIX] Fix print format for hex values	2020-11-21 16:45:51 +01:00
Dr-Noob	42ade63746	[v0.86][BUGFIX] Add old AMD CPUs cache fix to master branch	2020-11-21 16:41:08 +01:00
Dr-Noob	e4a4e13d56	[v0.82][BUGFIX] Using 0x80000006 in new AMD CPUs outputs wrong L3 size since it reports the full size instead the size of a single L3. Use old method just when is necessary	2020-11-21 16:37:51 +01:00
Dr-Noob	7d707916fb	[v0.86][OPTIONS] Replace levels option with debug option, which does the same on x86, but also exists on ARM, which prints MIDR registers (need work to be properly implemented)	2020-11-18 23:41:42 +01:00
Dr-Noob	c44a646cd1	[v0.85][ARM] Add SoC field in ARM and remove CPU Name field, which is only valid in x86. Fix Makefile for some strict compilers	2020-11-18 23:22:26 +01:00
Dr-Noob	8c11cb2422	[v0.84][ARM] Add ISA field in ARM. ISA depends on uarch, not on specific CPU. Fill all the missing data in uarch.c	2020-11-14 11:11:32 +01:00
Dr-Noob	cb78f18de1	[v0.84][BUGFIX] Fix more compilation issues	2020-11-10 22:46:39 +01:00
Dr-Noob	07f3f26ff6	[v0.84][BUGFIX] Fix more compilation issues	2020-11-10 22:45:14 +01:00
Dr-Noob	27aabb35be	[v0.84][BUGFIX] Fix compilation issues	2020-11-10 18:51:13 +01:00
Dr-Noob	904cb46765	[v0.84][ARM] Add lots of new microarch detection	2020-11-10 18:50:32 +01:00
Dr-Noob	3aa13269b7	[v0.83][ARM] Add basic support for microarchitecture and CPU name detection. Need to add the remaining models	2020-11-08 16:49:01 +01:00
Dr-Noob	b978ddc83d	[v0.82][BUGFIX] Issue #33 : Use 0x80000006 for cache fetching in AMD, instead of 0x8000001D. This means that a different approach in Intel and AMD CPUs	2020-11-07 10:48:48 +01:00
Dr-Noob	16abfa7022	[v0.82][README] Update README to show ARM experimental support	2020-11-06 11:10:30 +01:00
Dr-Noob	9c8e169592	[v0.82][ARM][ASCII][Refactoring] ARM ascii changes. Remove the assumption that all sockets are equal in a ARM based SoC. Little more support for ARM processors. Add ARM color style	2020-11-06 10:06:13 +01:00
Dr-Noob	4f1722ead6	[v0.81][ARM][Refactoring] Refactoring and very basic ARM support	2020-11-05 13:44:46 +01:00
Dr-Noob	f4f68287aa	[v0.8][Refactoring] Refactoring ARM code and source code tree	2020-11-05 11:01:46 +01:00
Dr-Noob	1fad4fd10b	[v0.8][ARM] Building support in ARM	2020-11-05 09:28:41 +01:00
Dr-Noob	5cc9038f3d	Fix peak performance in KNL	2020-10-20 21:13:04 +02:00
Dr-Noob	f992d0122f	Merge remote-tracking branch 'Wunkolo/feat/windows-colors' into master	2020-10-20 20:49:29 +02:00
Dr-Noob	ac86be2d7a	Fix bug in Windows where specifying a style while using a terminal that supports color does not enable the color support, so colors do not show correctly	2020-10-20 20:43:14 +02:00
Wunkolo	c158cab005	Update readme with new Windows terminal support	2020-10-17 18:46:53 -07:00
Wunkolo	9867754d08	Implement VT100 escape-code detection for Windows Latest versions of windows have support for the parsing VT100 escape code sequences, allowing for terminal colors similar to Linux. https://docs.microsoft.com/en-us/windows/console/console-virtual-terminal-sequences#screen-colors Here I have it get the console mode, set the `ENABLE_VIRTUAL_TERMINAL_PROCESSING` flag, and then grab the console mode again to both verify that VT100 escape sequences are supported and that it is enabled after setting it to determine if the printer should allow for fancy-color mode.	2020-10-17 18:46:20 -07:00
Dr-Noob	5119ece0dd	Refactoring defines to enums	2020-10-14 10:55:46 +02:00
Dr-Noob	e37c7d9ae0	Basic support for virtual machines	2020-10-11 23:27:19 +02:00
Dr-Noob	aa5f0a8b88	Add install option in Makefile	2020-09-21 13:07:18 +02:00
Dr-Noob	075e4399f8	Update description	2020-09-05 10:51:16 +02:00
Dr-Noob	3dedb0bbc3	Add programming documentation	2020-09-05 09:46:37 +02:00
Dr-Noob	60bc02185d	Small fix	2020-09-01 20:48:37 +02:00
Dr-Noob	ae752bac77	Add images	2020-09-01 20:45:52 +02:00
Dr-Noob	500ccfa871	Stable version 0.7 heavily tested in many different CPUs	2020-09-01 20:44:48 +02:00
Dr-Noob	877833db0a	Dont fetch if smt is enabled if its not supported (AMD). Dont guess cache topology, fetch it from CPUID (AMD)	2020-09-01 13:08:44 +02:00
Dr-Noob	5cca6df218	Fix memory leaks. Add debug message when microarch is unknown	2020-09-01 11:32:08 +02:00
Dr-Noob	de8952b4ea	Fix bug which caused you couldnt use --version. Change --style to be more user friendly. Update --help	2020-09-01 11:00:11 +02:00
Dr-Noob	1f80566f63	New info to be displayed (uarch and process) instead of other info (sha, aes, sse)	2020-09-01 09:37:53 +02:00
Dr-Noob	ab1416563c	Fix PP in Ice Lake	2020-08-31 18:27:32 +02:00
Dr-Noob	1a9c0546f2	Add support for detecting AMD microarch	2020-08-31 15:56:21 +02:00
Dr-Noob	35efdd8f2c	Fix #26 . Guess number of VPUs according to microarchitecture	2020-08-31 14:04:41 +02:00
Dr-Noob	5148962fa3	Add code to detect CPU microarchitecture (Intel only, at the moment)	2020-08-31 13:18:25 +02:00
Dr-Noob	d998acdcdf	Fix #25 : Compute PP taking into account the number of sockets	2020-08-31 09:33:39 +02:00
Dr-Noob	81a45628f0	Code refactoring. Forgot to add verbose option to help	2020-08-30 13:55:37 +02:00
Dr-Noob	4f98a5bccf	Refactor previous commit	2020-08-30 12:42:38 +02:00
Dr-Noob	dae0f678ad	Fix #23 . I tried fetching the cache topology in AMD but could not find a proper way, so the code fallback to two commits ago. cpufetch has to guess cache sizes except L3, which can be fetched. Since I have been trying many approaches and stuff, the code needs to be refactored	2020-08-30 12:12:25 +02:00
Dr-Noob	69cc08759a	Fix #21 and #22 : Obtain the number of caches of every level instead of guessing them. It is done by fetching cache topology from apic. It works, but it needs a big refactoring. Moreover, it currently works only on Intel CPUs, so this breaks the cache in AMD.	2020-08-29 21:51:14 +02:00
Dr-Noob	d8dad29a57	Fix SMT bug in AMD. I would like to improve it, since Intel can use APIC with 0x1 and 0xB (extended) while AMD does with 0x1 and extended seems to be 0x1E. Add support to detect more than one L3 cache. This is not a very elegant solution, since we still assume that we have the same number of caches as caches in a given level. To fix it, cpufetch should know how many caches are in a given level (hint, Linux knows using shared_cpu_map)	2020-08-29 15:42:56 +02:00
Dr-Noob	e08b60b1c8	Project stopped until I have time to continue	2020-07-12 19:08:38 +02:00
Dr-Noob	ad6c3c88ce	Small corrections in code and Makefile	2020-07-12 15:39:34 +02:00
Dr-Noob	e114bde128	Complete topology read in AMD	2020-07-06 01:58:48 +02:00
Dr-Noob	7164409ca2	Add legacy style (for Windows) and make it the default for Windows. Add verbose flag	2020-07-06 01:30:14 +02:00
Dr-Noob	08f79bb914	Fix compilation in Windows and add support for bind to specific cores. Separate APIC code in other file	2020-07-06 01:16:59 +02:00
Dr-Noob	b457c86100	Add support for obtaining topology in old processors (with CPUID less than 0xB)	2020-07-05 19:59:55 +02:00
Dr-Noob	e5d86289b5	Use APIC to obtain topology. This is interesting because this will allow us to obtain it even on older CPUs (without CPUID 0xB) (will be added in future commits)	2020-07-05 16:52:41 +02:00
Dr-Noob	c6c4d8b6fd	Fix spaces bug in CPU name	2020-07-03 19:42:05 +02:00
Dr-Noob	c8fde107dd	Fix ascii logo in AMD. Fix output on CPUs without L3	2020-07-03 16:24:14 +02:00
Dr-Noob	b076189b32	Add support to detect if HT/SMT is enabled or disabled	2020-07-03 16:11:09 +02:00
Dr-Noob	d43229359a	Support for 4 colors with --color (2 for ascii, 2 for text)	2020-07-03 09:42:30 +02:00
Dr-Noob	ba047c76e3	Add two different styles. The old one is now called retro, and the new one, which is the default, is called fancy	2020-07-02 18:53:28 +02:00
Dr-Noob	942a86c04f	Remove styles and add option to specify custom color output in RGB format	2020-07-02 16:14:37 +02:00
Dr-Noob	ea338a68c8	Forgot to support AMD in printer	2020-06-29 17:32:50 +02:00
Dr-Noob	d7b7e2b62d	Support printing dual socket. Fix bug where cache sizes were not displayed correctly (they were truncated)	2020-06-29 17:13:37 +02:00
Dr-Noob	941bf35d03	Big refactoring. Move ascii managment to printer. Mix extended and standart cpuid functions in cpuid file. Old cpuid renamed to cpuid_asm. Store cpu name in cpuInfo struct	2020-06-28 15:51:30 +02:00
Dr-Noob	131d860de6	Print total cache sizes (for L1 and L2, but also for L3 in case we run in dual socket!)	2020-06-28 12:47:03 +02:00
Dr-Noob	92992be225	Support for multi socket systems (only information gathering, not printing)	2020-06-22 18:04:24 +02:00
Dr-Noob	698274e44c	Fix bug and memory leak	2020-06-22 18:00:45 +02:00
Dr-Noob	7fee305e8b	Little fixes	2020-06-22 15:30:05 +02:00
Dr-Noob	1ce6b97bec	Fix topology in AMD, using extended level to fetch it	2020-06-22 15:04:32 +02:00
Dr-Noob	8211f24f46	Fix cache in AMD, using extended level	2020-06-22 13:50:00 +02:00
Dr-Noob	0725e9d876	Add --levels option	2020-06-22 13:17:00 +02:00