[v1.04] Testing bhyve matcher

Makefile

@@ -1,7 +1,7 @@
 CC ?= gcc
 
 CFLAGS+=-Wall -Wextra -pedantic
-SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith
+SANITY_FLAGS=-Wfloat-equal -Wshadow -Wpointer-arith -Wstrict-prototypes
 
 PREFIX ?= /usr
 
@@ -11,6 +11,7 @@ COMMON_SRC = $(SRC_COMMON)main.c $(SRC_COMMON)cpu.c $(SRC_COMMON)udev.c $(SRC_CO
 COMMON_HDR = $(SRC_COMMON)ascii.h $(SRC_COMMON)cpu.h $(SRC_COMMON)udev.h $(SRC_COMMON)printer.h $(SRC_COMMON)args.h $(SRC_COMMON)global.h
 
 ifneq ($(OS),Windows_NT)
+	GIT_VERSION := "$(shell git describe --abbrev=4 --dirty --always --tags)"
 	arch := $(shell uname -m)
 	ifeq ($(arch), $(filter $(arch), x86_64 amd64 i386 i486 i586 i686))
 		SRC_DIR=src/x86/
@@ -31,8 +32,8 @@ ifneq ($(OS),Windows_NT)
 		CFLAGS += -DARCH_PPC -std=gnu99 -fstack-protector-all -Wno-language-extension-token
 	else ifeq ($(arch), $(filter $(arch), arm aarch64_be aarch64 arm64 armv8b armv8l armv7l armv6l))
 		SRC_DIR=src/arm/
-		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
+		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
-		HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h  $(SRC_DIR)soc.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
+		HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h  $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
 		CFLAGS += -DARCH_ARM -Wno-unused-parameter -std=c99 -fstack-protector-all
 
 		os := $(shell uname -s)
@@ -40,6 +41,11 @@ ifneq ($(OS),Windows_NT)
 			SOURCE += $(SRC_DIR)sysctl.c
 			HEADERS += $(SRC_DIR)sysctl.h
 		endif
+        else ifeq ($(arch), $(filter $(arch), riscv64 riscv32))
+                SRC_DIR=src/riscv/
+                SOURCE += $(COMMON_SRC) $(SRC_DIR)riscv.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
+                HEADERS += $(COMMON_HDR) $(SRC_DIR)riscv.h $(SRC_DIR)uarch.h $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_DIR)udev.h $(SRC_DIR)socs.h
+                CFLAGS += -DARCH_RISCV -Wno-unused-parameter -std=c99 -fstack-protector-all
 	else
 		# Error lines should not be tabulated because Makefile complains about it
 $(warning Unsupported arch detected: $(arch). See https://github.com/Dr-Noob/cpufetch#1-support)
@@ -50,6 +56,7 @@ $(error Aborting compilation)
 	OUTPUT=cpufetch
 else
 	# Assume x86_64
+	GIT_VERSION := ""
 	SRC_DIR=src/x86/
 	SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
 	HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h
@@ -80,7 +87,11 @@ freq_avx512.o: Makefile $(SRC_DIR)freq/freq_avx512.c $(SRC_DIR)freq/freq_avx512.
 	$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -mavx512f -pthread $(SRC_DIR)freq/freq_avx512.c -o $@
 
 $(OUTPUT): Makefile $(SOURCE) $(HEADERS)
+ifeq ($(GIT_VERSION),"")
 	$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SOURCE) -o $(OUTPUT)
+else
+	$(CC) $(CFLAGS) $(SANITY_FLAGS) -DGIT_FULL_VERSION=\"$(GIT_VERSION)\" $(SOURCE) -o $(OUTPUT)
+endif
 
 run: $(OUTPUT)
 	./$(OUTPUT)

README.md

@@ -57,17 +57,17 @@ cpufetch is a command-line tool written in C that displays the CPU information i
 
 ## 1. Support
 
-| OS          | x86_64 / x86       | ARM                | PowerPC            |
+| OS          | x86_64 / x86       | ARM                | RISC-V             | PowerPC            |
-|:-----------:|:------------------:|:------------------:|:------------------:|
+|:-----------:|:------------------:|:------------------:|:------------------:|:------------------:|
-| GNU / Linux | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| GNU / Linux | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
-| Windows     | :heavy_check_mark: | :x:                | :x:                |
+| Windows     | :heavy_check_mark: | :x:                | :x:                | :x:                |
-| Android     | :heavy_check_mark: | :heavy_check_mark: | :x:                |
+| Android     | :heavy_check_mark: | :heavy_check_mark: | :x:                | :x:                |
-| macOS       | :heavy_check_mark: | :heavy_check_mark: | :x:                |
+| macOS       | :heavy_check_mark: | :heavy_check_mark: | :x:                | :heavy_check_mark: |
-| FreeBSD     | :heavy_check_mark: | :x:                | :x:                |
+| FreeBSD     | :heavy_check_mark: | :x:                | :x:                | :x:                |
 
 **NOTES:**
 - Colors will be used in Windows only if the terminal supports it.
-- Support in macOS ARM is limited to Apple M1 only
+- Support in macOS ARM is limited to Apple chips only
 
 ## 2. Installation
 ### 2.1 Installing from a package
@@ -151,10 +151,12 @@ See [cpufetch contributing guidelines](https://github.com/Dr-Noob/cpufetch/blob/
 
 ## 7. Acknowledgements
 Thanks to the fellow contributors and interested people in the project. Special thanks to:
-- [Gonzalocl](https://github.com/Gonzalocl), [OdnetninI](https://github.com/OdnetninI): Tested cpufetch in the earlier versions of the project in many different CPUs.
+- [Gonzalocl](https://github.com/Gonzalocl) and [OdnetninI](https://github.com/OdnetninI): Tested cpufetch in the earlier versions of the project in many different CPUs.
 - [Kyngo](https://github.com/Kyngo): Tested cpufetch in the Apple M1 CPU.
-- [avollmerhaus](https://github.com/avollmerhaus): Gave me ssh acess to a PowerPC machine, allowing me to develop the PowerPC port.
+- [avollmerhaus](https://github.com/avollmerhaus): Helped with PowerPC port giving ssh access to a PowerPC machine.
-- [bbonev](https://github.com/bbonev), [stephan-cr](https://github.com/stephan-cr): Reviewed the source code.
+- [bbonev](https://github.com/bbonev) and [stephan-cr](https://github.com/stephan-cr): Reviewed the source code.
+- [mdoksa76](https://github.com/mdoksa76) and [exkc](https://github.com/exkc): Excellent ideas and feedback for supporting Allwinner SoCs.
+- [Sakura286](https://github.com/Sakura286), [exkc](https://github.com/exkc) and [Patola](https://github.com/Patola): Helped with RISC-V port with ssh access, ideas, testing, etc.
 
 ## 8. cpufetch for GPUs (gpufetch)
 See [gpufetch](https://github.com/Dr-Noob/gpufetch) project!

src/arm/midr.c

@@ -13,10 +13,10 @@
 #endif
 
 #include "../common/global.h"
+#include "../common/soc.h"
 #include "udev.h"
 #include "midr.h"
 #include "uarch.h"
-#include "soc.h"
 
 bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
   return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
@@ -80,26 +80,21 @@ int64_t get_peak_performance(struct cpuInfo* cpu) {
     }
   }
 
-  int64_t flops = 0;
+  int64_t total_flops = 0;
   ptr = cpu;
 
-  if(cpu->soc->soc_vendor == SOC_VENDOR_APPLE) {
-    // Special case for M1/M2
-    // First we find the E cores, then the P
-    // M1 have 2 (E cores) or 4 (P cores) FMA units
-    // Source: https://dougallj.github.io/applecpu/firestorm-simd.html
-    flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000) * 2 * 4 * 2;
-    ptr = ptr->next_cpu;
-    flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000) * 2 * 4 * 4;
-  }
-  else {
   for(int i=0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
-      flops += ptr->topo->total_cores * (get_freq(ptr->freq) * 1000000);
+    int vpus = get_number_of_vpus(ptr);
-    }
+    int vpus_width = get_vpus_width(ptr);
-    if(cpu->feat->NEON) flops = flops * 4;
+    bool has_fma = has_fma_support(ptr);
+
+    int64_t flops = ptr->topo->total_cores * get_freq(ptr->freq) * 1000000 * vpus * (vpus_width/32);
+    if(has_fma) flops = flops * 2;
+
+    total_flops += flops;
   }
 
-  return flops;
+  return total_flops;
 }
 
 uint32_t fill_ids_from_midr(uint32_t* midr_array, int32_t* freq_array, uint32_t* ids_array, int len) {
@@ -141,7 +136,7 @@ void init_cpu_info(struct cpuInfo* cpu) {
 // true...
 // ARM32 https://elixir.bootlin.com/linux/latest/source/arch/arm/include/uapi/asm/hwcap.h
 // ARM64 https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/uapi/asm/hwcap.h
-struct features* get_features_info() {
+struct features* get_features_info(void) {
   struct features* feat = emalloc(sizeof(struct features));
   bool *ptr = &(feat->AES);
   for(uint32_t i = 0; i < sizeof(struct features)/sizeof(bool); i++, ptr++) {
@@ -356,9 +351,33 @@ struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
     cpu->peak_performance = get_peak_performance(cpu);
   }
   else if(cpu_family == CPUFAMILY_ARM_AVALANCHE_BLIZZARD) {
-    // Just the "normal" M2 exists for now
     cpu->num_cpus = 2;
+    // Now detect the M2 version
+    uint32_t cpu_subfamily = get_sys_info_by_name("hw.cpusubfamily");
+    if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
+      // Apple M2
       fill_cpu_info_avalanche_blizzard(cpu, 4, 4);
+    }
+    else if(cpu_subfamily == CPUSUBFAMILY_ARM_HS) {
+      // Apple M2 Pro/Max/Ultra. Detect number of cores
+      uint32_t physicalcpu = get_sys_info_by_name("hw.physicalcpu");
+      if(physicalcpu == 24) {
+        // M2 Ultra
+        fill_cpu_info_avalanche_blizzard(cpu, 16, 8);
+      }
+      else if(physicalcpu == 10 || physicalcpu == 12) {
+        // M2 Pro/Max
+        fill_cpu_info_avalanche_blizzard(cpu, physicalcpu-4, 4);
+      }
+      else {
+        printBug("Found invalid physical cpu number: %d", physicalcpu);
+        return NULL;
+      }
+    }
+    else {
+      printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
+      return NULL;
+    }
     cpu->soc = get_soc();
     cpu->peak_performance = get_peak_performance(cpu);
   }
@@ -371,7 +390,7 @@ struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
 }
 #endif
 
-struct cpuInfo* get_cpu_info() {
+struct cpuInfo* get_cpu_info(void) {
   struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
   init_cpu_info(cpu);
 

src/arm/midr.h

@@ -3,7 +3,7 @@
 
 #include "../common/cpu.h"
 
-struct cpuInfo* get_cpu_info();
+struct cpuInfo* get_cpu_info(void);
 
 uint32_t get_nsockets(struct topology* topo);
 char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_socket);

src/arm/soc.c

@@ -15,47 +15,14 @@
 #define min(a,b) (((a)<(b))?(a):(b))
 #define ARRAY_SIZE(arr)     (sizeof(arr) / sizeof((arr)[0]))
 
-static char* soc_trademark_string[] = {
-  [SOC_VENDOR_SNAPDRAGON] = "Snapdragon ",
-  [SOC_VENDOR_MEDIATEK]   = "MediaTek ",
-  [SOC_VENDOR_EXYNOS]     = "Exynos ",
-  [SOC_VENDOR_KIRIN]      = "Kirin ",
-  [SOC_VENDOR_BROADCOM]   = "Broadcom BCM",
-  [SOC_VENDOR_APPLE]      = "Apple ",
-  [SOC_VENDOR_ALLWINNER]  = "Allwinner "
-};
-
 static char* soc_rpi_string[] = {
   "BCM2835",
   "BCM2836",
   "BCM2837",
-  "BCM2711"
+  "BCM2711",
+  "BCM2712"
 };
 
-void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process) {
-  soc->soc_model = soc_model;
-  soc->soc_vendor = get_soc_vendor_from_soc(soc_model);
-  soc->process = process;
-  int len = strlen(soc_name) + strlen(soc_trademark_string[soc->soc_vendor]) + 1;
-  soc->soc_name = emalloc(sizeof(char) * len);
-  memset(soc->soc_name, 0, sizeof(char) * len);
-  sprintf(soc->soc_name, "%s%s", soc_trademark_string[soc->soc_vendor], soc_name);
-}
-
-bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
-  int len1 = strlen(raw_name);
-  int len2 = strlen(expected_name);
-  int len = min(len1, len2);
-
-  if(strncmp(raw_name, expected_name, len) != 0) {
-    return false;
-  }
-  else {
-    fill_soc(soc, soc_name, soc_model, process);
-    return true;
-  }
-}
-
 char* toupperstr(char* str) {
   int len = strlen(str) + 1;
   char* ret = emalloc(sizeof(char) * len);
@@ -68,11 +35,61 @@ char* toupperstr(char* str) {
   return ret;
 }
 
-#define SOC_START if (false) {}
+uint32_t get_sid_from_nvmem(char* buf) {
-#define SOC_EQ(raw_name, expected_name, soc_name, soc_model, soc, process) \
+  uint32_t sid = 0;
-   else if (match_soc(soc, raw_name, expected_name, soc_name, soc_model, process)) return true;
+  sid += (unsigned char) buf[0] * 1<<0;
-#define SOC_END else { return false; }
+  sid += (unsigned char) buf[1] * 1<<8;
-// Exynos special define
+  sid += (unsigned char) buf[2] * 1<<16;
+  sid += (unsigned char) buf[3] * 1<<24;
+  return sid;
+}
+
+// Security ID (SID) is an identifier that can help with SoC detection
+// in Allwinner SoCs (https://linux-sunxi.org/SID_Register_Guide#Security_ID)
+// SIDs list:
+// - https://linux-sunxi.org/SID_Register_Guide#Currently_known_SID.27s
+// - https://github.com/Dr-Noob/cpufetch/issues/173
+bool get_sunxisoc_from_sid(struct system_on_chip* soc, char* raw_name, uint32_t sid) {
+  typedef struct {
+    uint32_t sid;
+    struct system_on_chip soc;
+  } sidToSoC;
+
+  sidToSoC socFromSid[] = {
+    // --- sun8i Family ---
+    // H2+
+    {0x02c00042, {SOC_ALLWINNER_H2PLUS, SOC_VENDOR_ALLWINNER, 40, "H2+",  raw_name} },
+    {0x02c00142, {SOC_ALLWINNER_H2PLUS, SOC_VENDOR_ALLWINNER, 40, "H2+",  raw_name} },
+    // H3
+    {0x02c00181, {SOC_ALLWINNER_H3,     SOC_VENDOR_ALLWINNER, 40, "H3",   raw_name} },
+    {0x02c00081, {SOC_ALLWINNER_H3,     SOC_VENDOR_ALLWINNER, 40, "H3",   raw_name} },
+    // Others
+    {0x12c00017, {SOC_ALLWINNER_R40,    SOC_VENDOR_ALLWINNER, 40, "R40",  raw_name} },
+    {0x12c00000, {SOC_ALLWINNER_V3S,    SOC_VENDOR_ALLWINNER, 40, "V3s",  raw_name} }, // 40nm is only my guess, no source
+    // --- sun50i Family ---
+    {0x82800001, {SOC_ALLWINNER_H5,     SOC_VENDOR_ALLWINNER, 40, "H5",   raw_name} },
+    {0x82c00007, {SOC_ALLWINNER_H6,     SOC_VENDOR_ALLWINNER, 28, "H6",   raw_name} },
+    {0x92c000bb, {SOC_ALLWINNER_H64,    SOC_VENDOR_ALLWINNER, 40, "H64",  raw_name} }, // Same as A64
+    {0x32c05000, {SOC_ALLWINNER_H616,   SOC_VENDOR_ALLWINNER, 28, "H616", raw_name} },
+    {0x92c000ba, {SOC_ALLWINNER_A64,    SOC_VENDOR_ALLWINNER, 40, "A64",  raw_name} },
+    // Unknown
+    {0x00000000, {UNKNOWN,              SOC_VENDOR_UNKNOWN,   -1, "",    raw_name} }
+  };
+
+  int index = 0;
+  while(socFromSid[index].sid != 0x0) {
+    if(socFromSid[index].sid == sid) {
+      fill_soc(soc, socFromSid[index].soc.soc_name, socFromSid[index].soc.soc_model, socFromSid[index].soc.process);
+      return true;
+    }
+    index++;
+  }
+
+  printErr("SID was found but it does not match any known SIDs: %08x", sid);
+  return false;
+}
+
+// Exynos special define (not included in src/common/soc.h)
 #define SOC_EXY_EQ(raw_name, tmpsoc, soc_name, soc_model, soc, process)             \
    sprintf(tmpsoc, "exynos%s", soc_name);                                           \
    if (match_soc(soc, raw_name, tmpsoc, soc_name, soc_model, process)) return true; \
@@ -88,12 +105,13 @@ bool match_broadcom(char* soc_name, struct system_on_chip* soc) {
   if((tmp = strstr(soc_name, "BCM")) == NULL)
     return false;
 
+  soc->soc_vendor = SOC_VENDOR_BROADCOM;
+
   SOC_START
   SOC_EQ(tmp, "BCM2835",              "2835",              SOC_BCM_2835,   soc, 65)
   SOC_EQ(tmp, "BCM2836",              "2836",              SOC_BCM_2836,   soc, 40)
   SOC_EQ(tmp, "BCM2837",              "2837",              SOC_BCM_2837,   soc, 40)
   SOC_EQ(tmp, "BCM2837B0",            "2837B0",            SOC_BCM_2837B0, soc, 40)
-  SOC_EQ(tmp, "BCM2711",              "2711",              SOC_BCM_2711,   soc, 28)
   SOC_EQ(tmp, "BCM21553",             "21553",             SOC_BCM_21553,  soc, 65)
   SOC_EQ(tmp, "BCM21553-Thunderbird", "21553 Thunderbird", SOC_BCM_21553T, soc, 65)
   SOC_EQ(tmp, "BCM21663",             "21663",             SOC_BCM_21663,  soc, 40)
@@ -103,6 +121,8 @@ bool match_broadcom(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "BCM28145",             "28145",             SOC_BCM_28145,  soc, 40)
   SOC_EQ(tmp, "BCM2157",              "2157",              SOC_BCM_2157,   soc, 65)
   SOC_EQ(tmp, "BCM21654",             "21654",             SOC_BCM_21654,  soc, 40)
+  SOC_EQ(tmp, "BCM2711",              "2711",              SOC_BCM_2711,   soc, 28)
+  SOC_EQ(tmp, "BCM2712",              "2712",              SOC_BCM_2712,   soc, 16)
   SOC_END
 }
 
@@ -114,6 +134,8 @@ bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
   if((tmp = strstr(soc_name, "hi")) == NULL)
     return false;
 
+  soc->soc_vendor = SOC_VENDOR_KIRIN;
+
   SOC_START
   SOC_EQ(tmp, "hi3620GFC",  "K3V2",  SOC_HISILICON_3620, soc, 40)
   //SOC_EQ(tmp, "?",        "K3V2E", SOC_KIRIN, soc,  ?)
@@ -153,6 +175,8 @@ bool match_exynos(char* soc_name, struct system_on_chip* soc) {
   else if((tmp = strstr(soc_name, "exynos")) != NULL);
   else return false;
 
+  soc->soc_vendor = SOC_VENDOR_EXYNOS;
+
   // Because exynos are recently using "exynosXXXX" instead
   // of "universalXXXX" as codenames, SOC_EXY_EQ will check for
   // both cases, since it seems that there are some SoCs that
@@ -207,6 +231,8 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
   if((tmp = strstr(soc_name_upper, "MT")) == NULL)
     return false;
 
+  soc->soc_vendor = SOC_VENDOR_MEDIATEK;
+
   SOC_START
   // Dimensity //
   SOC_EQ(tmp, "MT6893",   "Dimensity 1200",  SOC_MTK_MT6893,   soc, 6)
@@ -335,6 +361,8 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
   else if((tmp = strstr(soc_name_upper, "QSD")) != NULL);
   else return false;
 
+  soc->soc_vendor = SOC_VENDOR_SNAPDRAGON;
+
   SOC_START
   // Snapdragon S1 //
   SOC_EQ(tmp, "QSD8650",        "S1",        SOC_SNAPD_QSD8650,        soc, 65)
@@ -430,6 +458,7 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "SM7125",         "720G",      SOC_SNAPD_SM7125,         soc,  8)
   SOC_EQ(tmp, "SM7150-AA",      "730",       SOC_SNAPD_SM7150_AA,      soc,  8)
   SOC_EQ(tmp, "SM7150-AB",      "730G",      SOC_SNAPD_SM7150_AB,      soc,  8)
+  SOC_EQ(tmp, "SDM730G",        "730G",      SOC_SNAPD_SM7150_AB,      soc,  8) // Issue #174
   SOC_EQ(tmp, "SM7150-AC",      "732G",      SOC_SNAPD_SM7150_AC,      soc,  8)
   SOC_EQ(tmp, "SM7225",         "750G",      SOC_SNAPD_SM7225,         soc,  8)
   SOC_EQ(tmp, "SM7250-AA",      "765",       SOC_SNAPD_SM7250_AA,      soc,  7)
@@ -466,40 +495,25 @@ bool match_allwinner(char* soc_name, struct system_on_chip* soc) {
   if((tmp = strstr(soc_name, "sun")) == NULL)
     return false;
 
+  soc->soc_vendor = SOC_VENDOR_ALLWINNER;
+
   SOC_START
-  // A series 32 bits
+  // SoCs we can detect just with with the name
   SOC_EQ(tmp, "sun4i", "A10",   SOC_ALLWINNER_A10,  soc, 55)
-  SOC_EQ(tmp, "sun5i", "A13",   SOC_ALLWINNER_A13,  soc, 55)
-  SOC_EQ(tmp, "sun5i", "A10s",  SOC_ALLWINNER_A10S, soc, 55)
-  SOC_EQ(tmp, "sun7i", "A20",   SOC_ALLWINNER_A20,  soc, 40)
-  SOC_EQ(tmp, "sun8i", "A23",   SOC_ALLWINNER_A23,  soc, 40)
   SOC_EQ(tmp, "sun6i", "A31",   SOC_ALLWINNER_A31,  soc, 40)
-  SOC_EQ(tmp, "sun6i", "A31s",  SOC_ALLWINNER_A31S, soc, 40)
+  SOC_EQ(tmp, "sun7i", "A20",   SOC_ALLWINNER_A20,  soc, 40)
-  SOC_EQ(tmp, "sun8i", "A33",   SOC_ALLWINNER_A33,  soc, 40)
+  else {
-  SOC_EQ(tmp, "sun8i", "A40",   SOC_ALLWINNER_A40,  soc, 40)
+    // sun5i/sun8i/sun9i/sun50i will fall here
-  SOC_EQ(tmp, "sun8i", "A50",   SOC_ALLWINNER_A50,  soc, 28)
+    // We need SID to actually distingish between the exact model
-  SOC_EQ(tmp, "sun9i", "A80",   SOC_ALLWINNER_A80,  soc, 28)
+    int filelen;
-  SOC_EQ(tmp, "sun8i", "A83T",  SOC_ALLWINNER_A83T, soc, 28)
+    char* sid_nvmem = read_file(_PATH_SUNXI_NVMEM, &filelen);
-
+    if(sid_nvmem == NULL) {
-  // H series 32 bits
+      printWarn("read_file: %s: %s", _PATH_SUNXI_NVMEM, strerror(errno));
-  SOC_EQ(tmp, "sun8i", "H2+",   SOC_ALLWINNER_HZP,  soc, 40)
+      return false;
-  SOC_EQ(tmp, "sun8i", "H3",    SOC_ALLWINNER_H3,   soc, 40)
+    }
-  SOC_EQ(tmp, "sun8i", "H8",    SOC_ALLWINNER_H8,   soc, 28)
+    uint32_t sid = get_sid_from_nvmem(sid_nvmem);
-
+    return get_sunxisoc_from_sid(soc, soc_name, sid);
-  // H series 64 bits
+  }
-  SOC_EQ(tmp, "sun50i", "H5",   SOC_ALLWINNER_H5,   soc, 40)
-  SOC_EQ(tmp, "sun50i", "H6",   SOC_ALLWINNER_H6,   soc, 28)
-  SOC_EQ(tmp, "sun50i", "H616", SOC_ALLWINNER_H616, soc, 28)
-
-  // R series 32 bits
-  SOC_EQ(tmp, "sun5i", "R8",    SOC_ALLWINNER_R8,   soc, 55)
-  SOC_EQ(tmp, "sun8i", "R16",   SOC_ALLWINNER_R16,  soc, 40)
-  SOC_EQ(tmp, "sun8i", "R40",   SOC_ALLWINNER_R40,  soc, 40)
-  SOC_EQ(tmp, "sun8i", "R58",   SOC_ALLWINNER_R58,  soc, 28)
-
-  // R series  64 bits
-  SOC_EQ(tmp, "sun50i", "R329", SOC_ALLWINNER_R328, soc, 28)
-  SOC_END
 }
 
 bool match_special(char* soc_name, struct system_on_chip* soc) {
@@ -517,6 +531,12 @@ bool match_special(char* soc_name, struct system_on_chip* soc) {
     return true;
   }
 
+  // Snapdragon 8 Gen 1 reported as "taro"
+  if(strcmp(soc_name, "taro") == 0) {
+    fill_soc(soc, "8 Gen 1", SOC_SNAPD_SM8450, 4);
+    return true;
+  }
+
   return false;
 }
 
@@ -600,6 +620,75 @@ struct system_on_chip* guess_soc_from_cpuinfo(struct system_on_chip* soc) {
   return soc;
 }
 
+char* get_rk_efuse(void) {
+  int filelen;
+  char* rk_soc = read_file(_PATH_RK_EFUSE0, &filelen);
+  if(rk_soc == NULL) {
+    printWarn("read_file: %s: %s", _PATH_RK_EFUSE0, strerror(errno));
+    rk_soc = read_file(_PATH_RK_OTP0, &filelen);
+    if(rk_soc == NULL) {
+      printWarn("read_file: %s: %s", _PATH_RK_OTP0, strerror(errno));
+    }
+  }
+  return rk_soc;
+}
+
+bool get_rk_soc_from_efuse(struct system_on_chip* soc, char* efuse) {
+  typedef struct {
+    uint16_t rk_soc;
+    struct system_on_chip soc;
+  } rkToSoC;
+
+  uint16_t rk_soc = efuse[2]*256 + efuse[3];
+
+  // https://wikimovel.com/index.php/Rockchip
+  rkToSoC socFromRK[] = {
+    // TODO: Add RK2XXX
+    // RK3XXX
+    {0x2388, {SOC_ROCKCHIP_3288,  SOC_VENDOR_ROCKCHIP, 28, "RK3288",  NULL} },
+    {0x2392, {SOC_ROCKCHIP_3229,  SOC_VENDOR_ROCKCHIP, 28, "RK3229",  NULL} }, // https://gadgetversus.com/processor/rockchip-rk3229-vs-rockchip-rk3128/
+    {0x3380, {SOC_ROCKCHIP_3308,  SOC_VENDOR_ROCKCHIP, 28, "RK3308",  NULL} }, // https://en.t-firefly.com/product/rocrk3308cc?theme=pc
+    {0x3381, {SOC_ROCKCHIP_3318,  SOC_VENDOR_ROCKCHIP, 28, "RK3318",  NULL} },
+    {0x3362, {SOC_ROCKCHIP_3326,  SOC_VENDOR_ROCKCHIP, 28, "RK3326",  NULL} },
+    {0x3382, {SOC_ROCKCHIP_3328,  SOC_VENDOR_ROCKCHIP, 28, "RK3328",  NULL} },
+    {0x3386, {SOC_ROCKCHIP_3368,  SOC_VENDOR_ROCKCHIP, 28, "RK3368",  NULL} },
+    {0x3399, {SOC_ROCKCHIP_3399,  SOC_VENDOR_ROCKCHIP, 28, "RK3399",  NULL} },
+    {0x5366, {SOC_ROCKCHIP_3566,  SOC_VENDOR_ROCKCHIP, 22, "RK3566",  NULL} },
+    {0x5386, {SOC_ROCKCHIP_3568,  SOC_VENDOR_ROCKCHIP, 22, "RK3568",  NULL} },
+    {0x5388, {SOC_ROCKCHIP_3588,  SOC_VENDOR_ROCKCHIP,  8, "RK3588",  NULL} },
+    {0x3588, {SOC_ROCKCHIP_3588S, SOC_VENDOR_ROCKCHIP,  8, "RK3588S", NULL} }, // https://github.com/Dr-Noob/cpufetch/issues/188
+    // Unknown
+    {0x0000, {UNKNOWN,            SOC_VENDOR_UNKNOWN,   -1,       "", NULL} }
+  };
+
+  int index = 0;
+  while(socFromRK[index].rk_soc != 0x0) {
+    if(socFromRK[index].rk_soc == rk_soc) {
+      fill_soc(soc, socFromRK[index].soc.soc_name, socFromRK[index].soc.soc_model, socFromRK[index].soc.process);
+      return true;
+    }
+    index++;
+  }
+
+  printErr("RK SoC was found but it does not match any known SoCs: 0x%04x", rk_soc);
+  return false;
+}
+
+struct system_on_chip* guess_soc_from_nvmem(struct system_on_chip* soc) {
+  // This method is only valid for Rockchip SoCs
+  char* rk_soc = get_rk_efuse();
+  if(rk_soc != NULL) {
+    if(rk_soc[0] == 0x52 && rk_soc[1] == 0x4b) {
+      get_rk_soc_from_efuse(soc, rk_soc);
+      return soc;
+    }
+    else {
+      printWarn("guess_soc_from_nvmem: efuse found, but contains unexpected header: 0x%x 0x%x", rk_soc[0], rk_soc[1]);
+    }
+  }
+  return soc;
+}
+
 int hex2int(char c) {
   if (c >= '0' && c <= '9')
     return c - '0';
@@ -611,7 +700,13 @@ int hex2int(char c) {
   return -1;
 }
 
-// https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md
+/*
+ * https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#raspberry-pi-revision-codes:
+ * NOTE: As of the 4.9 kernel, all Raspberry Pi computers report BCM2835, even those with BCM2836,
+ * BCM2837 and BCM2711 processors. You should not use this string to detect the processor. Decode the
+ * revision code using the information below.
+ * https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#new-style-revision-codes-in-use
+ */
 struct system_on_chip* guess_soc_raspbery_pi(struct system_on_chip* soc) {
   char* revision = get_revision_from_cpuinfo();
 
@@ -627,22 +722,19 @@ struct system_on_chip* guess_soc_raspbery_pi(struct system_on_chip* soc) {
 
   int arr_size = ARRAY_SIZE(soc_rpi_string);
   int pppp = hex2int(revision[2]);
-  if(pppp == -1) {
+  if(pppp < 0) {
-    printErr("[RPi] Found invalid RPi PPPP code: %s", revision[2]);
+    printBug("[RPi] Found invalid RPi PPPP code: %s", pppp);
     return soc;
   }
 
-  if(pppp > arr_size) {
+  if(pppp > arr_size-1) {
-    printErr("[RPi] Found invalid RPi PPPP code: %d while max is %d", pppp, arr_size);
+    printBug("[RPi] Found invalid RPi PPPP code: %d (max is %d)", pppp, arr_size-1);
     return soc;
   }
 
   char* soc_raw_name = soc_rpi_string[pppp];
-  /*int soc_len = strlen(soc_raw_name);
-  soc->raw_name = emalloc(sizeof(char) * (soc_len + 1));
-  strncpy(soc->raw_name, soc_raw_name, soc_len + 1);*/
-
   match_broadcom(soc_raw_name, soc);
+
   return soc;
 }
 
@@ -683,6 +775,23 @@ struct system_on_chip* guess_soc_apple(struct system_on_chip* soc) {
     if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
       fill_soc(soc, "M2", SOC_APPLE_M2, 5);
     }
+    else if(cpu_subfamily == CPUSUBFAMILY_ARM_HS) {
+      fill_soc(soc, "M2 Pro", SOC_APPLE_M2_PRO, 5);
+    }
+    else if(cpu_subfamily == CPUSUBFAMILY_ARM_HC_HD) {
+      // Could be M2 Max or M2 Ultra (2x M1 Max)
+      uint32_t physicalcpu = get_sys_info_by_name("hw.physicalcpu");
+      if(physicalcpu == 24) {
+        fill_soc(soc, "M2 Ultra", SOC_APPLE_M2_ULTRA, 5);
+      }
+      else if(physicalcpu == 12) {
+        fill_soc(soc, "M2 Max", SOC_APPLE_M2_MAX, 5);
+      }
+      else {
+        printBug("Found invalid physical cpu number: %d", physicalcpu);
+        soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+      }
+    }
     else {
       printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
       soc->soc_vendor = SOC_VENDOR_UNKNOWN;
@@ -696,10 +805,11 @@ struct system_on_chip* guess_soc_apple(struct system_on_chip* soc) {
 }
 #endif
 
-struct system_on_chip* get_soc() {
+struct system_on_chip* get_soc(void) {
   struct system_on_chip* soc = emalloc(sizeof(struct system_on_chip));
   soc->raw_name = NULL;
   soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+  soc->soc_model = SOC_MODEL_UNKNOWN;
   soc->process = UNKNOWN;
 
 #ifdef __linux__
@@ -707,7 +817,7 @@ struct system_on_chip* get_soc() {
   if(isRPi) {
     soc = guess_soc_raspbery_pi(soc);
     if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
-      printWarn("SoC detection failed using revision code");
+      printErr("[RPi] SoC detection failed using revision code, falling back to cpuinfo detection");
     }
     else {
       return soc;
@@ -716,17 +826,25 @@ struct system_on_chip* get_soc() {
 
   soc = guess_soc_from_cpuinfo(soc);
   if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
-    if(soc->raw_name != NULL)
+    if(soc->raw_name != NULL) {
       printWarn("SoC detection failed using /proc/cpuinfo: Found '%s' string", soc->raw_name);
-    else
+    }
+    else {
       printWarn("SoC detection failed using /proc/cpuinfo: No string found");
+    }
 #ifdef __ANDROID__
     soc = guess_soc_from_android(soc);
-    if(soc->raw_name == NULL)
+    if(soc->raw_name == NULL) {
       printWarn("SoC detection failed using Android: No string found");
-    else if(soc->soc_vendor == SOC_VENDOR_UNKNOWN)
+    }
+    else if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
       printWarn("SoC detection failed using Android: Found '%s' string", soc->raw_name);
+    }
 #endif // ifdef __ANDROID__
+    // If cpufinfo/Android (if available) detection fails, try with nvmem
+    if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+      soc = guess_soc_from_nvmem(soc);
+    }
   }
 #elif defined __APPLE__ || __MACH__
   soc = guess_soc_apple(soc);
@@ -738,35 +856,12 @@ struct system_on_chip* get_soc() {
   }
 #endif // ifdef __linux__
 
-  if(soc->raw_name == NULL) {
+  if(soc->soc_model == SOC_MODEL_UNKNOWN) {
+    // raw_name might not be NULL, but if we were unable to find
+    // the exact SoC, just print "Unkwnown"
     soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
     snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
   }
 
   return soc;
 }
-
-char* get_soc_name(struct system_on_chip* soc) {
-  if(soc->soc_vendor == SOC_VENDOR_UNKNOWN)
-    return soc->raw_name;
-  return soc->soc_name;
-}
-
-VENDOR get_soc_vendor(struct system_on_chip* soc) {
-  return soc->soc_vendor;
-}
-
-char* get_str_process(struct system_on_chip* soc) {
-  char* str;
-
-  if(soc->process == UNKNOWN) {
-    str = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
-    snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
-  }
-  else {
-    str = emalloc(sizeof(char) * 5);
-    memset(str, 0, sizeof(char) * 5);
-    snprintf(str, 5, "%dnm", soc->process);
-  }
-  return str;
-}

src/arm/soc.h

@@ -1,33 +1,10 @@
-#ifndef __SOC__
+#ifndef __SOC_ARM__
-#define __SOC__
+#define __SOC_ARM__
 
 #include "../common/cpu.h"
+#include "../common/soc.h"
 #include <stdint.h>
 
-typedef int32_t SOC;
+struct system_on_chip* get_soc(void);
-
-enum {
-  SOC_VENDOR_UNKNOWN,
-  SOC_VENDOR_SNAPDRAGON,
-  SOC_VENDOR_MEDIATEK,
-  SOC_VENDOR_EXYNOS,
-  SOC_VENDOR_KIRIN,
-  SOC_VENDOR_BROADCOM,
-  SOC_VENDOR_APPLE,
-  SOC_VENDOR_ALLWINNER
-};
-
-struct system_on_chip {
-  SOC soc_model;
-  VENDOR soc_vendor;
-  int32_t process;
-  char* soc_name;
-  char* raw_name;    
-};
-
-struct system_on_chip* get_soc();
-char* get_soc_name(struct system_on_chip* soc);
-VENDOR get_soc_vendor(struct system_on_chip* soc);
-char* get_str_process(struct system_on_chip* soc);
 
 #endif

src/arm/socs.h

@@ -10,7 +10,6 @@ enum {
   SOC_BCM_2836,
   SOC_BCM_2837,
   SOC_BCM_2837B0,
-  SOC_BCM_2711,
   SOC_BCM_21553,
   SOC_BCM_21553T,
   SOC_BCM_21663,
@@ -20,6 +19,8 @@ enum {
   SOC_BCM_28145,
   SOC_BCM_2157,
   SOC_BCM_21654,
+  SOC_BCM_2711,
+  SOC_BCM_2712,
   // Hisilicon //
   SOC_HISILICON_3620,
   SOC_HISILICON_3630,
@@ -252,12 +253,16 @@ enum {
   SOC_SNAPD_SM8250,
   SOC_SNAPD_SM8250_AB,
   SOC_SNAPD_SM8350,
+  SOC_SNAPD_SM8450,
   // APPLE
   SOC_APPLE_M1,
   SOC_APPLE_M1_PRO,
   SOC_APPLE_M1_MAX,
   SOC_APPLE_M1_ULTRA,
   SOC_APPLE_M2,
+  SOC_APPLE_M2_PRO,
+  SOC_APPLE_M2_MAX,
+  SOC_APPLE_M2_ULTRA,
   // ALLWINNER
   SOC_ALLWINNER_A10,
   SOC_ALLWINNER_A13,
@@ -269,29 +274,49 @@ enum {
   SOC_ALLWINNER_A33,
   SOC_ALLWINNER_A40,
   SOC_ALLWINNER_A50,
+  SOC_ALLWINNER_A64,
   SOC_ALLWINNER_A80,
   SOC_ALLWINNER_A83T,
+  SOC_ALLWINNER_V3S,
   SOC_ALLWINNER_HZP,
+  SOC_ALLWINNER_H2PLUS,
   SOC_ALLWINNER_H3,
   SOC_ALLWINNER_H8,
   SOC_ALLWINNER_H5,
   SOC_ALLWINNER_H6,
+  SOC_ALLWINNER_H64,
   SOC_ALLWINNER_H616,
   SOC_ALLWINNER_R8,
   SOC_ALLWINNER_R16,
   SOC_ALLWINNER_R40,
   SOC_ALLWINNER_R58,
-  SOC_ALLWINNER_R328
+  SOC_ALLWINNER_R328,
+  // ROCKCHIP
+  SOC_ROCKCHIP_3288,
+  SOC_ROCKCHIP_3229,
+  SOC_ROCKCHIP_3308,
+  SOC_ROCKCHIP_3318,
+  SOC_ROCKCHIP_3326,
+  SOC_ROCKCHIP_3328,
+  SOC_ROCKCHIP_3368,
+  SOC_ROCKCHIP_3399,
+  SOC_ROCKCHIP_3566,
+  SOC_ROCKCHIP_3568,
+  SOC_ROCKCHIP_3588,
+  SOC_ROCKCHIP_3588S,
+  // UNKNOWN
+  SOC_MODEL_UNKNOWN
 };
 
 inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
-  if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_21654) return SOC_VENDOR_BROADCOM;
+  if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_2712) return SOC_VENDOR_BROADCOM;
   else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_3690) return SOC_VENDOR_KIRIN;
   else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
   else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
-  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8350) return SOC_VENDOR_SNAPDRAGON;
+  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8450) return SOC_VENDOR_SNAPDRAGON;
-  else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M2) return SOC_VENDOR_APPLE;
+  else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M2_ULTRA) return SOC_VENDOR_APPLE;
   else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
+  else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588S) return SOC_VENDOR_ROCKCHIP;
   return SOC_VENDOR_UNKNOWN;
 }
 

src/arm/uarch.c

@@ -33,7 +33,8 @@ enum {
   ISA_ARMv8_2_A,
   ISA_ARMv8_3_A,
   ISA_ARMv8_4_A,
-  ISA_ARMv8_5_A
+  ISA_ARMv8_5_A,
+  ISA_ARMv9_A
 };
 
 enum {
@@ -65,9 +66,13 @@ enum {
   UARCH_CORTEX_A76,
   UARCH_CORTEX_A77,
   UARCH_CORTEX_A78,
+  UARCH_CORTEX_A510,
+  UARCH_CORTEX_A710,
   UARCH_CORTEX_X1,
+  UARCH_CORTEX_X2,
   UARCH_NEOVERSE_N1,
   UARCH_NEOVERSE_E1,
+  UARCH_NEOVERSE_V1,
   UARCH_SCORPION,
   UARCH_KRAIT,
   UARCH_KYRO,
@@ -136,9 +141,13 @@ static const ISA isas_uarch[] = {
   [UARCH_CORTEX_A76]   = ISA_ARMv8_2_A,
   [UARCH_CORTEX_A77]   = ISA_ARMv8_2_A,
   [UARCH_CORTEX_A78]   = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A510]   = ISA_ARMv9_A,
+  [UARCH_CORTEX_A710]   = ISA_ARMv9_A,
   [UARCH_CORTEX_X1]    = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_X2]    = ISA_ARMv9_A,
   [UARCH_NEOVERSE_N1]  = ISA_ARMv8_2_A,
   [UARCH_NEOVERSE_E1]  = ISA_ARMv8_2_A,
+  [UARCH_NEOVERSE_V1]  = ISA_ARMv8_4_A,
   [UARCH_BRAHMA_B15]   = ISA_ARMv7_A,   // Same as Cortex-A15
   [UARCH_BRAHMA_B53]   = ISA_ARMv8_A,   // Same as Cortex-A53
   [UARCH_THUNDERX]     = ISA_ARMv8_A,
@@ -178,7 +187,8 @@ static char* isas_string[] = {
   [ISA_ARMv8_2_A] = "ARMv8.2",
   [ISA_ARMv8_3_A] = "ARMv8.3",
   [ISA_ARMv8_4_A] = "ARMv8.4",
-  [ISA_ARMv8_5_A] = "ARMv8.5"
+  [ISA_ARMv8_5_A] = "ARMv8.5",
+  [ISA_ARMv9_A] = "ARMv9"
 };
 
 #define UARCH_START if (false) {}
@@ -246,8 +256,12 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   CHECK_UARCH(arch, cpu, 'A', 0xD0C, NA, NA, "Neoverse N1",           UARCH_NEOVERSE_N1,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD0D, NA, NA, "Cortex-A77",            UARCH_CORTEX_A77,   CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD0E, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD40, NA, NA, "Neoverse V1",           UARCH_NEOVERSE_V1,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD41, NA, NA, "Cortex-A78",            UARCH_CORTEX_A78,   CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD44, NA, NA, "Cortex-X1",             UARCH_CORTEX_X1,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD46, NA, NA, "Cortex‑A510",           UARCH_CORTEX_A510,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD47, NA, NA, "Cortex‑A710",           UARCH_CORTEX_A710,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD48, NA, NA, "Cortex-X2",             UARCH_CORTEX_X2,    CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD4A, NA, NA, "Neoverse E1",           UARCH_NEOVERSE_E1,  CPU_VENDOR_ARM)
 
   CHECK_UARCH(arch, cpu, 'B', 0x00F, NA, NA, "Brahma B15",            UARCH_BRAHMA_B15,   CPU_VENDOR_BROADCOM)
@@ -314,6 +328,96 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   return arch;
 }
 
+bool is_ARMv8_or_newer(struct cpuInfo* cpu) {
+  return cpu->arch->isa == ISA_ARMv8_A         ||
+         cpu->arch->isa == ISA_ARMv8_A_AArch32 ||
+         cpu->arch->isa == ISA_ARMv8_1_A       ||
+         cpu->arch->isa == ISA_ARMv8_2_A       ||
+         cpu->arch->isa == ISA_ARMv8_3_A       ||
+         cpu->arch->isa == ISA_ARMv8_4_A       ||
+         cpu->arch->isa == ISA_ARMv8_5_A       ||
+         cpu->arch->isa == ISA_ARMv9_A;
+}
+
+bool has_fma_support(struct cpuInfo* cpu) {
+  // Arm A64 Instruction Set Architecture
+  // https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions
+  return is_ARMv8_or_newer(cpu);
+}
+
+int get_vpus_width(struct cpuInfo* cpu) {
+  // If the CPU has NEON, width can be 64 or 128 [1].
+  // In >= ARMv8, NEON are 128 bits width [2]
+  // If the CPU has SVE/SVE2, width can be between 128-2048 [3],
+  // so we must check the exact width depending on
+  // the exact chip (Neoverse V1 uses 256b implementations.)
+  //
+  // [1] https://en.wikipedia.org/wiki/ARM_architecture_family#Advanced_SIMD_(Neon)
+  // [2] https://developer.arm.com/documentation/102474/0100/Fundamentals-of-Armv8-Neon-technology
+  // [3] https://www.anandtech.com/show/16640/arm-announces-neoverse-v1-n2-platforms-cpus-cmn700-mesh/5
+
+  MICROARCH ua = cpu->arch->uarch;
+  switch(ua) {
+    case UARCH_NEOVERSE_V1:
+      return 256;
+    default:
+      if(cpu->feat->NEON) {
+        if(is_ARMv8_or_newer(cpu)) {
+          return 128;
+        }
+        else {
+          return 64;
+        }
+      }
+      else {
+        return 32;
+      }
+  }
+}
+
+int get_number_of_vpus(struct cpuInfo* cpu) {
+  MICROARCH ua = cpu->arch->uarch;
+
+  switch(ua) {
+    case UARCH_FIRESTORM:   // [https://dougallj.github.io/applecpu/firestorm-simd.html]
+    case UARCH_AVALANCHE:   // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
+    case UARCH_CORTEX_X1:   // [https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging/3]
+    case UARCH_CORTEX_X2:   // [https://www.anandtech.com/show/16693/arm-announces-mobile-armv9-cpu-microarchitectures-cortexx2-cortexa710-cortexa510/2]
+    case UARCH_NEOVERSE_V1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v1]
+      return 4;
+    case UARCH_EXYNOS_M3:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
+    case UARCH_EXYNOS_M4:   // [https://en.wikichip.org/wiki/samsung/microarchitectures/m4#Block_Diagram]
+    case UARCH_EXYNOS_M5:   // [https://en.wikichip.org/wiki/samsung/microarchitectures/m5]
+      return 3;
+    case UARCH_ICESTORM:    // [https://dougallj.github.io/applecpu/icestorm-simd.html]
+    case UARCH_BLIZZARD:    // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
+    case UARCH_CORTEX_A57:  // [https://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/5]
+    case UARCH_CORTEX_A72:  // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]
+    case UARCH_CORTEX_A73:  // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]
+    case UARCH_CORTEX_A75:  // [https://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55/3]
+    case UARCH_CORTEX_A76:  // [https://www.anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse/3]
+    case UARCH_CORTEX_A77:  // [https://fuse.wikichip.org/news/2339/arm-unveils-cortex-a77-emphasizes-single-thread-performance]
+    case UARCH_CORTEX_A78:  // [https://fuse.wikichip.org/news/3536/arm-unveils-the-cortex-a78-when-less-is-more]
+    case UARCH_EXYNOS_M1:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
+    case UARCH_EXYNOS_M2:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
+    case UARCH_NEOVERSE_N1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_n1#Individual_Core]
+      return 2;
+    case UARCH_NEOVERSE_E1: // [https://www.anandtech.com/show/13959/arm-announces-neoverse-n1-platform/5]
+    // A510 is integrated as part of a Complex. Normally, each complex would incorporate two Cortex-A510 cores.
+    // Each complex incorporates a single VPU with 2 ports, so for each A510 there is theoretically 1 port.
+    case UARCH_CORTEX_A510: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a510#Vector_Processing_Unit_.28VPU.29]
+    // Not sure about this one since there is no explicit information saying it has one, but they never state it has more either.
+    case UARCH_CORTEX_A710: // [Arm Cortex‑A710 Core Technical Reference Manual]
+      return 1;
+    default:
+      // ARMv6
+      // ARMv7
+      // Remaining UARCH_CORTEX_AXX
+      // Old Snapdragon (e.g., Scorpion, Krait, etc)
+      return 1;
+  }
+}
+
 char* get_str_uarch(struct cpuInfo* cpu) {
   return cpu->arch->uarch_str;
 }

src/arm/uarch.h

@@ -6,6 +6,9 @@
 #include "midr.h"
 
 struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu);
+int get_number_of_vpus(struct cpuInfo* cpu);
+int get_vpus_width(struct cpuInfo* cpu);
+bool has_fma_support(struct cpuInfo* cpu);
 char* get_str_uarch(struct cpuInfo* cpu);
 void free_uarch_struct(struct uarch* arch);
 

src/arm/udev.c

@@ -3,8 +3,6 @@
 #include "midr.h"
 
 #define _PATH_DEVICETREE_MODEL       "/sys/firmware/devicetree/base/model"
-#define _PATH_CPUINFO                "/proc/cpuinfo"
-//#define _PATH_CPUINFO                "cpuinfo_debug"
 
 #define CPUINFO_CPU_IMPLEMENTER_STR  "CPU implementer\t: "
 #define CPUINFO_CPU_ARCHITECTURE_STR "CPU architecture: "
@@ -108,36 +106,15 @@ uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success) {
   return midr;
 }
 
-char* get_field_from_cpuinfo(char* CPUINFO_FIELD) {
+char* get_hardware_from_cpuinfo(void) {
-  int filelen;
-  char* buf;
-  if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
-    printWarn("read_file: %s: %s:\n", _PATH_CPUINFO, strerror(errno));
-    return NULL;
-  }
-
-  char* tmp1 = strstr(buf, CPUINFO_FIELD);
-  if(tmp1 == NULL) return NULL;
-  tmp1 = tmp1 + strlen(CPUINFO_FIELD);
-  char* tmp2 = strstr(tmp1, "\n");
-
-  int strlen = (1 + (tmp2-tmp1));
-  char* hardware = emalloc(sizeof(char) * strlen);
-  memset(hardware, 0, sizeof(char) * strlen);
-  strncpy(hardware, tmp1, tmp2-tmp1);
-
-  return hardware;
-}
-
-char* get_hardware_from_cpuinfo() {
   return get_field_from_cpuinfo(CPUINFO_HARDWARE_STR);
 }
 
-char* get_revision_from_cpuinfo() {
+char* get_revision_from_cpuinfo(void) {
   return get_field_from_cpuinfo(CPUINFO_REVISION_STR);
 }
 
-bool is_raspberry_pi() {
+bool is_raspberry_pi(void) {
   int filelen;
   char* buf;
   if((buf = read_file(_PATH_DEVICETREE_MODEL, &filelen)) == NULL) {

src/arm/udev.h

@@ -3,12 +3,16 @@
 
 #include "../common/udev.h"
 
+#define _PATH_SUNXI_NVMEM  "/sys/bus/nvmem/devices/sunxi-sid0/nvmem"
+#define _PATH_RK_EFUSE0    "/sys/bus/nvmem/devices/rockchip-efuse0/nvmem"
+#define _PATH_RK_OTP0      "/sys/bus/nvmem/devices/rockchip-otp0/nvmem"
+
 #define UNKNOWN -1
-int get_ncores_from_cpuinfo();
+int get_ncores_from_cpuinfo(void);
 uint32_t get_midr_from_cpuinfo(uint32_t core, bool* success);
-char* get_hardware_from_cpuinfo();
+char* get_hardware_from_cpuinfo(void);
-char* get_revision_from_cpuinfo();
+char* get_revision_from_cpuinfo(void);
-bool is_raspberry_pi();
+bool is_raspberry_pi(void);
 
 #endif
 

src/common/args.c

@@ -12,6 +12,8 @@
 #define COLOR_STR_AMD       "amd"
 #define COLOR_STR_IBM       "ibm"
 #define COLOR_STR_ARM       "arm"
+#define COLOR_STR_ROCKCHIP  "rockchip"
+#define COLOR_STR_SIFIVE    "sifive"
 
 static const char *SYTLES_STR_LIST[] = {
   [STYLE_EMPTY]   = NULL,
@@ -71,59 +73,59 @@ const char *args_str[] = {
 
 static struct args_struct args;
 
-STYLE get_style() {
+STYLE get_style(void) {
   return args.style;
 }
 
-struct color** get_colors() {
+struct color** get_colors(void) {
   return args.colors;
 }
 
-bool show_help() {
+bool show_help(void) {
   return args.help_flag;
 }
 
-bool show_version() {
+bool show_version(void) {
   return args.version_flag;
 }
 
-bool show_debug() {
+bool show_debug(void) {
   return args.debug_flag;
 }
 
-bool show_raw() {
+bool show_raw(void) {
   return args.raw_flag;
 }
 
-bool accurate_pp() {
+bool accurate_pp(void) {
   return args.accurate_pp;
 }
 
-bool show_full_cpu_name() {
+bool show_full_cpu_name(void) {
   return args.full_cpu_name_flag;
 }
 
-bool show_logo_long() {
+bool show_logo_long(void) {
   return args.logo_long;
 }
 
-bool show_logo_short() {
+bool show_logo_short(void) {
   return args.logo_short;
 }
 
-bool show_logo_intel_new() {
+bool show_logo_intel_new(void) {
   return args.logo_intel_new;
 }
 
-bool show_logo_intel_old() {
+bool show_logo_intel_old(void) {
   return args.logo_intel_old;
 }
 
-bool verbose_enabled() {
+bool verbose_enabled(void) {
   return args.verbose_flag;
 }
 
-int max_arg_str_length() {
+int max_arg_str_length(void) {
   int max_len = -1;
   int len = sizeof(args_str) / sizeof(args_str[0]);
   for(int i=0; i < len; i++) {
@@ -168,6 +170,8 @@ bool parse_color(char* optarg_str, struct color*** cs) {
   else if(strcmp(optarg_str, COLOR_STR_AMD) == 0) color_to_copy = COLOR_DEFAULT_AMD;
   else if(strcmp(optarg_str, COLOR_STR_IBM) == 0) color_to_copy = COLOR_DEFAULT_IBM;
   else if(strcmp(optarg_str, COLOR_STR_ARM) == 0) color_to_copy = COLOR_DEFAULT_ARM;
+  else if(strcmp(optarg_str, COLOR_STR_ROCKCHIP) == 0) color_to_copy = COLOR_DEFAULT_ROCKCHIP;
+  else if(strcmp(optarg_str, COLOR_STR_SIFIVE) == 0) color_to_copy = COLOR_DEFAULT_SIFIVE;
   else {
     str_to_parse = optarg_str;
     free_ptr = false;
@@ -211,7 +215,7 @@ bool parse_color(char* optarg_str, struct color*** cs) {
   return true;
 }
 
-char* build_short_options() {
+char* build_short_options(void) {
   const char *c = args_chr;
   int len = sizeof(args_chr) / sizeof(args_chr[0]);
   char* str = (char *) emalloc(sizeof(char) * (len*2 + 1));

src/common/args.h

@@ -39,21 +39,21 @@ extern const char *args_str[];
 
 #include "printer.h"
 
-int max_arg_str_length();
+int max_arg_str_length(void);
 bool parse_args(int argc, char* argv[]);
-bool show_help();
+bool show_help(void);
-bool accurate_pp();
+bool accurate_pp(void);
-bool show_full_cpu_name();
+bool show_full_cpu_name(void);
-bool show_logo_long();
+bool show_logo_long(void);
-bool show_logo_short();
+bool show_logo_short(void);
-bool show_logo_intel_new();
+bool show_logo_intel_new(void);
-bool show_logo_intel_old();
+bool show_logo_intel_old(void);
-bool show_raw();
+bool show_raw(void);
-bool show_debug();
+bool show_debug(void);
-bool show_version();
+bool show_version(void);
-bool verbose_enabled();
+bool verbose_enabled(void);
 void free_colors_struct(struct color** cs);
-struct color** get_colors();
+struct color** get_colors(void);
-STYLE get_style();
+STYLE get_style(void);
 
 #endif

src/common/ascii.h

@@ -236,6 +236,76 @@ $C1      #####                 ##.                \
 $C1            ###########.                       \
 $C1                                               "
 
+#define ASCII_ROCKCHIP \
+"$C1                                                          \
+$C1                                              $C2##          \
+$C1   ######                ##            ##                 \
+$C1  ##.  ### ##### #####  ## .## #####  ######. ##   #####  \
+$C1 #######. ##. # #.     #####  ##.    ###  ###  #     .##  \
+$C1##.  ###.  ####. #### ###  .## #### ###  ###   #.#####    \
+$C1                                                ##        \
+$C1                                                          "
+
+#define ASCII_RISCV \
+"$C1                                                               \
+$C1                                ************                   \
+$C1                    %%%%%%%%%    ***********                   \
+$C1                    %%%%%%%%%%   **********                    \
+$C1                    %%%%%%%%%    *********                     \
+$C1                    %           ********                       \
+$C1                    %%      .*********     %                   \
+$C1                    %%%%     *******     %%%                   \
+$C1                    %%%%%%.    ****    %%%%%                   \
+$C1                    %%%%%%%%.        %%%%%%%                   \
+$C1                                                               \
+$C1                                                               \
+$C1 ###########   ##   .#########    #########   .##           ## \
+$C1 ##        ##  ##  ##           ##              ###       ###  \
+$C1 ###########   ##  ##########. ##          ####  .##     ##    \
+$C1 ##     ###    ##           ##. ##                 ### ###     \
+$C1 ##       ###  ##  ##########.   ##########          ###       \
+$C1                                                               "
+
+#define ASCII_SIFIVE \
+"$C1 ############################################## \
+$C1 ###########@@@@@@@@@@@@@@@@@@@@@@@@########### \
+$C1 #########@@@@@@@@@@@@@@@@@@@@@@@@@@@@######### \
+$C1 ########@@@@######################@@@@######## \
+$C1 #######@@@@########################@@@@####### \
+$C1 ######@@@@##########################@@@@###### \
+$C1 #####@@@@#######@@@@@@@@@@@@@@@@@@@@@@@@@##### \
+$C1 ####@@@@#######@@@@@@@@@@@@@@@@@@@@@@@@@@@#### \
+$C1 ###@@@@################################@@@@### \
+$C1 ##@@@@##################################@@@@## \
+$C1 #@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@#########@@@@# \
+$C1 #@@@@@@@@@@@@@@@@@@@@@@@@@@@@@###########@@@@# \
+$C1 ##@@@@@@############@@@@@@############@@@@@@## \
+$C1 ######@@@@@###########@@###########@@@@@###### \
+$C1 #########@@@@@@################@@@@@@######### \
+$C1 #############@@@@@##########@@@@@############# \
+$C1 ################@@@@@@##@@@@@@################ \
+$C1 ####################@@@@@@#################### \
+$C1 ############################################## "
+
+#define ASCII_STARFIVE \
+"$C1                   #             \
+$C1               ##########        \
+$C1          ########   ########    \
+$C1     ########              ####  \
+$C1  #######           ####         \
+$C1 ####                #######     \
+$C1 ####        #####       ####### \
+$C1  #######      ########      .## \
+$C1      ########      ########     \
+$C1 ###      ########.     #######  \
+$C1 #######       #####        #### \
+$C1     ########      #.       #### \
+$C1  #      ####           #######  \
+$C1  #####             #######      \
+$C1    ########   ########          \
+$C1         #########               \
+$C1             #                   "
+
 // --------------------- LONG LOGOS ------------------------- //
 #define ASCII_AMD_L \
 "$C1                                                              \
@@ -320,11 +390,59 @@ $C1 ############ ################## #########   ####   ######### \
 $C1                                                              \
 $C1 ############ ################   #########    ##    ######### "
 
+#define ASCII_SIFIVE_L \
+"$C1 ################################################### \
+$C1 ###########@@@@@@@@@@@@@@@@@@@@@@@@@@@@############ \
+$C1 ##########@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@########### \
+$C1 #########@@@@@#######################@@@@########## \
+$C1 ########@@@@@#########################@@@@######### \
+$C1 #######@@@@@###########################@@@@######## \
+$C1 ######@@@@@########@@@@@@@@@@@@@@@@@@@@@@@@@####### \
+$C1 #####@@@@@########@@@@@@@@@@@@@@@@@@@@@@@@@@@###### \
+$C1 ####@@@@@################################@@@@@##### \
+$C1 ###@@@@@##################################@@@@@#### \
+$C1 ##@@@@@####################################@@@@@### \
+$C1 ##@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@#########@@@@### \
+$C1 ##@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@############@@@@### \
+$C1 ####@@@@@#############@@@@@@@############@@@@@##### \
+$C1 #######@@@@@@############@############@@@@@@####### \
+$C1 ##########@@@@@@###################@@@@@@########## \
+$C1 ##############@@@@@@###########@@@@@@############## \
+$C1 #################@@@@@@#####@@@@@@################# \
+$C1 ####################@@@@@@@@@@@#################### \
+$C1 ########################@@@######################## \
+$C1 ################################################### "
+
+#define ASCII_STARFIVE_L \
+"$C1                          #######                 \
+$C1                     ################.            \
+$C1                ############   ###########        \
+$C1            ############           ##########.    \
+$C1       ############           #         ######    \
+$C1    ###########               #####         ##    \
+$C1   #######.                   ##########          \
+$C1  ######            ###         *###########      \
+$C1  ######            #######.         ##########   \
+$C1   #########        ############         ######   \
+$C1     ###########.        ###########*         #   \
+$C1         ############        ############         \
+$C1   #         ############.       .###########     \
+$C1   ######         ###########         #########   \
+$C1   ##########         .######,            #####   \
+$C1      ############         ##.            #####.  \
+$C1           #########                   ########   \
+$C1    ##         #####               ##########.    \
+$C1    #######        #          ############        \
+$C1    ###########           ###########.            \
+$C1        ###########. ############                 \
+$C1            ################                      \
+$C1                 #######                          "
+
 typedef struct ascii_logo asciiL;
 
-//                        ------------------------------------------------------------------------------------------------------+
+//                        +-----------------------------------------------------------------------------------------------------+
 //                        | LOGO             | W | H | REPLACE | COLORS LOGO (>0 && <10)          | COLORS TEXT (=2)            |
-//                        ------------------------------------------------------------------------------------------------------+
+//                        +-----------------------------------------------------------------------------------------------------+
 asciiL logo_amd         = { ASCII_AMD,         39, 15, false, {C_FG_WHITE, C_FG_GREEN},           {C_FG_WHITE,   C_FG_GREEN}   };
 asciiL logo_intel       = { ASCII_INTEL,       48, 14, false, {C_FG_CYAN},                        {C_FG_CYAN,    C_FG_WHITE}   };
 asciiL logo_intel_new   = { ASCII_INTEL_NEW,   51,  9, false, {C_FG_CYAN},                        {C_FG_CYAN,    C_FG_WHITE}   };
@@ -337,6 +455,10 @@ asciiL logo_arm         = { ASCII_ARM,         42,  5, false, {C_FG_CYAN},
 asciiL logo_ibm         = { ASCII_IBM,         42,  9, false, {C_FG_CYAN, C_FG_WHITE},            {C_FG_CYAN,    C_FG_WHITE}   };
 asciiL logo_apple       = { ASCII_APPLE,       32, 17, false, {C_FG_WHITE},                       {C_FG_CYAN,    C_FG_B_WHITE} };
 asciiL logo_allwinner   = { ASCII_ALLWINNER,   47, 16, false, {C_FG_CYAN},                        {C_FG_B_BLACK, C_FG_B_CYAN } };
+asciiL logo_rockchip    = { ASCII_ROCKCHIP,    58,  8, false, {C_FG_CYAN, C_FG_YELLOW},           {C_FG_CYAN,    C_FG_YELLOW}  };
+asciiL logo_riscv       = { ASCII_RISCV,       63, 18, false, {C_FG_CYAN, C_FG_YELLOW},           {C_FG_CYAN,    C_FG_YELLOW}  };
+asciiL logo_sifive      = { ASCII_SIFIVE,      48, 19, true,  {C_BG_WHITE, C_BG_BLACK},           {C_FG_WHITE,   C_FG_BLUE}    };
+asciiL logo_starfive    = { ASCII_STARFIVE,    33, 17, false, {C_FG_WHITE},                       {C_FG_WHITE,   C_FG_BLUE}    };
 
 // Long variants          | ----------------------------------------------------------------------------------------------------|
 asciiL logo_amd_l       = { ASCII_AMD_L,       62, 19, true,  {C_BG_WHITE, C_BG_GREEN},           {C_FG_WHITE, C_FG_GREEN}     };
@@ -344,6 +466,8 @@ asciiL logo_intel_l     = { ASCII_INTEL_L,     62, 19, true,  {C_BG_CYAN, C_BG_W
 asciiL logo_intel_l_new = { ASCII_INTEL_L_NEW, 57, 14, true,  {C_BG_CYAN, C_BG_WHITE, C_BG_BLUE}, {C_FG_CYAN,  C_FG_WHITE}     };
 asciiL logo_arm_l       = { ASCII_ARM_L,       60,  8, true,  {C_BG_CYAN},                        {C_FG_WHITE, C_FG_CYAN}      };
 asciiL logo_ibm_l       = { ASCII_IBM_L,       62, 13, true,  {C_BG_CYAN, C_FG_WHITE},            {C_FG_CYAN,  C_FG_WHITE}     };
+asciiL logo_starfive_l  = { ASCII_STARFIVE_L,  50, 22, false, {C_FG_WHITE},                       {C_FG_WHITE, C_FG_BLUE}      };
+asciiL logo_sifive_l    = { ASCII_SIFIVE_L,    53, 21, true,  {C_BG_WHITE, C_BG_BLACK},           {C_FG_WHITE, C_FG_CYAN}      };
 asciiL logo_unknown     = { NULL,               0,  0, false, {COLOR_NONE},                       {COLOR_NONE, COLOR_NONE}     };
 
 #endif

src/common/cpu.c

@@ -14,10 +14,10 @@
   #include "../ppc/uarch.h"
 #elif ARCH_ARM
   #include "../arm/uarch.h"
+#elif ARCH_RISCV
+  #include "../riscv/uarch.h"
 #endif
 
-#define UNUSED(x) (void)(x)
-
 #define STRING_YES        "Yes"
 #define STRING_NO         "No"
 #define STRING_NONE       "None"

src/common/cpu.h

@@ -20,6 +20,10 @@ enum {
   CPU_VENDOR_SAMSUNG,
   CPU_VENDOR_MARVELL,
   CPU_VENDOR_PHYTIUM,
+// ARCH_RISCV
+  CPU_VENDOR_RISCV,
+  CPU_VENDOR_SIFIVE,
+  CPU_VENDOR_THEAD,
 // OTHERS
   CPU_VENDOR_UNKNOWN,
   CPU_VENDOR_INVALID
@@ -32,6 +36,8 @@ enum {
   HV_VENDOR_VMWARE,
   HV_VENDOR_XEN,
   HV_VENDOR_PARALLELS,
+  HV_VENDOR_PHYP,
+  HV_VENDOR_BHYVE,
   HV_VENDOR_INVALID
 };
 
@@ -116,6 +122,11 @@ struct features {
 #endif  
 };
 
+struct extensions {
+  char* str;
+  uint64_t mask;
+};
+
 struct cpuInfo {
   VENDOR cpu_vendor;
   struct uarch* arch;
@@ -123,9 +134,16 @@ struct cpuInfo {
   struct frequency* freq;
   struct cache* cach;
   struct topology* topo;
-  struct features* feat;
   int64_t peak_performance;
 
+  // Similar but not exactly equal
+  // to struct features
+#ifdef ARCH_RISCV
+  struct extensions* ext;
+#else
+  struct features* feat;
+#endif
+
 #if defined(ARCH_X86) || defined(ARCH_PPC)
   // CPU name from model
   char* cpu_name;
@@ -149,7 +167,7 @@ struct cpuInfo {
   uint32_t midr;
 #endif
 
-#ifdef ARCH_ARM
+#if defined(ARCH_ARM) || defined(ARCH_RISCV)
   struct system_on_chip* soc;
 #endif
 

src/common/global.c

@@ -20,6 +20,40 @@
 
 #endif
 
+#ifdef ARCH_X86
+  static const char* ARCH_STR = "x86_64 build";
+  #include "../x86/cpuid.h"
+#elif ARCH_PPC
+  static const char* ARCH_STR = "PowerPC build";
+  #include "../ppc/ppc.h"
+#elif ARCH_ARM
+  static const char* ARCH_STR = "ARM build";
+  #include "../arm/midr.h"
+#elif ARCH_RISCV
+  static const char* ARCH_STR = "RISC-V build";
+  #include "../riscv/riscv.h"
+#endif
+
+#ifdef __linux__
+  #ifdef __ANDROID__
+    static const char* OS_STR = "Android";
+  #else
+    static const char* OS_STR = "Linux";
+  #endif
+#elif __FreeBSD__
+  static const char* OS_STR = "FreeBSD";
+#elif _WIN32
+  static const char* OS_STR = "Windows";
+#elif defined __APPLE__ || __MACH__
+  static const char* OS_STR = "macOS";
+#else
+  static const char* OS_STR = "Unknown OS";
+#endif
+
+#ifndef GIT_FULL_VERSION
+  static const char* VERSION = "1.04";
+#endif
+
 enum {
   LOG_LEVEL_NORMAL,
   LOG_LEVEL_VERBOSE
@@ -47,6 +81,8 @@ void printErr(const char *fmt, ...) {
   vsnprintf(buffer,buffer_size, fmt, args);
   va_end(args);
   fprintf(stderr,RED "[ERROR]: "RESET "%s\n",buffer);
+  fprintf(stderr,"[VERSION]: ");
+  print_version(stderr);
 }
 
 void printBug(const char *fmt, ...) {
@@ -57,6 +93,8 @@ void printBug(const char *fmt, ...) {
   vsnprintf(buffer,buffer_size, fmt, args);
   va_end(args);
   fprintf(stderr,RED "[ERROR]: "RESET "%s\n",buffer);
+  fprintf(stderr,"[VERSION]: ");
+  print_version(stderr);
 #if defined(ARCH_X86) || defined(ARCH_PPC)
   fprintf(stderr, "Please, create a new issue with this error message, the output of 'cpufetch' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
 #elif ARCH_ARM
@@ -123,3 +161,10 @@ void* erealloc(void *ptr, size_t size) {
   return newptr;
 }
 
+void print_version(FILE *restrict stream) {
+#ifdef GIT_FULL_VERSION
+  fprintf(stream, "cpufetch %s (%s %s)\n", GIT_FULL_VERSION, OS_STR, ARCH_STR);
+#else
+  fprintf(stream, "cpufetch v%s (%s %s)\n", VERSION, OS_STR, ARCH_STR);
+#endif
+}

src/common/global.h

@@ -1,10 +1,12 @@
 #ifndef __GLOBAL__
 #define __GLOBAL__
 
+#include <stdio.h>
 #include <stdbool.h>
 #include <stddef.h>
 
 #define STRING_UNKNOWN "Unknown"
+#define UNUSED(x) (void)(x)
 
 void set_log_level(bool verbose);
 void printWarn(const char *fmt, ...);
@@ -16,5 +18,6 @@ char *strremove(char *str, const char *sub);
 void* emalloc(size_t size);
 void* ecalloc(size_t nmemb, size_t size);
 void* erealloc(void *ptr, size_t size);
+void print_version(FILE *restrict stream);
 
 #endif

src/common/main.c

@@ -6,35 +6,6 @@
 #include "printer.h"
 #include "global.h"
 
-#ifdef ARCH_X86
-  static const char* ARCH_STR = "x86_64 build";
-  #include "../x86/cpuid.h"
-#elif ARCH_PPC
-  static const char* ARCH_STR = "PowerPC build";
-  #include "../ppc/ppc.h"
-#elif ARCH_ARM
-  static const char* ARCH_STR = "ARM build";
-  #include "../arm/midr.h"
-#endif
-
-#ifdef __linux__
-  #ifdef __ANDROID__
-    static const char* OS_STR = "Android";
-  #else
-    static const char* OS_STR = "Linux";
-  #endif
-#elif __FreeBSD__
-  static const char* OS_STR = "FreeBSD";
-#elif _WIN32
-  static const char* OS_STR = "Windows";
-#elif defined __APPLE__ || __MACH__
-  static const char* OS_STR = "macOS";
-#else
-  static const char* OS_STR = "Unknown OS";
-#endif
-
-static const char* VERSION = "1.03";
-
 void print_help(char *argv[]) {
   const char **t = args_str;
   const char *c = args_chr;
@@ -69,10 +40,13 @@ void print_help(char *argv[]) {
   printf("  -%c, --%s %*s Print cpufetch version and exit\n", c[ARG_VERSION], t[ARG_VERSION], (int) (max_len-strlen(t[ARG_VERSION])), "");
 
   printf("\nCOLORS: \n");
-  printf("  * \"intel\":     Use Intel default color scheme \n");
+  printf("  * \"intel\":     Use Intel color scheme \n");
-  printf("  * \"amd\":       Use AMD default color scheme \n");
+  printf("  * \"intel-new\": Use Intel (new logo) color scheme \n");
-  printf("  * \"ibm\",       Use IBM default color scheme \n");
+  printf("  * \"amd\":       Use AMD color scheme \n");
-  printf("  * \"arm\":       Use ARM default color scheme \n");
+  printf("  * \"ibm\",       Use IBM color scheme \n");
+  printf("  * \"arm\":       Use ARM color scheme \n");
+  printf("  * \"rockchip\":  Use ARM color scheme \n");
+  printf("  * \"sifive\":    Use SiFive color scheme \n");
   printf("  * custom:      If the argument of --color does not match any of the previous strings, a custom scheme can be specified.\n");
   printf("                 5 colors must be given in RGB with the format: R,G,B:R,G,B:...\n");
   printf("                 The first 3 colors are the CPU art color and the next 2 colors are the text colors\n");
@@ -102,12 +76,10 @@ void print_help(char *argv[]) {
   printf("\nNOTE: \n");
   printf("    Peak performance information is NOT accurate. cpufetch computes peak performance using the max\n");
   printf("    frequency of the CPU. However, to compute the peak performance, you need to know the frequency of the\n");
-  printf("    CPU running AVX code. This value is not be fetched by cpufetch since it depends on each specific CPU.\n");
+  printf("    CPU running AVX code. By default, this value is not fetched by cpufetch, but you can use the\n");
-  printf("    To correctly measure peak performance, see: https://github.com/Dr-Noob/peakperf\n");
+  printf("    --accurate-pp option, which will measure the AVX frequency and show a more precise estimation\n");
-}
+  printf("    (this option is only available in x86 architectures).\n");
-
+  printf("    To precisely measure peak performance, see: https://github.com/Dr-Noob/peakperf\n");
-void print_version() {
-  printf("cpufetch v%s (%s %s)\n",VERSION, OS_STR, ARCH_STR);
 }
 
 int main(int argc, char* argv[]) {
@@ -120,7 +92,7 @@ int main(int argc, char* argv[]) {
   }
 
   if(show_version()) {
-    print_version();
+    print_version(stdout);
     return EXIT_SUCCESS;
   }
 
@@ -131,7 +103,7 @@ int main(int argc, char* argv[]) {
     return EXIT_FAILURE;
 
   if(show_debug()) {
-    print_version();
+    print_version(stdout);
     print_debug(cpu);
     return EXIT_SUCCESS;
   }
@@ -139,7 +111,7 @@ int main(int argc, char* argv[]) {
   // TODO: This should be moved to the end of args.c
   if(show_raw()) {
   #ifdef ARCH_X86
-    print_version();
+    print_version(stdout);
     print_raw(cpu);
     return EXIT_SUCCESS;
   #else
@@ -148,8 +120,10 @@ int main(int argc, char* argv[]) {
   #endif
   }
 
-  if(print_cpufetch(cpu, get_style(), get_colors(), show_full_cpu_name()))
+  if(print_cpufetch(cpu, get_style(), get_colors(), show_full_cpu_name())) {
     return EXIT_SUCCESS;
-  else
+  }
+  else {
     return EXIT_FAILURE;
   }
+}

src/common/printer.c

@@ -16,10 +16,15 @@
 #elif ARCH_PPC
   #include "../ppc/uarch.h"
   #include "../ppc/ppc.h"
-#else
+#elif ARCH_ARM
   #include "../arm/uarch.h"
   #include "../arm/midr.h"
   #include "../arm/soc.h"
+  #include "../common/soc.h"
+#elif ARCH_RISCV
+  #include "../riscv/riscv.h"
+  #include "../riscv/uarch.h"
+  #include "../riscv/soc.h"
 #endif
 
 #ifdef _WIN32
@@ -42,7 +47,7 @@
 enum {
 #if defined(ARCH_X86) || defined(ARCH_PPC)
   ATTRIBUTE_NAME,
-#elif ARCH_ARM
+#elif defined(ARCH_ARM) || defined(ARCH_RISCV)
   ATTRIBUTE_SOC,
 #endif
 #if defined(ARCH_X86) || defined(ARCH_ARM)
@@ -62,6 +67,8 @@ enum {
   ATTRIBUTE_ALTIVEC,
 #elif ARCH_ARM
   ATTRIBUTE_FEATURES,
+#elif ARCH_RISCV
+  ATTRIBUTE_EXTENSIONS,
 #endif
   ATTRIBUTE_L1i,
   ATTRIBUTE_L1d,
@@ -75,7 +82,7 @@ static const char* ATTRIBUTE_FIELDS [] = {
   "Name:",
 #elif ARCH_PPC
   "Part Number:",
-#elif ARCH_ARM
+#elif defined(ARCH_ARM) || defined(ARCH_RISCV)
   "SoC:",
 #endif
 #if defined(ARCH_X86) || defined(ARCH_ARM)
@@ -95,6 +102,8 @@ static const char* ATTRIBUTE_FIELDS [] = {
   "Altivec: ",
 #elif defined(ARCH_ARM)
   "Features: ",
+#elif defined(ARCH_RISCV)
+  "Extensions: ",
 #endif
   "L1i Size:",
   "L1d Size:",
@@ -128,6 +137,8 @@ static const char* ATTRIBUTE_FIELDS_SHORT [] = {
   "Altivec: ",
 #elif defined(ARCH_ARM)
   "Features: ",
+#elif defined(ARCH_RISCV)
+  "Extensions: ",
 #endif
   "L1i Size:",
   "L1d Size:",
@@ -303,8 +314,6 @@ bool ascii_fits_screen(int termw, struct ascii_logo logo, int lf) {
 void replace_bgbyfg_color(struct ascii_logo* logo) {
   // Replace background by foreground color
   for(int i=0; i < 3; i++) {
-    if(logo->color_ascii[i] == NULL) break;
-
     if(strcmp(logo->color_ascii[i], C_BG_BLACK) == 0) strcpy(logo->color_ascii[i], C_FG_BLACK);
     else if(strcmp(logo->color_ascii[i], C_BG_RED) == 0) strcpy(logo->color_ascii[i], C_FG_RED);
     else if(strcmp(logo->color_ascii[i], C_BG_GREEN) == 0) strcpy(logo->color_ascii[i], C_FG_GREEN);
@@ -361,9 +370,20 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
     art->art = &logo_apple;
   else if(art->vendor == SOC_VENDOR_ALLWINNER)
     art->art = &logo_allwinner;
+  else if(art->vendor == SOC_VENDOR_ROCKCHIP)
+    art->art = &logo_rockchip;
   else {
     art->art = choose_ascii_art_aux(&logo_arm_l, &logo_arm, term, lf);
   }
+#elif ARCH_RISCV
+  if(art->vendor == SOC_VENDOR_SIFIVE)
+    art->art = choose_ascii_art_aux(&logo_sifive_l, &logo_sifive, term, lf);
+  else if(art->vendor == SOC_VENDOR_STARFIVE)
+    art->art = choose_ascii_art_aux(&logo_starfive_l, &logo_starfive, term, lf);
+  else if(art->vendor == SOC_VENDOR_ALLWINNER)
+    art->art = &logo_allwinner;
+  else
+    art->art = &logo_riscv;
 #endif
 
   // 2. Choose colors
@@ -481,6 +501,7 @@ void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const ch
       attr_value = art->attributes[attr_to_print]->value;
       attr_to_print++;
 
+#ifdef ARCH_X86
       if(attr_type == ATTRIBUTE_L3) {
         add_space = false;
       }
@@ -489,6 +510,7 @@ void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const ch
         add_space = true;
       }
       else {
+#endif
         beg_space = 0;
         space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
         if(hybrid_architecture && add_space) {
@@ -498,7 +520,9 @@ void print_ascii_generic(struct ascii* art, uint32_t la, int32_t termw, const ch
 
         printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
                  "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
+#ifdef ARCH_X86
       }
+#endif
     }
     printOutLine(lbuf, art, termw);
     printf("\n");
@@ -657,6 +681,9 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     setAttribute(art, ATTRIBUTE_NAME, cpu_name);
   }
   setAttribute(art, ATTRIBUTE_UARCH, uarch);
+  if(cpu->hv->present) {
+    setAttribute(art, ATTRIBUTE_HYPERVISOR, cpu->hv->hv_name);
+  }
   setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
   setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
   uint32_t socket_num = get_nsockets(cpu->topo);
@@ -690,7 +717,7 @@ bool print_cpufetch_ppc(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     longest_attribute = longest_attribute_length(art, attribute_fields);
   }
 
-  print_ascii_generic(art, longest_attribute, term->w, attribute_fields);
+  print_ascii_generic(art, longest_attribute, term->w, attribute_fields, false);
 
   return true;
 }
@@ -823,15 +850,6 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     char* uarch = get_str_uarch(cpu);
     char* max_frequency = get_str_freq(cpu->freq);
     char* n_cores = get_str_topology(cpu, cpu->topo, false);
-    /*
-     * char* l1i = get_str_l1i(cpu->cach);
-     * char* l1d = get_str_l1d(cpu->cach);
-     * char* l2 = get_str_l2(cpu->cach);
-     * char* l3 = get_str_l3(cpu->cach);
-     * Do not setAttribute for caches.
-     * Cache functionality may be implemented
-     * in the future
-    */
 
     setAttribute(art, ATTRIBUTE_UARCH, uarch);
     setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
@@ -846,17 +864,8 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
       char* uarch = get_str_uarch(ptr);
       char* max_frequency = get_str_freq(ptr->freq);
       char* n_cores = get_str_topology(ptr, ptr->topo, false);
-      /*
-       * char* l1i = get_str_l1i(cpu->cach);
-       * char* l1d = get_str_l1d(cpu->cach);
-       * char* l2 = get_str_l2(cpu->cach);
-       * char* l3 = get_str_l3(cpu->cach);
-       * Do not setAttribute for caches.
-       * Cache functionality may be implemented
-       * in the future
-       */
-
       char* cpu_num = emalloc(sizeof(char) * 9);
+
       sprintf(cpu_num, "CPU %d:", i+1);
       setAttribute(art, ATTRIBUTE_CPU_NUM, cpu_num);
       setAttribute(art, ATTRIBUTE_UARCH, uarch);
@@ -907,7 +916,142 @@ bool print_cpufetch_arm(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
 }
 #endif
 
-struct terminal* get_terminal_size() {
+#ifdef ARCH_RISCV
+// https://stackoverflow.com/a/2709523
+uint64_t number_of_bits(uint64_t i) {
+  i = i - ((i >> 1) & 0x5555555555555555);
+  i = (i & 0x3333333333333333) + ((i >> 2) & 0x3333333333333333);
+  return (((i + (i >> 4)) & 0xF0F0F0F0F0F0F0F) * 0x101010101010101) >> 56;
+}
+
+void print_ascii_riscv(struct ascii* art, uint32_t la, int32_t termw, const char** attribute_fields, uint64_t extensions_mask) {
+  struct ascii_logo* logo = art->art;
+  int attr_to_print = 0;
+  int attr_type;
+  char* attr_value;
+  int32_t beg_space;
+  int32_t space_right;
+  int32_t ext_list_size = sizeof(extension_list)/sizeof(extension_list[0]);
+  int32_t ext_num = 0;
+  int32_t ext_to_print = 0;
+  int32_t num_extensions = number_of_bits(extensions_mask);
+  int32_t space_up = ((int)logo->height - (int)(art->n_attributes_set + num_extensions))/2;
+  int32_t space_down = (int)logo->height - (int)(art->n_attributes_set + num_extensions) - (int)space_up;
+  uint32_t logo_pos = 0;
+  int32_t iters = max(logo->height, art->n_attributes_set + num_extensions);
+
+  struct line_buffer* lbuf = emalloc(sizeof(struct line_buffer));
+  lbuf->buf = emalloc(sizeof(char) * LINE_BUFFER_SIZE);
+  lbuf->pos = 0;
+  lbuf->chars = 0;
+
+  printf("\n");
+  for(int32_t n=0; n < iters; n++) {
+    // 1. Print logo
+    if(space_up > 0 || (space_up + n >= 0 && space_up + n < (int)logo->height)) {
+      for(uint32_t i=0; i < logo->width; i++) {
+        if(logo->art[logo_pos] == '$') {
+          if(logo->replace_blocks) logo_pos += 3;
+          else parse_print_color(art, lbuf, &logo_pos);
+        }
+        if(logo->replace_blocks && logo->art[logo_pos] != ' ') {
+          if(logo->art[logo_pos] == '#') printOut(lbuf, 1, "%s%c%s", logo->color_ascii[0], ' ', art->reset);
+          else if(logo->art[logo_pos] == '@') printOut(lbuf, 1, "%s%c%s", logo->color_ascii[1], ' ', art->reset);
+          else if(logo->art[logo_pos] == '%') printOut(lbuf, 1, "%s%c%s", logo->color_ascii[2], ' ', art->reset);
+          else printOut(lbuf, 1, "%c", logo->art[logo_pos]);
+        }
+        else
+          printOut(lbuf, 1, "%c", logo->art[logo_pos]);
+
+        logo_pos++;
+      }
+      printOut(lbuf, 0, "%s", art->reset);
+    }
+    else {
+      // If logo should not be printed, fill with spaces
+      printOut(lbuf, logo->width, "%*c", logo->width, ' ');
+    }
+
+    // 2. Print text
+    if(space_up < 0 || (n > space_up-1 && n < (int)logo->height - space_down)) {
+      attr_type = art->attributes[attr_to_print]->type;
+      attr_value = art->attributes[attr_to_print]->value;
+
+      // Print extension
+      if(attr_to_print > 0 && art->attributes[attr_to_print-1]->type == ATTRIBUTE_EXTENSIONS && ext_num != num_extensions) {
+        // Search for the extension to print
+        while(ext_to_print < ext_list_size && !((extensions_mask >> extension_list[ext_to_print].id) & 1U)) ext_to_print++;
+        if(ext_to_print == ext_list_size) {
+          printBug("print_ascii_riscv: Unable to find the extension to print");
+        }
+
+        printOut(lbuf, 3 + strlen(extension_list[ext_to_print].str), "%s - %s%s", logo->color_text[0], extension_list[ext_to_print].str, art->reset);
+        ext_num++;
+        ext_to_print++;
+      }
+      else {
+        attr_to_print++;
+        beg_space = 0;
+        space_right = 2 + 1 + (la - strlen(attribute_fields[attr_type]));
+
+        printOut(lbuf, beg_space + strlen(attribute_fields[attr_type]) + space_right + strlen(attr_value),
+                 "%*s%s%s%s%*s%s%s%s", beg_space, "", logo->color_text[0], attribute_fields[attr_type], art->reset, space_right, "", logo->color_text[1], attr_value, art->reset);
+      }
+    }
+    printOutLine(lbuf, art, termw);
+    printf("\n");
+  }
+  printf("\n");
+
+  free(lbuf->buf);
+  free(lbuf);
+}
+
+bool print_cpufetch_riscv(struct cpuInfo* cpu, STYLE s, struct color** cs, struct terminal* term) {
+  struct ascii* art = set_ascii(get_soc_vendor(cpu->soc), s);
+  if(art == NULL)
+    return false;
+
+  // Step 1. Retrieve attributes
+  char* uarch = get_str_uarch(cpu);
+  char* manufacturing_process = get_str_process(cpu->soc);
+  char* soc_name = get_soc_name(cpu->soc);
+  char* extensions = get_str_extensions(cpu);
+  char* max_frequency = get_str_freq(cpu->freq);
+  char* n_cores = get_str_topology(cpu, cpu->topo);
+  char* pp = get_str_peak_performance(cpu->peak_performance);
+
+  // Step 2. Set attributes
+  setAttribute(art, ATTRIBUTE_SOC, soc_name);
+  setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
+  setAttribute(art, ATTRIBUTE_UARCH, uarch);
+  setAttribute(art, ATTRIBUTE_NCORES, n_cores);
+  setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
+  if(extensions != NULL) {
+    setAttribute(art, ATTRIBUTE_EXTENSIONS, extensions);
+  }
+  setAttribute(art, ATTRIBUTE_PEAK, pp);
+
+  // Step 3. Print output
+  const char** attribute_fields = ATTRIBUTE_FIELDS;
+  uint32_t longest_attribute = longest_attribute_length(art, attribute_fields);
+  uint32_t longest_field = longest_field_length(art, longest_attribute);
+  choose_ascii_art(art, cs, term, longest_field);
+
+  if(!ascii_fits_screen(term->w, *art->art, longest_field)) {
+    // Despite of choosing the smallest logo, the output does not fit
+    // Choose the shorter field names and recalculate the longest attr
+    attribute_fields = ATTRIBUTE_FIELDS_SHORT;
+    longest_attribute = longest_attribute_length(art, attribute_fields);
+  }
+
+  print_ascii_riscv(art, longest_attribute, term->w, attribute_fields, cpu->ext->mask);
+
+  return true;
+}
+#endif
+
+struct terminal* get_terminal_size(void) {
   struct terminal* term = emalloc(sizeof(struct terminal));
 
 #ifdef _WIN32
@@ -944,5 +1088,7 @@ bool print_cpufetch(struct cpuInfo* cpu, STYLE s, struct color** cs, bool show_f
   return print_cpufetch_ppc(cpu, s, cs, term, show_full_cpu_name);
 #elif ARCH_ARM
   return print_cpufetch_arm(cpu, s, cs, term);
+#elif ARCH_RISCV
+  return print_cpufetch_riscv(cpu, s, cs, term);
 #endif
 }

src/common/printer.h

@@ -11,6 +11,8 @@ typedef int STYLE;
   #include "../ppc/ppc.h"
 #elif ARCH_ARM
   #include "../arm/midr.h"
+#elif ARCH_RISCV
+  #include "../riscv/riscv.h"
 #endif
 
 //                              +-----------------------------------+-----------------------+
@@ -21,6 +23,8 @@ typedef int STYLE;
 #define COLOR_DEFAULT_AMD       "250,250,250:000,154,102:000,000,000:250,250,250:000,154,102"
 #define COLOR_DEFAULT_IBM       "092,119,172:092,119,172:000,000,000:240,240,240:092,119,172"
 #define COLOR_DEFAULT_ARM       "000,145,189:000,145,189:000,000,000:240,240,240:000,145,189"
+#define COLOR_DEFAULT_ROCKCHIP  "114,159,207:229,195,000:000,000,000:240,240,240:114,159,207"
+#define COLOR_DEFAULT_SIFIVE    "255,255,255:000,000,000:000,000,000:255,255,255:000,000,000"
 
 #ifdef ARCH_X86
 void print_levels(struct cpuInfo* cpu);

src/common/soc.c

@@ -0,0 +1,88 @@
+#include "soc.h"
+#ifdef ARCH_ARM
+  #include "../arm/socs.h"
+#elif ARCH_RISCV
+  #include "../riscv/socs.h"
+#endif
+#include "udev.h"
+#include "../common/global.h"
+
+#include <string.h>
+
+static char* soc_trademark_string[] = {
+  // ARM
+  [SOC_VENDOR_SNAPDRAGON] = "Snapdragon ",
+  [SOC_VENDOR_MEDIATEK]   = "MediaTek ",
+  [SOC_VENDOR_EXYNOS]     = "Exynos ",
+  [SOC_VENDOR_KIRIN]      = "Kirin ",
+  [SOC_VENDOR_BROADCOM]   = "Broadcom BCM",
+  [SOC_VENDOR_APPLE]      = "Apple ",
+  [SOC_VENDOR_ROCKCHIP]   = "Rockchip ",
+  // RISC-V
+  [SOC_VENDOR_SIFIVE]     = "SiFive ",
+  [SOC_VENDOR_STARFIVE]   = "StarFive ",
+  // ARM & RISC-V
+  [SOC_VENDOR_ALLWINNER]  = "Allwinner "
+};
+
+VENDOR get_soc_vendor(struct system_on_chip* soc) {
+  return soc->soc_vendor;
+}
+
+char* get_str_process(struct system_on_chip* soc) {
+  char* str;
+
+  if(soc->process == UNKNOWN) {
+    str = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
+    snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+  }
+  else {
+    str = emalloc(sizeof(char) * 5);
+    memset(str, 0, sizeof(char) * 5);
+    snprintf(str, 5, "%dnm", soc->process);
+  }
+  return str;
+}
+
+char* get_soc_name(struct system_on_chip* soc) {
+  if(soc->soc_model == SOC_MODEL_UNKNOWN)
+    return soc->raw_name;
+  return soc->soc_name;
+}
+
+void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process) {
+  soc->soc_model = soc_model;
+  soc->soc_vendor = get_soc_vendor_from_soc(soc_model);
+  soc->process = process;
+  if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+    printBug("fill_soc: soc->soc_vendor == SOC_VENDOR_UNKOWN");
+    // If we fall here there is a bug in socs.h
+    // Reset everything to avoid segfault
+    soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+    soc->soc_model = SOC_MODEL_UNKNOWN;
+    soc->process = UNKNOWN;
+    soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
+    snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+  }
+  else {
+    soc->process = process;
+    int len = strlen(soc_name) + strlen(soc_trademark_string[soc->soc_vendor]) + 1;
+    soc->soc_name = emalloc(sizeof(char) * len);
+    memset(soc->soc_name, 0, sizeof(char) * len);
+    sprintf(soc->soc_name, "%s%s", soc_trademark_string[soc->soc_vendor], soc_name);
+  }
+}
+
+bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
+  int len1 = strlen(raw_name);
+  int len2 = strlen(expected_name);
+  int len = min(len1, len2);
+
+  if(strncmp(raw_name, expected_name, len) != 0) {
+    return false;
+  }
+  else {
+    fill_soc(soc, soc_name, soc_model, process);
+    return true;
+  }
+}

src/common/soc.h

@@ -0,0 +1,52 @@
+#ifndef __SOC__
+#define __SOC__
+
+// NOTE:
+// soc.c/soc.h are used by
+// ARM and RISC-V backends
+
+#include "../common/cpu.h"
+#include <stdint.h>
+
+#define UNKNOWN -1
+
+typedef int32_t SOC;
+
+enum {
+  SOC_VENDOR_UNKNOWN,
+  // ARM
+  SOC_VENDOR_SNAPDRAGON,
+  SOC_VENDOR_MEDIATEK,
+  SOC_VENDOR_EXYNOS,
+  SOC_VENDOR_KIRIN,
+  SOC_VENDOR_BROADCOM,
+  SOC_VENDOR_APPLE,
+  SOC_VENDOR_ROCKCHIP,
+  // RISC-V
+  SOC_VENDOR_SIFIVE,
+  SOC_VENDOR_STARFIVE,
+  // ARM & RISC-V
+  SOC_VENDOR_ALLWINNER
+};
+
+struct system_on_chip {
+  SOC soc_model;
+  VENDOR soc_vendor;
+  int32_t process;
+  char* soc_name;
+  char* raw_name;
+};
+
+struct system_on_chip* get_soc(void);
+char* get_soc_name(struct system_on_chip* soc);
+VENDOR get_soc_vendor(struct system_on_chip* soc);
+bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process);
+char* get_str_process(struct system_on_chip* soc);
+void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process);
+
+#define SOC_START if (false) {}
+#define SOC_EQ(raw_name, expected_name, soc_name, soc_model, soc, process) \
+   else if (match_soc(soc, raw_name, expected_name, soc_name, soc_model, process)) return true;
+#define SOC_END else { return false; }
+
+#endif

src/common/udev.c

@@ -3,7 +3,7 @@
 #include "cpu.h"
 
 // https://www.kernel.org/doc/html/latest/core-api/cpu_hotplug.html
-int get_ncores_from_cpuinfo() {
+int get_ncores_from_cpuinfo(void) {
   // Examples:
   // 0-271
   // 0-7
@@ -129,6 +129,27 @@ long get_cache_size_from_file(char* path) {
   return ret * 1024;
 }
 
+char* get_field_from_cpuinfo(char* CPUINFO_FIELD) {
+  int filelen;
+  char* buf;
+  if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
+    printWarn("read_file: %s: %s:\n", _PATH_CPUINFO, strerror(errno));
+    return NULL;
+  }
+
+  char* tmp1 = strstr(buf, CPUINFO_FIELD);
+  if(tmp1 == NULL) return NULL;
+  tmp1 = tmp1 + strlen(CPUINFO_FIELD);
+  char* tmp2 = strstr(tmp1, "\n");
+
+  int strlen = (1 + (tmp2-tmp1));
+  char* hardware = emalloc(sizeof(char) * strlen);
+  memset(hardware, 0, sizeof(char) * strlen);
+  strncpy(hardware, tmp1, tmp2-tmp1);
+
+  return hardware;
+}
+
 long get_max_freq_from_file(uint32_t core) {
   char path[_PATH_FREQUENCY_MAX_LEN];
   sprintf(path, "%s%s/cpu%d%s%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_FREQUENCY, _PATH_FREQUENCY_MAX);
@@ -178,7 +199,13 @@ bool maps_equal(uint32_t* map1, uint32_t* map2, int n) {
   return true;
 }
 
-int get_num_caches_from_files(char** paths, int num_paths) {
+// Generic function to count the number of distinct
+// elements in the list of files passed in char** paths.
+// An element can be potentially anything.
+// We use this function to count:
+// - The number of caches
+// - The number of sockets
+int get_num_elements_from_files(char** paths, int num_paths) {
   int filelen;
   char* buf;
   char* tmpbuf;
@@ -193,10 +220,10 @@ int get_num_caches_from_files(char** paths, int num_paths) {
     num_bitmasks += (buf[i] == ',');
   }
 
-  // 2. Read cpu_shared_map from every core
+  // 2. Read map from every core
-  uint32_t** shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
+  uint32_t** maps = emalloc(sizeof(uint32_t *) * num_paths);
   for(int i=0; i < num_paths; i++) {
-    shared_maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
+    maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
 
     if((buf = read_file(paths[i], &filelen)) == NULL) {
       printWarn("Could not open '%s'", paths[i]);
@@ -206,6 +233,7 @@ int get_num_caches_from_files(char** paths, int num_paths) {
     for(int j=0; j < num_bitmasks; j++) {
       char* end;
       tmpbuf = emalloc(sizeof(char) * (strlen(buf) + 1));
+      memset(tmpbuf, 0, sizeof(char) * (strlen(buf) + 1));
       char* commaend = strstr(buf, ",");
       if(commaend == NULL) {
         strcpy(tmpbuf, buf);
@@ -221,35 +249,43 @@ int get_num_caches_from_files(char** paths, int num_paths) {
         return -1;
       }
 
-      shared_maps[i][j] = (uint32_t) ret;
+      maps[i][j] = (uint32_t) ret;
       buf = commaend + 1;
       free(tmpbuf);
     }
   }
 
-  // 2. Count number of different masks; this is the number of caches
+  // 2. Count number of different masks; this is the number of elements
-  int num_caches = 0;
+  int num_elements = 0;
   bool found = false;
-  uint32_t** unique_shared_maps = emalloc(sizeof(uint32_t *) * num_paths);
+  uint32_t** unique_maps = emalloc(sizeof(uint32_t *) * num_paths);
   for(int i=0; i < num_paths; i++) {
-    unique_shared_maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
+    unique_maps[i] = emalloc(sizeof(uint32_t) * num_bitmasks);
     for(int j=0; j < num_bitmasks; j++) {
-      unique_shared_maps[i][j] = 0;
+      unique_maps[i][j] = 0;
     }
   }
 
   for(int i=0; i < num_paths; i++) {
     for(int j=0; j < num_paths && !found; j++) {
-      if(maps_equal(shared_maps[i], unique_shared_maps[j], num_bitmasks)) found = true;
+      if(maps_equal(maps[i], unique_maps[j], num_bitmasks)) found = true;
     }
     if(!found) {
-      add_shared_map(shared_maps, i, unique_shared_maps, num_caches, num_bitmasks);
+      add_shared_map(maps, i, unique_maps, num_elements, num_bitmasks);
-      num_caches++;
+      num_elements++;
     }
     found = false;
   }
 
-  return num_caches;
+  return num_elements;
+}
+
+int get_num_caches_from_files(char** paths, int num_paths) {
+  return get_num_elements_from_files(paths, num_paths);
+}
+
+int get_num_sockets_from_files(char** paths, int num_paths) {
+  return get_num_elements_from_files(paths, num_paths);
 }
 
 int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level) {
@@ -278,3 +314,38 @@ int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level) {
 
   return ret;
 }
+
+int get_num_sockets_package_cpus(struct topology* topo) {
+  // Get number of sockets using
+  // /sys/devices/system/cpu/cpu*/topology/package_cpus
+
+  char** paths = emalloc(sizeof(char *) * topo->total_cores);
+
+  for(int i=0; i < topo->total_cores; i++) {
+    paths[i] = emalloc(sizeof(char) * _PATH_PACKAGE_MAX_LEN);
+    sprintf(paths[i], "%s%s/cpu%d%s",  _PATH_SYS_SYSTEM, _PATH_SYS_CPU, i, _PATH_TOPO_PACKAGE_CPUS);
+  }
+
+  int ret = get_num_sockets_from_files(paths, topo->total_cores);
+
+  for(int i=0; i < topo->total_cores; i++)
+    free(paths[i]);
+  free(paths);
+
+  return ret;
+}
+
+// Inspired in is_devtree_compatible from lscpu
+bool is_devtree_compatible(char* str) {
+  int filelen;
+  char* buf;
+  if((buf = read_file("/proc/device-tree/compatible", &filelen)) == NULL) {
+    return false;
+  }
+
+  char* tmp;
+  if((tmp = strstr(buf, str)) == NULL) {
+    return false;
+  }
+  return true;
+}

src/common/udev.h

@@ -12,6 +12,7 @@
 
 #include "cpu.h"
 
+#define _PATH_CPUINFO           "/proc/cpuinfo"
 #define _PATH_SYS_SYSTEM        "/sys/devices/system"
 #define _PATH_SYS_CPU           "/cpu"
 #define _PATH_FREQUENCY         "/cpufreq"
@@ -24,9 +25,11 @@
 #define _PATH_CACHE_SIZE        "/size"
 #define _PATH_CACHE_SHARED_MAP  "/shared_cpu_map"
 #define _PATH_CPUS_PRESENT      _PATH_SYS_SYSTEM _PATH_SYS_CPU "/present"
+#define _PATH_TOPO_PACKAGE_CPUS "/topology/package_cpus"
 
 #define _PATH_FREQUENCY_MAX_LEN 100
 #define _PATH_CACHE_MAX_LEN     200
+#define _PATH_PACKAGE_MAX_LEN   200
 
 char* read_file(char* path, int* len);
 long get_max_freq_from_file(uint32_t core);
@@ -36,6 +39,9 @@ long get_l1d_cache_size(uint32_t core);
 long get_l2_cache_size(uint32_t core);
 long get_l3_cache_size(uint32_t core);
 int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level);
-int get_ncores_from_cpuinfo();
+int get_num_sockets_package_cpus(struct topology* topo);
+int get_ncores_from_cpuinfo(void);
+char* get_field_from_cpuinfo(char* CPUINFO_FIELD);
+bool is_devtree_compatible(char* str);
 
 #endif

src/ppc/ppc.c

@@ -11,6 +11,18 @@
 #include "../common/udev.h"
 #include "../common/global.h"
 
+static char *hv_vendors_name[] = {
+  [HV_VENDOR_KVM]       = "KVM",
+  [HV_VENDOR_QEMU]      = "QEMU",
+  [HV_VENDOR_HYPERV]    = "Microsoft Hyper-V",
+  [HV_VENDOR_VMWARE]    = "VMware",
+  [HV_VENDOR_XEN]       = "Xen",
+  [HV_VENDOR_PARALLELS] = "Parallels",
+  [HV_VENDOR_PHYP]      = "pHyp",
+  [HV_VENDOR_BHYVE]     = "bhyve",
+  [HV_VENDOR_INVALID]   = STRING_UNKNOWN
+};
+
 struct cache* get_cache_info(struct cpuInfo* cpu) {
   struct cache* cach = emalloc(sizeof(struct cache));
   init_cache_struct(cach);
@@ -63,12 +75,17 @@ struct topology* get_topology_info(struct cache* cach) {
     printWarn("fill_core_ids_from_sys failed, output may be incomplete/invalid");
     for(int i=0; i < topo->total_cores; i++) core_ids[i] = 0;
   }
+
   if(!fill_package_ids_from_sys(package_ids, topo->total_cores)) {
     printWarn("fill_package_ids_from_sys failed, output may be incomplete/invalid");
     for(int i=0; i < topo->total_cores; i++) package_ids[i] = 0;
+    // fill_package_ids_from_sys failed, use a
+    // more sophisticated wat to find the number of sockets
+    topo->sockets = get_num_sockets_package_cpus(topo);
   }
-
+  else {
-  // 2. Socket detection
+    // fill_package_ids_from_sys succeeded, use the
+    // traditional socket detection algorithm
     int *package_ids_count = emalloc(sizeof(int) * topo->total_cores);
     for(int i=0; i < topo->total_cores; i++) {
       package_ids_count[i] = 0;
@@ -81,6 +98,8 @@ struct topology* get_topology_info(struct cache* cach) {
         topo->sockets++;
       }
     }
+    free(package_ids_count);
+  }
 
   // 3. Physical cores detection
   int *core_ids_unified = emalloc(sizeof(int) * topo->total_cores);
@@ -105,13 +124,12 @@ struct topology* get_topology_info(struct cache* cach) {
 
   free(core_ids);
   free(package_ids);
-  free(package_ids_count);
   free(core_ids_unified);
 
   return topo;
 }
 
-static inline uint32_t mfpvr() {
+static inline uint32_t mfpvr(void) {
     uint32_t pvr;
 
     asm ("mfpvr %0"
@@ -123,12 +141,18 @@ struct uarch* get_cpu_uarch(struct cpuInfo* cpu) {
   return get_uarch_from_pvr(cpu->pvr);
 }
 
-struct frequency* get_frequency_info() {
+struct frequency* get_frequency_info(void) {
   struct frequency* freq = emalloc(sizeof(struct frequency));
 
   freq->max = get_max_freq_from_file(0);
   freq->base = get_min_freq_from_file(0);
 
+  if(freq->max == UNKNOWN_DATA) {
+    // If we are unable to find it in the
+    // standard path, try /proc/cpuinfo
+    freq->max = get_frequency_from_cpuinfo();
+  }
+
   return freq;
 }
 
@@ -158,7 +182,29 @@ int64_t get_peak_performance(struct cpuInfo* cpu, struct topology* topo, int64_t
   return flops;
 }
 
-struct cpuInfo* get_cpu_info() {
+struct hypervisor* get_hp_info(void) {
+  struct hypervisor* hv = emalloc(sizeof(struct hypervisor));
+  hv->present = false;
+
+  // Weird heuristic found in lscpu:
+  // https://github.com/util-linux/util-linux/blob/master/sys-utils/lscpu-virt.c
+  if(access("/proc" _PATH_DT_IBM_PARTIT_NAME, F_OK) == 0 &&
+     access("/proc" _PATH_DT_HMC_MANAGED, F_OK) == 0 &&
+     access("/proc" _PATH_DT_QEMU_WIDTH, F_OK) != 0) {
+    hv->present = true;
+    hv->hv_vendor = HV_VENDOR_PHYP;
+  }
+  else if(is_devtree_compatible("qemu,pseries")) {
+    hv->present = true;
+    hv->hv_vendor = HV_VENDOR_QEMU;
+  }
+
+  hv->hv_name = hv_vendors_name[hv->hv_vendor];
+
+  return hv;
+}
+
+struct cpuInfo* get_cpu_info(void) {
   struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
   struct features* feat = emalloc(sizeof(struct features));
   cpu->feat = feat;
@@ -172,8 +218,11 @@ struct cpuInfo* get_cpu_info() {
   char* path = emalloc(sizeof(char) * (strlen(_PATH_DT) + strlen(_PATH_DT_PART) + 1));
   sprintf(path, "%s%s", _PATH_DT, _PATH_DT_PART);
 
-  cpu->cpu_name = read_file(path, &len);
+  if((cpu->cpu_name = read_file(path, &len)) == NULL) {
+    printWarn("Could not open '%s'", path);
+  }
   cpu->pvr = mfpvr();
+  cpu->hv = get_hp_info();
   cpu->arch = get_cpu_uarch(cpu);
   cpu->freq = get_frequency_info();
   cpu->topo = get_topology_info(cpu->cach);

src/ppc/ppc.h

@@ -3,7 +3,7 @@
 
 #include "../common/cpu.h"
 
-struct cpuInfo* get_cpu_info();
+struct cpuInfo* get_cpu_info(void);
 char* get_str_altivec(struct cpuInfo* cpu);
 char* get_str_topology(struct topology* topo, bool dual_socket);
 void print_debug(struct cpuInfo* cpu);

src/ppc/uarch.c

@@ -3,7 +3,6 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include <sys/auxv.h>
 #include <errno.h>
 
 #include "uarch.h"
@@ -36,6 +35,7 @@ enum {
   UARCH_POWER7,
   UARCH_POWER7PLUS,
   UARCH_POWER8,
+  UARCH_POWER8_DD21,
   UARCH_POWER9,
   UARCH_POWER9_DD20,
   UARCH_POWER9_DD21,
@@ -85,6 +85,7 @@ void fill_uarch(struct uarch* arch, MICROARCH u) {
   FILL_UARCH(arch->uarch, UARCH_POWER7,      "POWER7",         45)
   FILL_UARCH(arch->uarch, UARCH_POWER7PLUS,  "POWER7+",        32)
   FILL_UARCH(arch->uarch, UARCH_POWER8,      "POWER8",         22)
+  FILL_UARCH(arch->uarch, UARCH_POWER8_DD21, "POWER8 (DD2.1)", 22)
   FILL_UARCH(arch->uarch, UARCH_POWER9,      "POWER9",         14)
   FILL_UARCH(arch->uarch, UARCH_POWER9_DD20, "POWER9 (DD2.0)", 14)
   FILL_UARCH(arch->uarch, UARCH_POWER9_DD21, "POWER9 (DD2.1)", 14)
@@ -101,7 +102,19 @@ void fill_uarch(struct uarch* arch, MICROARCH u) {
 }
 
 /*
- * PVR masks/values from arch/powerpc/kernel/cputable.c (Linux kernel)
+ * PVR masks/values from Linux kernel:
+ * - arch/powerpc/kernel/cputable.c            (kernel <= 6.0)
+ * - arch/powerpc/kernel/cpu_specs_book3s_64.h (kernel >= 6.1)
+ *
+ * In the kernel, there is a POWER8E identifier. In
+ * https://wiki.raptorcs.com/wiki/POWER8E it says it is
+ * actually DD2.1, while other POWER8 should be DD2.0.
+ * The last assumption does not seem to be correct according
+ * to https://openbenchmarking.org/s/POWER8NVL, which shows a
+ * POWER8NVL where kernel says it is DD1.0. We implement this
+ * to show only the uarch, not the revision, since it seems a bit
+ * redundant?
+ *
  * This list may be incorrect, incomplete or overly simplified,
  * specially in the case of 32 bit entries
  */
@@ -126,7 +139,7 @@ struct uarch* get_uarch_from_pvr(uint32_t pvr) {
   CHECK_UARCH(arch, pvr, 0xffffffff, 0x0f000006, UARCH_POWER10)
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x003f0000, UARCH_POWER7)
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x004A0000, UARCH_POWER7PLUS)
-  CHECK_UARCH(arch, pvr, 0xffff0000, 0x004b0000, UARCH_POWER8)
+  CHECK_UARCH(arch, pvr, 0xffff0000, 0x004b0000, UARCH_POWER8_DD21)
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x004c0000, UARCH_POWER8)
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x004d0000, UARCH_POWER8)
   CHECK_UARCH(arch, pvr, 0xffffefff, 0x004e0200, UARCH_POWER9_DD20)
@@ -235,6 +248,7 @@ bool has_altivec(struct uarch* arch) {
     case UARCH_POWER7:
     case UARCH_POWER7PLUS:
     case UARCH_POWER8:
+    case UARCH_POWER8_DD21:
     case UARCH_POWER9:
     case UARCH_POWER9_DD20:
     case UARCH_POWER9_DD21:

src/ppc/udev.c

@@ -1,16 +1,19 @@
 #include <errno.h>
 
+#include "../common/udev.h"
 #include "../common/global.h"
 #include "udev.h"
 
 #define _PATH_TOPO_CORE_ID         "topology/core_id"
 #define _PATH_TOPO_PACKAGE_ID      "topology/physical_package_id"
+#define CPUINFO_FREQUENCY_STR      "clock\t\t: "
 
 bool fill_array_from_sys(int *core_ids, int total_cores, char* SYS_PATH) {
   int filelen;
   char* buf;
   char* end;
   char path[128];
+  memset(path, 0, 128);
 
   for(int i=0; i < total_cores; i++) {
     sprintf(path, "%s%s/cpu%d/%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, i, SYS_PATH);
@@ -36,5 +39,52 @@ bool fill_core_ids_from_sys(int *core_ids, int total_cores) {
 }
 
 bool fill_package_ids_from_sys(int* package_ids, int total_cores) {
-  return fill_array_from_sys(package_ids, total_cores, _PATH_TOPO_PACKAGE_ID);
+  bool status = fill_array_from_sys(package_ids, total_cores, _PATH_TOPO_PACKAGE_ID);
+  if(status) {
+    // fill_array_from_sys completed successfully, but we
+    // must to check the integrity of the package_ids array
+    for(int i=0; i < total_cores; i++) {
+      if(package_ids[i] == -1) {
+        printWarn("fill_package_ids_from_sys: package_ids[%d] = -1", i);
+        return false;
+      }
+      else if(package_ids[i] >= total_cores || package_ids[i] < 0) {
+        printBug("fill_package_ids_from_sys: package_ids[%d] = %d", i, package_ids[i]);
+        return false;
+      }
+    }
+
+    return true;
+  }
+  return false;
+}
+
+long get_frequency_from_cpuinfo(void) {
+  char* freq_str = get_field_from_cpuinfo(CPUINFO_FREQUENCY_STR);
+  if(freq_str == NULL) {
+    return UNKNOWN_DATA;
+  }
+  else {
+    // freq_str should be in the form XXXX.YYYYYYMHz
+    char* dot = strstr(freq_str, ".");
+    freq_str[dot-freq_str] = '\0';
+
+    char* end;
+    errno = 0;
+    long ret = strtol(freq_str, &end, 10);
+    if(errno != 0) {
+      printBug("strtol: %s", strerror(errno));
+      free(freq_str);
+      return UNKNOWN_DATA;
+    }
+
+    // We consider it an error if frequency is
+    // greater than 10 GHz or less than 100 MHz
+    if(ret > 10000 || ret <  100) {
+      printBug("Invalid data was read from file '%s': %ld\n", CPUINFO_FREQUENCY_STR, ret);
+      return UNKNOWN_DATA;
+    }
+
+    return ret;
+  }
 }

src/ppc/udev.h

@@ -4,8 +4,13 @@
 #include "../common/udev.h"
 #define _PATH_DT                  "/proc/device-tree/vpd/root-node-vpd@a000/enclosure@1e00/backplane@800/processor@1000"
 #define _PATH_DT_PART             "/part-number"
+#define _PATH_DT_IBM_PARTIT_NAME  "/device-tree/ibm,partition-name"
+#define _PATH_DT_HMC_MANAGED      "/device-tree/hmc-managed?"
+#define _PATH_DT_QEMU_WIDTH       "/device-tree/chosen/qemu,graphic-width"
 
 bool fill_core_ids_from_sys(int *core_ids, int total_cores);
 bool fill_package_ids_from_sys(int* package_ids, int total_cores);
+int get_num_sockets_package_cpus(struct topology* topo);
+long get_frequency_from_cpuinfo(void);
 
 #endif

src/riscv/riscv.c

@@ -0,0 +1,180 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+
+#include "../common/global.h"
+#include "../common/udev.h"
+#include "udev.h"
+#include "uarch.h"
+#include "soc.h"
+
+#define SET_ISA_EXT_MAP(name, bit)          \
+  if(strncmp(multi_letter_extension, name,  \
+        multi_letter_extension_len) == 0) { \
+    ext->mask |= 1UL << bit;                \
+    maskset = true;                         \
+  }                                         \
+
+struct frequency* get_frequency_info(uint32_t core) {
+  struct frequency* freq = emalloc(sizeof(struct frequency));
+
+  freq->base = UNKNOWN_DATA;
+  freq->max = get_max_freq_from_file(core);
+
+  return freq;
+}
+
+int64_t get_peak_performance(struct cpuInfo* cpu) {
+  //First check we have consistent data
+  if(get_freq(cpu->freq) == UNKNOWN_DATA) {
+    return -1;
+  }
+
+  int64_t flops = cpu->topo->total_cores * (get_freq(cpu->freq) * 1000000);
+  return flops;
+}
+
+// Returns the length of the multi-letter
+// extension, or -1 if an error occurs
+int parse_multi_letter_extension(struct extensions* ext, char* e) {
+  if(*e != '_') return -1;
+  char* multi_letter_extension_end = strstr(e+1, "_");
+  if(multi_letter_extension_end == NULL) {
+    // This is the last extension, find the end
+    // of the string
+    multi_letter_extension_end = e + strlen(e);
+  }
+
+  int multi_letter_extension_len = multi_letter_extension_end-(e+1);
+  bool maskset = false;
+  char* multi_letter_extension = emalloc(multi_letter_extension_len);
+  strncpy(multi_letter_extension, e+1, multi_letter_extension_len);
+  // This should be up-to-date with
+  // https://elixir.bootlin.com/linux/latest/source/arch/riscv/kernel/cpufeature.c
+  // which should represent the list of extensions available in real chips
+  SET_ISA_EXT_MAP("sscofpmf",    RISCV_ISA_EXT_SSCOFPMF)
+  SET_ISA_EXT_MAP("sstc",        RISCV_ISA_EXT_SSTC)
+  SET_ISA_EXT_MAP("svinval",     RISCV_ISA_EXT_SVINVAL)
+  SET_ISA_EXT_MAP("svpbmt",      RISCV_ISA_EXT_SVPBMT)
+  SET_ISA_EXT_MAP("zbb",         RISCV_ISA_EXT_ZBB)
+  SET_ISA_EXT_MAP("zicbom",      RISCV_ISA_EXT_ZICBOM)
+  SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE)
+  SET_ISA_EXT_MAP("svnapot",     RISCV_ISA_EXT_SVNAPOT)
+  SET_ISA_EXT_MAP("zicboz",      RISCV_ISA_EXT_ZICBOZ)
+  SET_ISA_EXT_MAP("smaia",       RISCV_ISA_EXT_SMAIA)
+  SET_ISA_EXT_MAP("ssaia",       RISCV_ISA_EXT_SSAIA)
+  SET_ISA_EXT_MAP("zba",         RISCV_ISA_EXT_ZBA)
+  SET_ISA_EXT_MAP("zbs",         RISCV_ISA_EXT_ZBS)
+  SET_ISA_EXT_MAP("zicntr",      RISCV_ISA_EXT_ZICNTR)
+  SET_ISA_EXT_MAP("zicsr",       RISCV_ISA_EXT_ZICSR)
+  SET_ISA_EXT_MAP("zifencei",    RISCV_ISA_EXT_ZIFENCEI)
+  SET_ISA_EXT_MAP("zihpm",       RISCV_ISA_EXT_ZIHPM)
+  if(!maskset) {
+    printBug("parse_multi_letter_extension: Unknown multi-letter extension: %s", multi_letter_extension);
+    return -1;
+  }
+
+  return multi_letter_extension_len;
+}
+
+struct extensions* get_extensions_from_str(char* str) {
+  struct extensions* ext = emalloc(sizeof(struct extensions));
+  ext->mask = 0;
+  ext->str = NULL;
+
+  if(str == NULL) {
+    return ext;
+  }
+
+  int len = sizeof(char) * (strlen(str)+1);
+  ext->str = emalloc(sizeof(char) * len);
+  memset(ext->str, 0, len);
+  strncpy(ext->str, str, sizeof(char) * len);
+
+  // Code inspired in Linux kernel (riscv_fill_hwcap):
+  // https://elixir.bootlin.com/linux/v6.2.10/source/arch/riscv/kernel/cpufeature.c
+  char* isa = str;
+  if (!strncmp(isa, "rv32", 4))
+    isa += 4;
+  else if (!strncmp(isa, "rv64", 4))
+    isa += 4;
+  else {
+    printBug("get_extensions_from_str: ISA string must start with rv64 or rv32");
+    return ext;
+  }
+
+  for(char* e = isa; *e != '\0'; e++) {
+    if(*e == '_') {
+      // Multi-letter extension
+      int multi_letter_extension_len = parse_multi_letter_extension(ext, e);
+      if(multi_letter_extension_len == -1) {
+        return ext;
+      }
+      e += multi_letter_extension_len;
+    }
+    else {
+      int n = *e - 'a';
+      ext->mask |= 1UL << n;
+    }
+  }
+
+  return ext;
+}
+
+struct cpuInfo* get_cpu_info(void) {
+  struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
+  //init_cpu_info(cpu);
+  struct topology* topo = emalloc(sizeof(struct topology));
+  topo->total_cores = get_ncores_from_cpuinfo();
+  topo->cach = NULL;
+  cpu->topo = topo;
+
+  char* cpuinfo_str = get_uarch_from_cpuinfo();
+  char* ext_str = get_extensions_from_cpuinfo();
+  cpu->hv = emalloc(sizeof(struct hypervisor));
+  cpu->hv->present = false;
+  cpu->ext = get_extensions_from_str(ext_str);
+  if(cpu->ext->str != NULL && cpu->ext->mask == 0) return NULL;
+  cpu->arch = get_uarch_from_cpuinfo_str(cpuinfo_str, cpu);
+  cpu->soc = get_soc();
+  cpu->freq = get_frequency_info(0);
+  cpu->peak_performance = get_peak_performance(cpu);
+
+  return cpu;
+}
+
+//TODO: Might be worth refactoring with other archs
+char* get_str_topology(struct cpuInfo* cpu, struct topology* topo) {
+  uint32_t size = 3+7+1;
+  char* string = emalloc(sizeof(char)*size);
+  snprintf(string, size, "%d cores", topo->total_cores);
+
+  return string;
+}
+
+char* get_str_extensions(struct cpuInfo* cpu) {
+  if(cpu->ext != NULL) {
+    return cpu->ext->str;
+  }
+  return NULL;
+}
+
+void print_debug(struct cpuInfo* cpu) {
+  printf("- soc: ");
+  if(cpu->soc->raw_name == NULL) {
+    printf("NULL\n");
+  }
+  else {
+    printf("'%s'\n", cpu->soc->raw_name);
+  }
+
+  printf("- uarch: ");
+  char* arch_cpuinfo_str = get_arch_cpuinfo_str(cpu);
+  if(arch_cpuinfo_str == NULL) {
+    printf("NULL\n");
+  }
+  else {
+    printf("'%s'\n", arch_cpuinfo_str);
+  }
+}

src/riscv/riscv.h

@@ -0,0 +1,83 @@
+#ifndef __RISCV__
+#define __RISCV__
+
+#include "../common/cpu.h"
+
+struct extension {
+  int id;
+  char* str;
+};
+
+#define RISCV_ISA_EXT_NAME_LEN_MAX 32
+#define RISCV_ISA_EXT_BASE         26
+
+// https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/asm/hwcap.h
+// This enum represent the logical ID for multi-letter RISC-V ISA extensions.
+// The logical ID should start from RISCV_ISA_EXT_BASE
+enum riscv_isa_ext_id {
+  RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
+  RISCV_ISA_EXT_SSTC,
+  RISCV_ISA_EXT_SVINVAL,
+  RISCV_ISA_EXT_SVPBMT,
+  RISCV_ISA_EXT_ZBB,
+  RISCV_ISA_EXT_ZICBOM,
+  RISCV_ISA_EXT_ZIHINTPAUSE,
+  RISCV_ISA_EXT_SVNAPOT,
+  RISCV_ISA_EXT_ZICBOZ,
+  RISCV_ISA_EXT_SMAIA,
+  RISCV_ISA_EXT_SSAIA,
+  RISCV_ISA_EXT_ZBA,
+  RISCV_ISA_EXT_ZBS,
+  RISCV_ISA_EXT_ZICNTR,
+  RISCV_ISA_EXT_ZICSR,
+  RISCV_ISA_EXT_ZIFENCEI,
+  RISCV_ISA_EXT_ZIHPM,
+  RISCV_ISA_EXT_ID_MAX
+};
+
+// https://five-embeddev.com/riscv-isa-manual/latest/preface.html#preface
+// https://en.wikichip.org/wiki/risc-v/standard_extensions
+// Included all except for G
+static const struct extension extension_list[] = {
+  { 'i' - 'a', "(I) Integer Instruction Set" },
+  { 'm' - 'a', "(M) Integer Multiplication and Division" },
+  { 'a' - 'a', "(A) Atomic Instructions" },
+  { 'f' - 'a', "(F) Single-Precision Floating-Point" },
+  { 'd' - 'a', "(D) Double-Precision Floating-Point" },
+  { 'q' - 'a', "(Q) Quad-Precision Floating-Point" },
+  { 'l' - 'a', "(L) Decimal Floating-Point" },
+  { 'c' - 'a', "(C) Compressed Instructions" },
+  { 'b' - 'a', "(B) Double-Precision Floating-Point" },
+  { 'j' - 'a', "(J) Dynamically Translated Languages" },
+  { 't' - 'a', "(T) Transactional Memory" },
+  { 'p' - 'a', "(P) Packed-SIMD Instructions" },
+  { 'v' - 'a', "(V) Vector Operations" },
+  { 'n' - 'a', "(N) User-Level Interrupts" },
+  { 'h' - 'a', "(H) Hypervisor" },
+  { 's' - 'a', "(S) Supervisor-level Instructions" },
+  // multi-letter extensions
+  { RISCV_ISA_EXT_SSCOFPMF,    "(Sscofpmf) Count OverFlow and Privilege Mode Filtering" },
+  { RISCV_ISA_EXT_SSTC,        "(Sstc) S and VS level Time Compare" },
+  { RISCV_ISA_EXT_SVINVAL,     "(Svinval) Fast TLB Invalidation" },
+  { RISCV_ISA_EXT_SVPBMT,      "(Svpbmt) Page-based Memory Types" },
+  { RISCV_ISA_EXT_ZBB,         "(Zbb) Basic bit-manipulation" },
+  { RISCV_ISA_EXT_ZICBOM,      "(Zicbom) Cache Block Management Operations" },
+  { RISCV_ISA_EXT_ZIHINTPAUSE, "(Zihintpause) Pause Hint" },
+  { RISCV_ISA_EXT_SVNAPOT,     "(Svnapot) Naturally Aligned Power of Two Pages" },
+  { RISCV_ISA_EXT_ZICBOZ,      "(Zicboz) Cache Block Zero Operations" },
+  { RISCV_ISA_EXT_SMAIA,       "(Smaia) Advanced Interrupt Architecture" },
+  { RISCV_ISA_EXT_SSAIA,       "(Ssaia) Advanced Interrupt Architecture" },
+  { RISCV_ISA_EXT_ZBA,         "(Zba) Address Generation" },
+  { RISCV_ISA_EXT_ZBS,         "(Zbs) Single-bit Instructions" },
+  { RISCV_ISA_EXT_ZICNTR,      "(Zicntr) Base Counters and Timers" },
+  { RISCV_ISA_EXT_ZICSR,       "(Zicsr) Control and Status Register" },
+  { RISCV_ISA_EXT_ZIFENCEI,    "(Zifencei) Instruction-Fetch Fence" },
+  { RISCV_ISA_EXT_ZIHPM,       "(Zihpm) Hardware Performance Counters" }
+};
+
+struct cpuInfo* get_cpu_info(void);
+char* get_str_topology(struct cpuInfo* cpu, struct topology* topo);
+char* get_str_extensions(struct cpuInfo* cpu);
+void print_debug(struct cpuInfo* cpu);
+
+#endif

src/riscv/soc.c

@@ -0,0 +1,84 @@
+#include "soc.h"
+#include "socs.h"
+#include "udev.h"
+#include "../common/global.h"
+
+#include <string.h>
+
+bool match_sifive(char* soc_name, struct system_on_chip* soc) {
+  char* tmp = soc_name;
+
+  // Dont know if it makes sense in RISC-V
+  /*if((tmp = strstr(soc_name, "???")) == NULL)
+    return false;*/
+
+  //soc->soc_vendor = ???
+
+  SOC_START
+  SOC_EQ(tmp, "fu740", "Freedom U740",  SOC_SIFIVE_U740, soc, 40)
+  SOC_END
+}
+
+bool match_starfive(char* soc_name, struct system_on_chip* soc) {
+  SOC_START
+  SOC_EQ(soc_name, "jh7110#", "VisionFive 2",  SOC_STARFIVE_VF2, soc, 28) // https://blog.bitsofnetworks.org/benchmarking-risc-v-visionfive-2-vs-the-world.html
+  SOC_EQ(soc_name, "jh7110",  "VisionFive 2",  SOC_STARFIVE_VF2, soc, 28)
+  SOC_END
+}
+
+bool match_allwinner(char* soc_name, struct system_on_chip* soc) {
+  SOC_START
+  SOC_EQ(soc_name, "sun20i-d1", "D1-H", SOC_ALLWINNER_D1H, soc, 22)
+  SOC_END
+}
+
+struct system_on_chip* parse_soc_from_string(struct system_on_chip* soc) {
+  char* raw_name = soc->raw_name;
+
+  if(match_starfive(raw_name, soc))
+    return soc;
+
+  if(match_allwinner(raw_name, soc))
+    return soc;
+
+  match_sifive(raw_name, soc);
+  return soc;
+}
+
+struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
+  char* tmp = get_hardware_from_devtree();
+
+  if(tmp != NULL) {
+    soc->raw_name = tmp;
+    return parse_soc_from_string(soc);
+  }
+
+  return soc;
+}
+
+struct system_on_chip* get_soc(void) {
+  struct system_on_chip* soc = emalloc(sizeof(struct system_on_chip));
+  soc->raw_name = NULL;
+  soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+  soc->soc_model = SOC_MODEL_UNKNOWN;
+  soc->process = UNKNOWN;
+
+  soc = guess_soc_from_devtree(soc);
+  if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+    if(soc->raw_name != NULL) {
+      printWarn("SoC detection failed using device tree: Found '%s' string", soc->raw_name);
+    }
+    else {
+      printWarn("SoC detection failed using device tree");
+    }
+  }
+
+  if(soc->soc_model == SOC_MODEL_UNKNOWN) {
+    // raw_name might not be NULL, but if we were unable to find
+    // the exact SoC, just print "Unkwnown"
+    soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
+    snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
+  }
+
+  return soc;
+}

src/riscv/soc.h

@@ -0,0 +1,10 @@
+#ifndef __SOC_RISCV__
+#define __SOC_RISCV__
+
+#include "../common/soc.h"
+#include "../common/cpu.h"
+#include <stdint.h>
+
+struct system_on_chip* get_soc(void);
+
+#endif

src/riscv/socs.h

@@ -0,0 +1,25 @@
+#ifndef __SOCS__
+#define __SOCS__
+
+#include "soc.h"
+
+// List of supported SOCs
+enum {
+  // SIFIVE
+  SOC_SIFIVE_U740,
+  // STARFIVE
+  SOC_STARFIVE_VF2,
+  // ALLWINNER
+  SOC_ALLWINNER_D1H,
+  // UNKNOWN
+  SOC_MODEL_UNKNOWN
+};
+
+inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
+  if(soc >= SOC_SIFIVE_U740 && soc <= SOC_SIFIVE_U740) return SOC_VENDOR_SIFIVE;
+  if(soc >= SOC_STARFIVE_VF2 && soc <= SOC_STARFIVE_VF2) return SOC_VENDOR_STARFIVE;
+  if(soc >= SOC_ALLWINNER_D1H && soc <= SOC_ALLWINNER_D1H) return SOC_VENDOR_ALLWINNER;
+  return SOC_VENDOR_UNKNOWN;
+}
+
+#endif

src/riscv/uarch.c

@@ -0,0 +1,84 @@
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "uarch.h"
+#include "../common/global.h"
+
+typedef uint32_t MICROARCH;
+
+struct uarch {
+  MICROARCH uarch;
+  char* uarch_str;
+  char* cpuinfo_str;
+};
+
+enum {
+  UARCH_UNKNOWN,
+  // SIFIVE
+  UARCH_U54,
+  UARCH_U74,
+  // THEAD
+  UARCH_C906,
+  UARCH_C910
+};
+
+#define UARCH_START if (false) {}
+#define CHECK_UARCH(arch, cpu, cpuinfo_str, uarch_str, str, uarch, vendor) \
+   else if (strcmp(cpuinfo_str, uarch_str) == 0) fill_uarch(arch, cpu, str, uarch, vendor);
+#define UARCH_END else { printBug("Unknown microarchitecture detected: uarch='%s'", cpuinfo_str); fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
+
+void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
+  arch->uarch = u;
+  cpu->cpu_vendor = vendor;
+  arch->uarch_str = emalloc(sizeof(char) * (strlen(str)+1));
+  strcpy(arch->uarch_str, str);
+}
+
+// https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/riscv/cpus.yaml
+// SiFive: https://www.sifive.com/risc-v-core-ip
+// T-Head: https://www.t-head.cn/product/c906
+struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu) {
+  struct uarch* arch = emalloc(sizeof(struct uarch));
+  arch->cpuinfo_str = cpuinfo_str;
+  if(cpuinfo_str == NULL) {
+    printWarn("get_uarch_from_cpuinfo: Unable to detect microarchitecture, cpuinfo_str is NULL");
+    fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN);
+    return arch;
+  }
+
+  // U74/U74-MC:
+  // SiFive says that U74-MC is "Multicore: four U74 cores and one S76 core" while
+  // U74 is "High performance Linux-capable processor". It's like U74-MC is somehow a small SoC containing
+  // the U74 and the S76? Then U74-MC is not a microarchitecture per se...
+  UARCH_START
+  CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,bullet0", "U74",         UARCH_U74, CPU_VENDOR_SIFIVE) // bullet0 is present in U740, which has U74
+  // CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,e5",      "XXXXXX",      UARCH_U74, CPU_VENDOR_SIFIVE)
+  // CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,e7",      "XXXXXX",      UARCH_U74, CPU_VENDOR_SIFIVE)
+  // CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,e71",     "XXXXXX",      UARCH_U74, CPU_VENDOR_SIFIVE)
+  // CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,rocket0", "XXXXXX",      UARCH_U74, CPU_VENDOR_SIFIVE)
+  // CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u5",      "XXXXXX",      UARCH_U74, CPU_VENDOR_SIFIVE)
+  CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u54",     "U54",         UARCH_U54,  CPU_VENDOR_SIFIVE)
+  // CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u7",      "XXXXXX",      UARCH_U74, CPU_VENDOR_SIFIVE)
+  CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u74",     "U74",         UARCH_U74,  CPU_VENDOR_SIFIVE)
+  CHECK_UARCH(arch, cpu, cpuinfo_str, "sifive,u74-mc",  "U74",         UARCH_U74,  CPU_VENDOR_SIFIVE)
+  CHECK_UARCH(arch, cpu, cpuinfo_str, "thead,c906",     "T-Head C906", UARCH_C906, CPU_VENDOR_THEAD)
+  CHECK_UARCH(arch, cpu, cpuinfo_str, "thead,c910",     "T-Head C910", UARCH_C910, CPU_VENDOR_THEAD)
+  UARCH_END
+
+  return arch;
+}
+
+char* get_str_uarch(struct cpuInfo* cpu) {
+  return cpu->arch->uarch_str;
+}
+
+char* get_arch_cpuinfo_str(struct cpuInfo* cpu) {
+  return cpu->arch->cpuinfo_str;
+}
+
+void free_uarch_struct(struct uarch* arch) {
+  free(arch->uarch_str);
+  free(arch);
+}

src/riscv/uarch.h

@@ -0,0 +1,14 @@
+#ifndef __UARCH__
+#define __UARCH__
+
+#include <stdint.h>
+#include "riscv.h"
+
+struct uarch;
+
+char* get_arch_cpuinfo_str(struct cpuInfo* cpu);
+char* get_str_uarch(struct cpuInfo* cpu);
+void free_uarch_struct(struct uarch* arch);
+struct uarch* get_uarch_from_cpuinfo_str(char* cpuinfo_str, struct cpuInfo* cpu);
+
+#endif

src/riscv/udev.c

@@ -0,0 +1,91 @@
+#include <errno.h>
+#include <string.h>
+
+#include "../common/global.h"
+#include "udev.h"
+
+#define _PATH_DEVTREE          "/proc/device-tree/compatible"
+#define CPUINFO_UARCH_STR      "uarch\t\t: "
+#define CPUINFO_EXTENSIONS_STR "isa\t\t: "
+#define DEVTREE_HARDWARE_FIELD 0
+
+char* get_field_from_devtree(int DEVTREE_FIELD) {
+  int filelen;
+  char* buf;
+  if((buf = read_file(_PATH_DEVTREE, &filelen)) == NULL) {
+    printWarn("read_file: %s: %s", _PATH_DEVTREE, strerror(errno));
+    return NULL;
+  }
+
+  // Here we would use strstr to find the comma.
+  // However, the device-tree file may contain NULL
+  // bytes in the middle of the string, which would
+  // cause strstr to return NULL even when there might
+  // be an occurence after the NULL byte
+  //
+  // We iterate the string backwards to find the field
+  // in position n-DEVTREE_HARDWARE_FIELD where n
+  // is the number of fields.
+  int i=0;
+  char* tmp1 = buf+filelen-1;
+  do {
+    tmp1--;
+    if(*tmp1 == ',') i++;
+  } while(tmp1 != buf && i <= DEVTREE_FIELD);
+
+  if(tmp1 == buf) {
+    printWarn("get_field_from_devtree: Unable to find field %d", DEVTREE_FIELD);
+    return NULL;
+  }
+
+  tmp1++;
+  int strlen = filelen-(tmp1-buf);
+  char* hardware = emalloc(sizeof(char) * strlen);
+  memset(hardware, 0, sizeof(char) * strlen);
+  strncpy(hardware, tmp1, strlen-1);
+
+  return hardware;
+}
+
+char* parse_cpuinfo_field(char* field_str) {
+  int filelen;
+  char* buf;
+  if((buf = read_file(_PATH_CPUINFO, &filelen)) == NULL) {
+    printWarn("read_file: %s: %s", _PATH_CPUINFO, strerror(errno));
+    return NULL;
+  }
+
+  char* tmp = strstr(buf, field_str);
+  if(tmp == NULL) {
+    printWarn("parse_cpuinfo_field: Unable to find field %s", field_str);
+    return NULL;
+  }
+
+  tmp += strlen(field_str);
+  char* end = strstr(tmp, "\n");
+
+  if(end == NULL) {
+    printWarn("parse_cpuinfo_field: Unable to find newline after field %s", field_str);
+    return NULL;
+  }
+
+  int ret_strlen = (end-tmp);
+  char* ret = emalloc(sizeof(char) * (ret_strlen+1));
+  memset(ret, 0, sizeof(char) * (ret_strlen+1));
+  strncpy(ret, tmp, ret_strlen);
+
+  return ret;
+}
+
+char* get_hardware_from_devtree(void) {
+  return get_field_from_devtree(DEVTREE_HARDWARE_FIELD);
+}
+
+char* get_uarch_from_cpuinfo(void) {
+  return parse_cpuinfo_field(CPUINFO_UARCH_STR);
+}
+
+char* get_extensions_from_cpuinfo(void) {
+  return parse_cpuinfo_field(CPUINFO_EXTENSIONS_STR);
+}
+

src/riscv/udev.h

@@ -0,0 +1,12 @@
+#ifndef __UDEV_RISCV__
+#define __UDEV_RISCV__
+
+#include "../common/udev.h"
+
+#define UNKNOWN -1
+
+char* get_hardware_from_devtree(void);
+char* get_uarch_from_cpuinfo(void);
+char* get_extensions_from_cpuinfo(void);
+
+#endif

src/x86/apic.c

@@ -7,8 +7,6 @@
 #elif defined __FreeBSD__
   #include <sys/param.h>
   #include <sys/cpuset.h>
-#elif defined __APPLE__
-  #define UNUSED(x) (void)(x)
 #endif
 
 #include <stdlib.h>
@@ -102,6 +100,7 @@ bool bind_to_cpu(int cpu_id) {
 }
 #endif
 
+#ifdef __linux__
 int get_total_cores_module(int total_cores, int module) {
   int total_modules = 2;
   int32_t current_module_idx = -1;
@@ -154,6 +153,7 @@ int get_total_cores_module(int total_cores, int module) {
   //printf("Module %d has %d cores\n", module, cores_in_module);
   return cores_in_module;
 }
+#endif
 
 bool fill_topo_masks_apic(struct topology* topo) {
   uint32_t eax = 0x00000001;
@@ -353,6 +353,7 @@ void add_apic_to_array(uint32_t apic, uint32_t* apic_ids, int n) {
 bool fill_apic_ids(uint32_t* apic_ids, int first_core, int n, bool x2apic_id) {
 #ifdef __APPLE__
   // macOS extremely dirty approach...
+  UNUSED(first_core);
   printf("cpufetch is computing APIC IDs, please wait...\n");
   bool end = false;
   uint32_t apic;

src/x86/apic.h

@@ -21,6 +21,8 @@ uint32_t is_smt_enabled_amd(struct topology* topo);
 bool bind_to_cpu(int cpu_id);
 #endif
 
+#ifdef __linux__
 int get_total_cores_module(int total_cores, int module);
+#endif
 
 #endif

src/x86/cpuid.c

@@ -30,6 +30,8 @@ static const char *hv_vendors_string[] = {
   [HV_VENDOR_VMWARE]    = "VMwareVMware",
   [HV_VENDOR_XEN]       = "XenVMMXenVMM",
   [HV_VENDOR_PARALLELS] = "lrpepyh vr",
+  [HV_VENDOR_BHYVE]     = "bhyve bhyve ",
+  [HV_VENDOR_PHYP]      = NULL
 };
 
 static char *hv_vendors_name[] = {
@@ -39,11 +41,11 @@ static char *hv_vendors_name[] = {
   [HV_VENDOR_VMWARE]    = "VMware",
   [HV_VENDOR_XEN]       = "Xen",
   [HV_VENDOR_PARALLELS] = "Parallels",
+  [HV_VENDOR_PHYP]      = "pHyp",
+  [HV_VENDOR_BHYVE]     = "bhyve",
   [HV_VENDOR_INVALID]   = STRING_UNKNOWN
 };
 
-#define HYPERVISOR_NAME_MAX_LENGTH 17
-
 #define MASK 0xFF
 
 /*
@@ -70,7 +72,7 @@ void get_name_cpuid(char* name, uint32_t reg1, uint32_t reg2, uint32_t reg3) {
   name[c++] = (reg3>>24) & MASK;
 }
 
-char* get_str_cpu_name_internal() {
+char* get_str_cpu_name_internal(void) {
   uint32_t eax = 0;
   uint32_t ebx = 0;
   uint32_t ecx = 0;
@@ -223,9 +225,10 @@ int64_t get_peak_performance(struct cpuInfo* cpu, bool accurate_pp) {
     if(feat->FMA3 || feat->FMA4)
       flops = flops*2;
 
-    // Ice Lake has AVX512, but it has 1 VPU for AVX512, while
+    // NOTE:
-    // it has 2 for AVX2. If this is a Ice Lake CPU, we are computing
+    // Some CPUs (Ice Lake, Zen 4) have AVX512, but they have only
-    // the peak performance supposing AVX2, not AVX512
+    // 1 VPU for AVX512, while they have 2 for AVX2. In such cases,
+    // we are computing the peak performance supposing AVX2, not AVX512
     if(feat->AVX512 && vpus_are_AVX512(ptr))
       flops = flops*16;
     else if(feat->AVX || feat->AVX2)
@@ -260,6 +263,11 @@ struct hypervisor* get_hp_info(bool hv_present) {
 
   cpuid(&eax, &ebx, &ecx, &edx);
 
+  if(ebx == 0x0 && ecx == 0x0 && edx == 0x0) {
+    hv->hv_vendor = HV_VENDOR_INVALID;
+    printWarn("Hypervisor vendor is empty");
+  }
+  else {
     char name[13];
     memset(name, 0, 13);
     get_name_cpuid(name, ebx, ecx, edx);
@@ -268,7 +276,7 @@ struct hypervisor* get_hp_info(bool hv_present) {
     uint8_t len = sizeof(hv_vendors_string) / sizeof(hv_vendors_string[0]);
 
     for(uint8_t v=0; v < len && !found; v++) {
-    if(strcmp(hv_vendors_string[v], name) == 0) {
+      if(hv_vendors_string[v] != NULL && strcmp(hv_vendors_string[v], name) == 0) {
         hv->hv_vendor = v;
         found = true;
       }
@@ -276,7 +284,8 @@ struct hypervisor* get_hp_info(bool hv_present) {
 
     if(!found) {
       hv->hv_vendor = HV_VENDOR_INVALID;
-    printWarn("Unknown hypervisor vendor: %s", name);
+      printBug("Unknown hypervisor vendor: %s", name);
+    }
   }
 
   hv->hv_name = hv_vendors_name[hv->hv_vendor];
@@ -356,6 +365,11 @@ struct features* get_features_info(struct cpuInfo* cpu) {
 
 bool set_cpu_module(int m, int total_modules, int32_t* first_core) {
   if(total_modules > 1) {
+    #ifdef __APPLE__
+    UNUSED(m);
+    printBug("Hybrid architectures are not supported under macOS");
+    return false;
+    #else
     // We have a hybrid architecture.
     // 1. Find the first core from module m
     int32_t core_id = -1;
@@ -397,12 +411,17 @@ bool set_cpu_module(int m, int total_modules, int32_t* first_core) {
     if(!bind_to_cpu(core_id)) {
       return false;
     }
+    #endif
+  }
+  else {
+    // This is a normal architecture
+    *first_core = 0;
   }
 
   return true;
 }
 
-int32_t get_core_type() {
+int32_t get_core_type(void) {
   uint32_t eax = 0x0000001A;
   uint32_t ebx = 0;
   uint32_t ecx = 0;
@@ -420,7 +439,7 @@ int32_t get_core_type() {
   }
 }
 
-struct cpuInfo* get_cpu_info() {
+struct cpuInfo* get_cpu_info(void) {
   struct cpuInfo* cpu = emalloc(sizeof(struct cpuInfo));
   cpu->peak_performance = -1;
   cpu->next_cpu = NULL;
@@ -615,6 +634,7 @@ bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
   return true;
 }
 
+#ifdef __linux__
 void get_topology_from_udev(struct topology* topo) {
   // TODO: To be improved in the future
   topo->total_cores = get_ncores_from_cpuinfo();
@@ -624,6 +644,7 @@ void get_topology_from_udev(struct topology* topo) {
   topo->smt_supported = 1;
   topo->sockets = 1;
 }
+#endif
 
 // Main reference: https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html
 // Very interesting resource: https://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
@@ -652,7 +673,12 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
   #endif
 
   if(cpu->hybrid_flag) {
+    #ifdef __linux__
       topo->total_cores_module = get_total_cores_module(topo->total_cores, module);
+    #else
+      UNUSED(module);
+      topo->total_cores_module = topo->total_cores;
+    #endif
   }
   else {
     topo->total_cores_module = topo->total_cores;
@@ -1069,12 +1095,29 @@ void print_debug(struct cpuInfo* cpu) {
   free_cpuinfo_struct(cpu);
 }
 
-// TODO: Query HV and Xeon Phi levels
+void print_raw_level(uint32_t reg) {
+  uint32_t eax = reg;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+
+  cpuid(&eax, &ebx, &ecx, &edx);
+
+  printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
+}
+
+void print_raw_sublevel(uint32_t reg, uint32_t reg2) {
+  uint32_t eax = reg;
+  uint32_t ebx = 0;
+  uint32_t ecx = reg2;
+  uint32_t edx = 0;
+
+  cpuid(&eax, &ebx, &ecx, &edx);
+
+  printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
+}
+
 void print_raw(struct cpuInfo* cpu) {
-  uint32_t eax;
-  uint32_t ebx;
-  uint32_t ecx;
-  uint32_t edx;
   printf("%s\n\n", cpu->cpu_name);
   printf("  CPUID leaf sub   EAX        EBX        ECX        EDX       \n");
   printf("--------------------------------------------------------------\n");
@@ -1089,66 +1132,40 @@ void print_raw(struct cpuInfo* cpu) {
 
     printf("CPU %d:\n", c);
 
+    // Standard levels
     for(uint32_t reg=0x00000000; reg <= cpu->maxLevels; reg++) {
       if(reg == 0x00000004) {
         for(uint32_t reg2=0x00000000; reg2 < cpu->cach->max_cache_level; reg2++) {
-          eax = reg;
+          print_raw_sublevel(reg, reg2);
-          ebx = 0;
-          ecx = reg2;
-          edx = 0;
-
-          cpuid(&eax, &ebx, &ecx, &edx);
-
-          printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
         }
       }
       else if(reg == 0x0000000B) {
         for(uint32_t reg2=0x00000000; reg2 < cpu->topo->smt_supported; reg2++) {
-          eax = reg;
+          print_raw_sublevel(reg, reg2);
-          ebx = 0;
-          ecx = reg2;
-          edx = 0;
-
-          cpuid(&eax, &ebx, &ecx, &edx);
-
-          printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
         }
       }
       else {
-        eax = reg;
+        print_raw_level(reg);
-        ebx = 0;
-        ecx = 0;
-        edx = 0;
-
-        cpuid(&eax, &ebx, &ecx, &edx);
-
-        printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
       }
     }
+
+    // Hypervisor levels
+    for(uint32_t reg=0x40000000; reg <= 0x40000006; reg++) {
+      print_raw_level(reg);
+    }
+
+    // Extended levels
     for(uint32_t reg=0x80000000; reg <= cpu->maxExtendedLevels; reg++) {
       if(reg == 0x8000001D) {
         for(uint32_t reg2=0x00000000; reg2 < cpu->cach->max_cache_level; reg2++) {
-          eax = reg;
+          print_raw_sublevel(reg, reg2);
-          ebx = 0;
-          ecx = reg2;
-          edx = 0;
-
-          cpuid(&eax, &ebx, &ecx, &edx);
-
-          printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, reg2, eax, ebx, ecx, edx);
         }
       }
       else {
-        eax = reg;
+        print_raw_level(reg);
-        ebx = 0;
-        ecx = 0;
-        edx = 0;
-
-        cpuid(&eax, &ebx, &ecx, &edx);
-
-        printf("  0x%.8X 0x%.2X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 0x00, eax, ebx, ecx, edx);
       }
     }
+
   }
 }
 

src/x86/cpuid.h

@@ -3,7 +3,7 @@
 
 #include "../common/cpu.h"
 
-struct cpuInfo* get_cpu_info();
+struct cpuInfo* get_cpu_info(void);
 struct cache* get_cache_info(struct cpuInfo* cpu);
 struct frequency* get_frequency_info(struct cpuInfo* cpu);
 struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int module);

src/x86/freq/freq.h

@@ -3,6 +3,7 @@
 
 #include <stdint.h>
 #include "../../common/cpu.h"
+#include "../../common/global.h"
 
 #define MEASURE_TIME_SECONDS         5
 #define LOOP_ITERS           100000000

src/x86/freq/freq_avx.c

@@ -10,7 +10,8 @@
 #include <stdint.h>
 #include "freq.h"
 
-void* compute_avx() {
+void* compute_avx(void * pthread_arg) {
+  UNUSED(pthread_arg);
   bool end = false;
 
   struct timeval begin, now;

src/x86/freq/freq_avx.h

@@ -1,6 +1,6 @@
 #ifndef __FREQ_AVX__
 #define __FREQ_AVX__
 
-void* compute_avx();
+void* compute_avx(void * pthread_arg);
 
 #endif

src/x86/freq/freq_avx512.c

@@ -10,7 +10,8 @@
 #include <stdint.h>
 #include "freq.h"
 
-void* compute_avx512() {
+void* compute_avx512(void * pthread_arg) {
+  UNUSED(pthread_arg);
   bool end = false;
 
   struct timeval begin, now;

src/x86/freq/freq_avx512.h

@@ -1,6 +1,6 @@
 #ifndef __FREQ_AVX512__
 #define __FREQ_AVX512__
 
-void* compute_avx512();
+void* compute_avx512(void * pthread_arg);
 
 #endif

src/x86/freq/freq_nov.c

@@ -10,7 +10,8 @@
 #include <stdint.h>
 #include "freq.h"
 
-void* compute_nov() {
+void* compute_nov(void * pthread_arg) {
+  UNUSED(pthread_arg);
   bool end = false;
 
   struct timeval begin, now;

src/x86/freq/freq_nov.h

@@ -1,6 +1,6 @@
 #ifndef __FREQ_NO_VECTOR__
 #define __FREQ_NO_VECTOR__
 
-void* compute_nov();
+void* compute_nov(void * pthread_arg);
 
 #endif

src/x86/uarch.c

@@ -91,6 +91,7 @@ enum {
   UARCH_ICE_LAKE,
   UARCH_TIGER_LAKE,
   UARCH_ALDER_LAKE,
+  UARCH_RAPTOR_LAKE,
   // AMD //
   UARCH_AM486,
   UARCH_AM5X86,
@@ -227,12 +228,12 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 0,  6,  8, 12, NA, "Tiger Lake",      UARCH_TIGER_LAKE,       10) // instlatx64
   CHECK_UARCH(arch, 0,  6,  8, 13, NA, "Tiger Lake",      UARCH_TIGER_LAKE,       10) // instlatx64
   // CHECK_UARCH(arch, 0,  6,  8, 14,  9, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
-  CHECK_UARCH(arch, 0,  6,  8, 14, 10, "Coffee Lake",     UARCH_COFFEE_LAKE,      14) // wikichip
+  // CHECK_UARCH(arch, 0,  6,  8, 14, 10, ...) It is not possible to determine uarch only from CPUID dump (can be Kaby Lake R or Coffee Lake U)
   CHECK_UARCH(arch, 0,  6,  8, 14, 11, "Whiskey Lake",    UARCH_WHISKEY_LAKE,     14) // wikichip
   CHECK_UARCH(arch, 0,  6,  8, 14, 12, "Comet Lake",      UARCH_COMET_LAKE,       14) // wikichip
   CHECK_UARCH(arch, 0,  6,  9,  6, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
-  CHECK_UARCH(arch, 0,  6,  9,  7, NA, "Alder Lake",      UARCH_ALDER_LAKE,       10) // wikichip
+  CHECK_UARCH(arch, 0,  6,  9,  7, NA, "Alder Lake",      UARCH_ALDER_LAKE,       10) // instlatx64 (Alder Lake-S)
-  CHECK_UARCH(arch, 0,  6,  9, 10, NA, "Tremont",         UARCH_TREMONT,          10) // instlatx64
+  CHECK_UARCH(arch, 0,  6,  9, 10, NA, "Alder Lake",      UARCH_ALDER_LAKE,       10) // instlatx64 (Alder Lake-P)
   CHECK_UARCH(arch, 0,  6,  9, 12, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
   CHECK_UARCH(arch, 0,  6,  9, 13, NA, "Sunny Cove",      UARCH_SUNNY_COVE,       10) // LX*
   CHECK_UARCH(arch, 0,  6,  9, 14,  9, "Kaby Lake",       UARCH_KABY_LAKE,        14)
@@ -243,6 +244,10 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 0,  6, 10,  5, NA, "Comet Lake",      UARCH_COMET_LAKE,       14) // wikichip
   CHECK_UARCH(arch, 0,  6, 10,  6, NA, "Comet Lake",      UARCH_COMET_LAKE,       14) // instlatx64.atw.hu (i7-10710U)
   CHECK_UARCH(arch, 0,  6, 10,  7, NA, "Rocket Lake",     UARCH_ROCKET_LAKE,      14) // instlatx64.atw.hu (i7-11700K)
+  CHECK_UARCH(arch, 0,  6, 11,  7, NA, "Raptor Lake",     UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i5-13600K)
+  CHECK_UARCH(arch, 0,  6, 11, 10, NA, "Raptor Lake",     UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i7-1370P)
+  CHECK_UARCH(arch, 0,  6, 11, 14, NA, "Alder Lake",      UARCH_ALDER_LAKE,       10) // instlatx64.atw.hu (Alder Lake-N)
+  CHECK_UARCH(arch, 0,  6, 11, 15, NA, "Raptor Lake",     UARCH_RAPTOR_LAKE,      10) // instlatx64.atw.hu (i5-13500)
   CHECK_UARCH(arch, 0, 11,  0,  0, NA, "Knights Ferry",   UARCH_KNIGHTS_FERRY,    45) // found only on en.wikichip.org
   CHECK_UARCH(arch, 0, 11,  0,  1, NA, "Knights Corner",  UARCH_KNIGHTS_CORNER,   22)
   CHECK_UARCH(arch, 0, 15,  0,  0, NA, "Willamette",      UARCH_WILLAMETTE,      180)
@@ -255,7 +260,6 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 1, 15,  0,  1, NA, "Itanium2",        UARCH_ITANIUM2,        130)
   CHECK_UARCH(arch, 1, 15,  0,  2, NA, "Itanium2",        UARCH_ITANIUM2,        130)
   UARCH_END
-
   return arch;
 }
 
@@ -365,7 +369,9 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
   CHECK_UARCH(arch, 10, 15,  2,  1, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
   CHECK_UARCH(arch, 10, 15,  4,  4, NA, "Zen 3+",      UARCH_ZEN3_PLUS,    6) // instlatx64 (they say it is Zen3...)
   CHECK_UARCH(arch, 10, 15,  5,  0, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  1,  1, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64
   CHECK_UARCH(arch, 10, 15,  6,  1,  2, "Zen 4",       UARCH_ZEN4,         5) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  7,  4,  1, "Zen 4",       UARCH_ZEN4,         4) // instlatx64
   UARCH_END
 
   return arch;
@@ -375,6 +381,7 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
   if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
     if(dump == 0x000806E9) {
       // It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
+      // See issue https://github.com/Dr-Noob/cpufetch/issues/122
       struct uarch* arch = emalloc(sizeof(struct uarch));
 
       if(strstr(cpu->cpu_name, "Y") != NULL) {
@@ -386,6 +393,23 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
 
       return arch;
     }
+    else if (dump == 0x000806EA) {
+      // It is not possible to determine uarch only from CPUID dump (can be Kaby Lake R or Coffee Lake U)
+      // See issue https://github.com/Dr-Noob/cpufetch/issues/149
+      struct uarch* arch = emalloc(sizeof(struct uarch));
+
+      if(strstr(cpu->cpu_name, "i5-8250U") != NULL ||
+         strstr(cpu->cpu_name, "i5-8350U") != NULL ||
+         strstr(cpu->cpu_name, "i7-8550U") != NULL ||
+         strstr(cpu->cpu_name, "i7-8650U") != NULL) {
+        fill_uarch(arch, "Kaby Lake", UARCH_KABY_LAKE, 14);
+      }
+      else {
+        fill_uarch(arch, "Coffee Lake", UARCH_COFFEE_LAKE, 14);
+      }
+
+      return arch;
+    }
     return get_uarch_from_cpuid_intel(ef, f, em, m, s);
   }
   else
@@ -393,7 +417,9 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
 }
 
 bool vpus_are_AVX512(struct cpuInfo* cpu) {
-  return cpu->arch->uarch != UARCH_ICE_LAKE && cpu->arch->uarch != UARCH_TIGER_LAKE;
+  return cpu->arch->uarch != UARCH_ICE_LAKE &&
+         cpu->arch->uarch != UARCH_TIGER_LAKE &&
+         cpu->arch->uarch != UARCH_ZEN4;
 }
 
 bool is_knights_landing(struct cpuInfo* cpu) {
@@ -422,6 +448,7 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
       case UARCH_ICE_LAKE:
       case UARCH_TIGER_LAKE:
       case UARCH_ALDER_LAKE:
+      case UARCH_RAPTOR_LAKE:
 
       // AMD
       case UARCH_ZEN2:
@@ -439,6 +466,7 @@ bool choose_new_intel_logo_uarch(struct cpuInfo* cpu) {
     case UARCH_ALDER_LAKE:
     case UARCH_ROCKET_LAKE:
     case UARCH_TIGER_LAKE:
+    case UARCH_RAPTOR_LAKE:
       return true;
     default:
       return false;