[v1.06][ARM] Add SC8280XP (on device tree) (#272)

There are cases where measure_frequency is called after binding the
process to a specific core via bind_to_cpu (e.g., when iterating over
modules in hybrid architectures). Thus, in measure_frequency we must
set the affinity of the newly created threads, ensuring they are
binded to the right core.

Makefile

@@ -13,17 +13,27 @@ COMMON_HDR = $(SRC_COMMON)ascii.h $(SRC_COMMON)cpu.h $(SRC_COMMON)udev.h $(SRC_C
 ifneq ($(OS),Windows_NT)
 	GIT_VERSION := "$(shell git describe --abbrev=4 --dirty --always --tags)"
 	arch := $(shell uname -m)
+	os := $(shell uname -s)
+
+	ifeq ($(os), Linux)
+		COMMON_SRC += $(SRC_COMMON)freq.c
+		COMMON_HDR += $(SRC_COMMON)freq.h
+	endif
+
 	ifeq ($(arch), $(filter $(arch), x86_64 amd64 i386 i486 i586 i686))
 		SRC_DIR=src/x86/
 		SOURCE += $(COMMON_SRC) $(SRC_DIR)cpuid.c $(SRC_DIR)apic.c $(SRC_DIR)cpuid_asm.c $(SRC_DIR)uarch.c
 		HEADERS += $(COMMON_HDR) $(SRC_DIR)cpuid.h $(SRC_DIR)apic.h $(SRC_DIR)cpuid_asm.h $(SRC_DIR)uarch.h $(SRC_DIR)freq/freq.h
 
-                os := $(shell uname -s)
 		ifeq ($(os), Linux)
 			SOURCE += $(SRC_DIR)freq/freq.c freq_nov.o freq_avx.o freq_avx512.o
 			HEADERS += $(SRC_DIR)freq/freq.h
 			CFLAGS += -pthread
 		endif
+		ifeq ($(os), FreeBSD)
+			SOURCE += $(SRC_COMMON)sysctl.c
+			HEADERS += $(SRC_COMMON)sysctl.h
+		endif
 		CFLAGS += -DARCH_X86 -std=c99 -fstack-protector-all
 	else ifeq ($(arch), $(filter $(arch), ppc64le ppc64 ppcle ppc))
 		SRC_DIR=src/ppc/
@@ -32,14 +42,19 @@ ifneq ($(OS),Windows_NT)
 		CFLAGS += -DARCH_PPC -std=gnu99 -fstack-protector-all -Wno-language-extension-token
 	else ifeq ($(arch), $(filter $(arch), arm aarch64_be aarch64 arm64 armv8b armv8l armv7l armv6l))
 		SRC_DIR=src/arm/
-		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_DIR)udev.c
+		SOURCE += $(COMMON_SRC) $(SRC_DIR)midr.c $(SRC_DIR)uarch.c $(SRC_COMMON)soc.c $(SRC_DIR)soc.c $(SRC_COMMON)pci.c $(SRC_DIR)udev.c sve.o
-		HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h  $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
+		HEADERS += $(COMMON_HDR) $(SRC_DIR)midr.h $(SRC_DIR)uarch.h  $(SRC_COMMON)soc.h $(SRC_DIR)soc.h $(SRC_COMMON)pci.h $(SRC_DIR)udev.c $(SRC_DIR)socs.h
 		CFLAGS += -DARCH_ARM -Wno-unused-parameter -std=c99 -fstack-protector-all
 
-		os := $(shell uname -s)
+		# Check if the compiler supports -march=armv8-a+sve. We will use it (if supported) to compile SVE detection code later
+		is_sve_flag_supported := $(shell $(CC) -march=armv8-a+sve -c $(SRC_DIR)sve.c -o sve_test.o 2> /dev/null && echo 'yes'; rm -f sve_test.o)
+		ifeq ($(is_sve_flag_supported), yes)
+			SVE_FLAGS += -march=armv8-a+sve
+		endif
+
 		ifeq ($(os), Darwin)
-			SOURCE += $(SRC_DIR)sysctl.c
+			SOURCE += $(SRC_COMMON)sysctl.c
-			HEADERS += $(SRC_DIR)sysctl.h
+			HEADERS += $(SRC_COMMON)sysctl.h
 		endif
 	else ifeq ($(arch), $(filter $(arch), riscv64 riscv32))
 		SRC_DIR=src/riscv/
@@ -86,6 +101,9 @@ freq_avx.o: Makefile $(SRC_DIR)freq/freq_avx.c $(SRC_DIR)freq/freq_avx.h $(SRC_D
 freq_avx512.o: Makefile $(SRC_DIR)freq/freq_avx512.c $(SRC_DIR)freq/freq_avx512.h $(SRC_DIR)freq/freq.h
 	$(CC) $(CFLAGS) $(SANITY_FLAGS) -c -mavx512f -pthread $(SRC_DIR)freq/freq_avx512.c -o $@
 
+sve.o: Makefile $(SRC_DIR)sve.c $(SRC_DIR)sve.h
+	$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SVE_FLAGS) -c $(SRC_DIR)sve.c -o $@
+
 $(OUTPUT): Makefile $(SOURCE) $(HEADERS)
 ifeq ($(GIT_VERSION),"")
 	$(CC) $(CFLAGS) $(SANITY_FLAGS) $(SOURCE) -o $(OUTPUT)
@@ -102,9 +120,9 @@ clean:
 install: $(OUTPUT)
 	install -Dm755 "cpufetch"   "$(DESTDIR)$(PREFIX)/bin/cpufetch"
 	install -Dm644 "LICENSE"    "$(DESTDIR)$(PREFIX)/share/licenses/cpufetch-git/LICENSE"
-	install -Dm644 "cpufetch.1" "$(DESTDIR)$(PREFIX)/share/man/man1/cpufetch.1.gz"
+	install -Dm644 "cpufetch.1" "$(DESTDIR)$(PREFIX)/share/man/man1/cpufetch.1"
 
 uninstall:
 	rm -f "$(DESTDIR)$(PREFIX)/bin/cpufetch"
 	rm -f "$(DESTDIR)$(PREFIX)/share/licenses/cpufetch-git/LICENSE"
-	rm -f "$(DESTDIR)$(PREFIX)/share/man/man1/cpufetch.1.gz"
+	rm -f "$(DESTDIR)$(PREFIX)/share/man/man1/cpufetch.1"

README.md

@@ -45,6 +45,7 @@ cpufetch is a command-line tool written in C that displays the CPU information i
   - [3.1 x86_64](#31-x86_64)
   - [3.2 ARM](#32-arm)
   - [3.3 PowerPC](#33-powerpc)
+  - [3.4 RISC-V](#34-risc-v)
 - [4. Colors](#4-colors)
   - [4.1 Specifying a name](#41-specifying-a-name)
   - [4.2 Specifying the colors in RGB format](#42-specifying-the-colors-in-rgb-format)
@@ -120,6 +121,11 @@ make
 <p align="center"><img width=90% src="pictures/ibm.png"></p>
 <p align="center">Talos II</p>
 
+## 3.4 RISC-V
+
+<p align="center"><img width=80% src="pictures/starfive.png"></p>
+<p align="center">StarFive VisionFive 2</p>
+
 ## 4. Colors
 By default, `cpufetch` will print the CPU logo with the system colorscheme. However, you can set a custom color scheme in two different ways:
 
@@ -174,6 +180,8 @@ Thanks to the fellow contributors and interested people in the project. Special
 - [bbonev](https://github.com/bbonev) and [stephan-cr](https://github.com/stephan-cr): Reviewed the source code.
 - [mdoksa76](https://github.com/mdoksa76) and [exkc](https://github.com/exkc): Excellent ideas and feedback for supporting Allwinner SoCs.
 - [Sakura286](https://github.com/Sakura286), [exkc](https://github.com/exkc) and [Patola](https://github.com/Patola): Helped with RISC-V port with ssh access, ideas, testing, etc.
+- [ThomasKaiser](https://github.com/ThomasKaiser): Very valuable feedback on improving ARM SoC detection (Apple, Allwinner, Rockchip).
+- [zerkerX](https://github.com/zerkerX): Helped with feedback for supporting old (e.g., Pentium III) Intel CPUs.
 
 ## 8. cpufetch for GPUs (gpufetch)
 See [gpufetch](https://github.com/Dr-Noob/gpufetch) project!

src/arm/midr.c

@@ -8,15 +8,18 @@
 #ifdef __linux__
   #include <sys/auxv.h>
   #include <asm/hwcap.h>
+  #include "../common/freq.h"
 #elif defined __APPLE__ || __MACH__
-  #include "sysctl.h"
+  #include "../common/sysctl.h"
 #endif
 
 #include "../common/global.h"
 #include "../common/soc.h"
+#include "../common/args.h"
 #include "udev.h"
 #include "midr.h"
 #include "uarch.h"
+#include "sve.h"
 
 bool cores_are_equal(int c1pos, int c2pos, uint32_t* midr_array, int32_t* freq_array) {
   return midr_array[c1pos] == midr_array[c2pos] && freq_array[c1pos] == freq_array[c2pos];
@@ -39,8 +42,17 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
 struct frequency* get_frequency_info(uint32_t core) {
   struct frequency* freq = emalloc(sizeof(struct frequency));
 
+  freq->measured = false;
   freq->base = UNKNOWN_DATA;
   freq->max = get_max_freq_from_file(core);
+  #ifdef __linux__
+    if (freq->max == UNKNOWN_DATA || measure_max_frequency_flag()) {
+      if (freq->max == UNKNOWN_DATA)
+        printWarn("Unable to find max frequency from udev, measuring CPU frequency");
+      freq->max = measure_max_frequency(core);
+      freq->measured = true;
+    }
+  #endif
 
   return freq;
 }
@@ -157,6 +169,17 @@ struct features* get_features_info(void) {
     feat->SHA1 = hwcaps & HWCAP_SHA1;
     feat->SHA2 = hwcaps & HWCAP_SHA2;
     feat->NEON = hwcaps & HWCAP_ASIMD;
+    feat->SVE = hwcaps & HWCAP_SVE;
+
+    hwcaps = getauxval(AT_HWCAP2);
+    if (errno == ENOENT) {
+      printWarn("Unable to retrieve AT_HWCAP2 using getauxval");
+    }
+    else {
+      #ifdef HWCAP2_SVE2
+        feat->SVE2 = hwcaps & HWCAP2_SVE2;
+      #endif
+    }
   }
 #else
   else {
@@ -172,6 +195,8 @@ struct features* get_features_info(void) {
     feat->CRC32 = hwcaps & HWCAP2_CRC32;
     feat->SHA1 = hwcaps & HWCAP2_SHA1;
     feat->SHA2 = hwcaps & HWCAP2_SHA2;
+    feat->SVE = false;
+    feat->SVE2 = false;
   }
 #endif // ifdef __aarch64__
 #elif defined __APPLE__ || __MACH__
@@ -181,8 +206,14 @@ struct features* get_features_info(void) {
   feat->SHA1 = true;
   feat->SHA2 = true;
   feat->NEON = true;
+  feat->SVE = false;
+  feat->SVE2 = false;
 #endif  // ifdef __linux__
 
+  if (feat->SVE || feat->SVE2) {
+    feat->cntb = sve_cntb();
+  }
+
   return feat;
 }
 
@@ -237,7 +268,7 @@ struct cpuInfo* get_cpu_info_linux(struct cpuInfo* cpu) {
   cpu->num_cpus = sockets;
   cpu->hv = emalloc(sizeof(struct hypervisor));
   cpu->hv->present = false;
-  cpu->soc = get_soc();
+  cpu->soc = get_soc(cpu);
   cpu->peak_performance = get_peak_performance(cpu);
 
   return cpu;
@@ -289,7 +320,7 @@ void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint
   bli->feat = get_features_info();
   bli->topo = malloc(sizeof(struct topology));
   bli->topo->cach = bli->cach;
-  bli->topo->total_cores = pcores;
+  bli->topo->total_cores = ecores;
   bli->freq = malloc(sizeof(struct frequency));
   bli->freq->base = UNKNOWN_DATA;
   bli->freq->max = 2800;
@@ -305,7 +336,7 @@ void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint
   ava->feat = get_features_info();
   ava->topo = malloc(sizeof(struct topology));
   ava->topo->cach = ava->cach;
-  ava->topo->total_cores = ecores;
+  ava->topo->total_cores = pcores;
   ava->freq = malloc(sizeof(struct frequency));
   ava->freq->base = UNKNOWN_DATA;
   ava->freq->max = 3500;
@@ -314,75 +345,84 @@ void fill_cpu_info_avalanche_blizzard(struct cpuInfo* cpu, uint32_t pcores, uint
   ava->next_cpu = NULL;
 }
 
-struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
+void fill_cpu_info_everest_sawtooth(struct cpuInfo* cpu, uint32_t pcores, uint32_t ecores) {
-  uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
+  // 1. Fill SAWTOOTH
+  struct cpuInfo* saw = cpu;
 
+  saw->midr = MIDR_APPLE_M3_SAWTOOTH;
+  saw->arch = get_uarch_from_midr(saw->midr, saw);
+  saw->cach = get_cache_info(saw);
+  saw->feat = get_features_info();
+  saw->topo = malloc(sizeof(struct topology));
+  saw->topo->cach = saw->cach;
+  saw->topo->total_cores = ecores;
+  saw->freq = malloc(sizeof(struct frequency));
+  saw->freq->base = UNKNOWN_DATA;
+  saw->freq->max = 2750;
+  saw->hv = malloc(sizeof(struct hypervisor));
+  saw->hv->present = false;
+  saw->next_cpu = malloc(sizeof(struct cpuInfo));
+
+  // 2. Fill EVEREST
+  struct cpuInfo* eve = saw->next_cpu;
+  eve->midr = MIDR_APPLE_M3_EVEREST;
+  eve->arch = get_uarch_from_midr(eve->midr, eve);
+  eve->cach = get_cache_info(eve);
+  eve->feat = get_features_info();
+  eve->topo = malloc(sizeof(struct topology));
+  eve->topo->cach = eve->cach;
+  eve->topo->total_cores = pcores;
+  eve->freq = malloc(sizeof(struct frequency));
+  eve->freq->base = UNKNOWN_DATA;
+  eve->freq->max = 4050;
+  eve->hv = malloc(sizeof(struct hypervisor));
+  eve->hv->present = false;
+  eve->next_cpu = NULL;
+}
+
+struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
+  // https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_system_capabilities
+  uint32_t nperflevels = get_sys_info_by_name("hw.nperflevels");
+
+  if((cpu->num_cpus = nperflevels) != 2) {
+    printBug("Expected to find SoC with 2 perf levels, found: %d", cpu->num_cpus);
+    return NULL;
+  }
+
+  uint32_t pcores = get_sys_info_by_name("hw.perflevel0.physicalcpu");
+  uint32_t ecores = get_sys_info_by_name("hw.perflevel1.physicalcpu");
+  if(ecores <= 0) {
+    printBug("Expected to find a numer of ecores > 0, found: %d", ecores);
+    return NULL;
+  }
+  if(pcores <= 0) {
+    printBug("Expected to find a numer of pcores > 0, found: %d", pcores);
+    return NULL;
+  }
+
+  uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
   // Manually fill the cpuInfo assuming that
-  // the CPU is an Apple M1/M2
+  // the CPU is an Apple SoC
   if(cpu_family == CPUFAMILY_ARM_FIRESTORM_ICESTORM) {
-    cpu->num_cpus = 2;
+    fill_cpu_info_firestorm_icestorm(cpu, pcores, ecores);
-    // Now detect the M1 version
+    cpu->soc = get_soc(cpu);
-    uint32_t cpu_subfamily = get_sys_info_by_name("hw.cpusubfamily");
-    if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
-      // Apple M1
-      fill_cpu_info_firestorm_icestorm(cpu, 4, 4);
-    }
-    else if(cpu_subfamily == CPUSUBFAMILY_ARM_HS || cpu_subfamily == CPUSUBFAMILY_ARM_HC_HD) {
-      // Apple M1 Pro/Max/Ultra. Detect number of cores
-      uint32_t physicalcpu = get_sys_info_by_name("hw.physicalcpu");
-      if(physicalcpu == 20) {
-        // M1 Ultra
-        fill_cpu_info_firestorm_icestorm(cpu, 16, 4);
-      }
-      else if(physicalcpu == 8 || physicalcpu == 10) {
-        // M1 Pro/Max
-        fill_cpu_info_firestorm_icestorm(cpu, physicalcpu-2, 2);
-      }
-      else {
-        printBug("Found invalid physical cpu number: %d", physicalcpu);
-        return NULL;
-      }
-    }
-    else {
-      printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
-      return NULL;
-    }
-    cpu->soc = get_soc();
     cpu->peak_performance = get_peak_performance(cpu);
   }
   else if(cpu_family == CPUFAMILY_ARM_AVALANCHE_BLIZZARD) {
-    cpu->num_cpus = 2;
+    fill_cpu_info_avalanche_blizzard(cpu, pcores, ecores);
-    // Now detect the M2 version
+    cpu->soc = get_soc(cpu);
-    uint32_t cpu_subfamily = get_sys_info_by_name("hw.cpusubfamily");
+    cpu->peak_performance = get_peak_performance(cpu);
-    if(cpu_subfamily == CPUSUBFAMILY_ARM_HG) {
-      // Apple M2
-      fill_cpu_info_avalanche_blizzard(cpu, 4, 4);
   }
-    else if(cpu_subfamily == CPUSUBFAMILY_ARM_HS) {
+  else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
-      // Apple M2 Pro/Max/Ultra. Detect number of cores
+          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_2   ||
-      uint32_t physicalcpu = get_sys_info_by_name("hw.physicalcpu");
+          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
-      if(physicalcpu == 24) {
+          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
-        // M2 Ultra
+    fill_cpu_info_everest_sawtooth(cpu, pcores, ecores);
-        fill_cpu_info_avalanche_blizzard(cpu, 16, 8);
+    cpu->soc = get_soc(cpu);
-      }
-      else if(physicalcpu == 10 || physicalcpu == 12) {
-        // M2 Pro/Max
-        fill_cpu_info_avalanche_blizzard(cpu, physicalcpu-4, 4);
-      }
-      else {
-        printBug("Found invalid physical cpu number: %d", physicalcpu);
-        return NULL;
-      }
-    }
-    else {
-      printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
-      return NULL;
-    }
-    cpu->soc = get_soc();
     cpu->peak_performance = get_peak_performance(cpu);
   }
   else {
-    printBug("Found invalid cpu_family: 0x%.8X", cpu_family);
+    printBugCheckRelease("Found invalid cpu_family: 0x%.8X", cpu_family);
     return NULL;
   }
 
@@ -411,7 +451,7 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_soc
 
 char* get_str_features(struct cpuInfo* cpu) {
   struct features* feat = cpu->feat;
-  uint32_t max_len = strlen("NEON,SHA1,SHA2,AES,CRC32,") + 1;
+  uint32_t max_len = strlen("NEON,SHA1,SHA2,AES,CRC32,SVE,SVE2,") + 1;
   uint32_t len = 0;
   char* string = ecalloc(max_len, sizeof(char));
 
@@ -419,6 +459,14 @@ char* get_str_features(struct cpuInfo* cpu) {
     strcat(string, "NEON,");
     len += 5;
   }
+  if(feat->SVE) {
+    strcat(string, "SVE,");
+    len += 4;
+  }
+  if(feat->SVE2) {
+    strcat(string, "SVE2,");
+    len += 5;
+  }
   if(feat->SHA1) {
     strcat(string, "SHA1,");
     len += 5;
@@ -467,6 +515,19 @@ void print_debug(struct cpuInfo* cpu) {
       printf("%ld MHz\n", freq);
     }
   }
+
+  if (cpu->feat->SVE || cpu->feat->SVE2) {
+    printf("- cntb: %d\n", (int) cpu->feat->cntb);
+  }
+
+  #if defined(__APPLE__) || defined(__MACH__)
+    printf("hw.cpufamily: 0x%.8X\n", get_sys_info_by_name("hw.cpufamily"));
+    printf("hw.cpusubfamily: 0x%.8X\n", get_sys_info_by_name("hw.cpusubfamily"));
+    printf("hw.nperflevels: %d\n", get_sys_info_by_name("hw.nperflevels"));
+    printf("hw.physicalcpu: %d\n", get_sys_info_by_name("hw.physicalcpu"));
+    printf("hw.perflevel0.physicalcpu: %d\n", get_sys_info_by_name("hw.perflevel0.physicalcpu"));
+    printf("hw.perflevel1.physicalcpu: %d\n", get_sys_info_by_name("hw.perflevel1.physicalcpu"));
+  #endif
 }
 
 void free_topo_struct(struct topology* topo) {

src/arm/soc.c

@@ -6,16 +6,23 @@
 #include "soc.h"
 #include "socs.h"
 #include "udev.h"
+#include "uarch.h"
 #include "../common/global.h"
+#include "../common/pci.h"
 
 #if defined(__APPLE__) || defined(__MACH__)
-  #include "sysctl.h"
+  #include "../common/sysctl.h"
 #endif
 
 #define NA -1
 #define min(a,b) (((a)<(b))?(a):(b))
 #define ARRAY_SIZE(arr)     (sizeof(arr) / sizeof((arr)[0]))
 
+#define PROP_MTK_PLATFORM   "ro.mediatek.platform"
+#define PROP_SOC_MODEL      "ro.soc.model"
+#define PROP_PRODUCT_BOARD  "ro.product.board"
+#define PROP_BOARD_PLATFORM "ro.board.platform"
+
 static char* soc_rpi_string[] = {
   "BCM2835",
   "BCM2836",
@@ -26,8 +33,7 @@ static char* soc_rpi_string[] = {
 
 char* toupperstr(char* str) {
   int len = strlen(str) + 1;
-  char* ret = emalloc(sizeof(char) * len);
+  char* ret = ecalloc(len, sizeof(char));
-  memset(ret, 0, sizeof(char) * len);
 
   for(int i=0; i < len; i++) {
     ret[i] = toupper((unsigned char) str[i]);
@@ -50,6 +56,8 @@ uint32_t get_sid_from_nvmem(char* buf) {
 // SIDs list:
 // - https://linux-sunxi.org/SID_Register_Guide#Currently_known_SID.27s
 // - https://github.com/Dr-Noob/cpufetch/issues/173
+// - https://github.com/ThomasKaiser/sbc-bench/blob/master/sbc-bench.sh
+// - https://linux-sunxi.org/*CHIP_NAME*
 bool get_sunxisoc_from_sid(struct system_on_chip* soc, char* raw_name, uint32_t sid) {
   typedef struct {
     uint32_t sid;
@@ -58,21 +66,39 @@ bool get_sunxisoc_from_sid(struct system_on_chip* soc, char* raw_name, uint32_t
 
   sidToSoC socFromSid[] = {
     // --- sun8i Family ---
+    // A33
+    {0x0461872a, {SOC_ALLWINNER_A33,    SOC_VENDOR_ALLWINNER, 40, "A33",  raw_name} },
+    // A83T
+    {0x32c00401, {SOC_ALLWINNER_A83T,   SOC_VENDOR_ALLWINNER, 28, "A83T", raw_name} },
+    {0x32c00403, {SOC_ALLWINNER_A83T,   SOC_VENDOR_ALLWINNER, 28, "A83T", raw_name} },
+    // S3
+    {0x12c00001, {SOC_ALLWINNER_S3,     SOC_VENDOR_ALLWINNER, 40, "S3",   raw_name} },
     // H2+
     {0x02c00042, {SOC_ALLWINNER_H2PLUS, SOC_VENDOR_ALLWINNER, 40, "H2+",  raw_name} },
     {0x02c00142, {SOC_ALLWINNER_H2PLUS, SOC_VENDOR_ALLWINNER, 40, "H2+",  raw_name} },
+    {0x02c00242, {SOC_ALLWINNER_H2PLUS, SOC_VENDOR_ALLWINNER, 40, "H2+",  raw_name} },
     // H3
     {0x02c00181, {SOC_ALLWINNER_H3,     SOC_VENDOR_ALLWINNER, 40, "H3",   raw_name} },
     {0x02c00081, {SOC_ALLWINNER_H3,     SOC_VENDOR_ALLWINNER, 40, "H3",   raw_name} },
-    // Others
+    // R40
     {0x12c00017, {SOC_ALLWINNER_R40,    SOC_VENDOR_ALLWINNER, 40, "R40",  raw_name} },
+    // V3S
     {0x12c00000, {SOC_ALLWINNER_V3S,    SOC_VENDOR_ALLWINNER, 40, "V3s",  raw_name} }, // 40nm is only my guess, no source
     // --- sun50i Family ---
+    // H5
     {0x82800001, {SOC_ALLWINNER_H5,     SOC_VENDOR_ALLWINNER, 40, "H5",   raw_name} },
+    // H6
+    {0x82c00001, {SOC_ALLWINNER_H6,     SOC_VENDOR_ALLWINNER, 28, "H6",   raw_name} },
     {0x82c00007, {SOC_ALLWINNER_H6,     SOC_VENDOR_ALLWINNER, 28, "H6",   raw_name} },
-    {0x92c000bb, {SOC_ALLWINNER_H64,    SOC_VENDOR_ALLWINNER, 40, "H64",  raw_name} }, // Same as A64
+    // H64
+    {0x92c000bb, {SOC_ALLWINNER_H64,    SOC_VENDOR_ALLWINNER, 40, "H64",  raw_name} }, // Same manufacturing process as A64
+    // H616
     {0x32c05000, {SOC_ALLWINNER_H616,   SOC_VENDOR_ALLWINNER, 28, "H616", raw_name} },
+    // H618
+    {0x33802000, {SOC_ALLWINNER_H618,   SOC_VENDOR_ALLWINNER, 28, "H618", raw_name} },
+    // A64
     {0x92c000ba, {SOC_ALLWINNER_A64,    SOC_VENDOR_ALLWINNER, 40, "A64",  raw_name} },
+    {0x92c001ba, {SOC_ALLWINNER_A64,    SOC_VENDOR_ALLWINNER, 40, "A64",  raw_name} },
     // Unknown
     {0x00000000, {UNKNOWN,              SOC_VENDOR_UNKNOWN,   -1, "",     raw_name} }
   };
@@ -80,7 +106,7 @@ bool get_sunxisoc_from_sid(struct system_on_chip* soc, char* raw_name, uint32_t
   int index = 0;
   while(socFromSid[index].sid != 0x0) {
     if(socFromSid[index].sid == sid) {
-      fill_soc(soc, socFromSid[index].soc.soc_name, socFromSid[index].soc.soc_model, socFromSid[index].soc.process);
+      fill_soc(soc, socFromSid[index].soc.name, socFromSid[index].soc.model, socFromSid[index].soc.process);
       return true;
     }
     index++;
@@ -106,24 +132,24 @@ bool match_broadcom(char* soc_name, struct system_on_chip* soc) {
   if((tmp = strstr(soc_name, "BCM")) == NULL)
     return false;
 
-  soc->soc_vendor = SOC_VENDOR_BROADCOM;
+  soc->vendor = SOC_VENDOR_BROADCOM;
 
   SOC_START
-  SOC_EQ(tmp, "BCM2835",              "2835",              SOC_BCM_2835,   soc, 65)
+  SOC_EQ(tmp, "BCM2835",              "BCM2835",              SOC_BCM_2835,   soc, 65)
-  SOC_EQ(tmp, "BCM2836",              "2836",              SOC_BCM_2836,   soc, 40)
+  SOC_EQ(tmp, "BCM2836",              "BCM2836",              SOC_BCM_2836,   soc, 40)
-  SOC_EQ(tmp, "BCM2837",              "2837",              SOC_BCM_2837,   soc, 40)
+  SOC_EQ(tmp, "BCM2837",              "BCM2837",              SOC_BCM_2837,   soc, 40)
-  SOC_EQ(tmp, "BCM2837B0",            "2837B0",            SOC_BCM_2837B0, soc, 40)
+  SOC_EQ(tmp, "BCM2837B0",            "BCM2837B0",            SOC_BCM_2837B0, soc, 40)
-  SOC_EQ(tmp, "BCM21553",             "21553",             SOC_BCM_21553,  soc, 65)
+  SOC_EQ(tmp, "BCM21553",             "BCM21553",             SOC_BCM_21553,  soc, 65)
-  SOC_EQ(tmp, "BCM21553-Thunderbird", "21553 Thunderbird", SOC_BCM_21553T, soc, 65)
+  SOC_EQ(tmp, "BCM21553-Thunderbird", "BCM21553 Thunderbird", SOC_BCM_21553T, soc, 65)
-  SOC_EQ(tmp, "BCM21663",             "21663",             SOC_BCM_21663,  soc, 40)
+  SOC_EQ(tmp, "BCM21663",             "BCM21663",             SOC_BCM_21663,  soc, 40)
-  SOC_EQ(tmp, "BCM21664",             "21664",             SOC_BCM_21664,  soc, 40)
+  SOC_EQ(tmp, "BCM21664",             "BCM21664",             SOC_BCM_21664,  soc, 40)
-  SOC_EQ(tmp, "BCM28155",             "28155",             SOC_BCM_28155,  soc, 40)
+  SOC_EQ(tmp, "BCM28155",             "BCM28155",             SOC_BCM_28155,  soc, 40)
-  SOC_EQ(tmp, "BCM23550",             "23550",             SOC_BCM_23550,  soc, 40)
+  SOC_EQ(tmp, "BCM23550",             "BCM23550",             SOC_BCM_23550,  soc, 40)
-  SOC_EQ(tmp, "BCM28145",             "28145",             SOC_BCM_28145,  soc, 40)
+  SOC_EQ(tmp, "BCM28145",             "BCM28145",             SOC_BCM_28145,  soc, 40)
-  SOC_EQ(tmp, "BCM2157",              "2157",              SOC_BCM_2157,   soc, 65)
+  SOC_EQ(tmp, "BCM2157",              "BCM2157",              SOC_BCM_2157,   soc, 65)
-  SOC_EQ(tmp, "BCM21654",             "21654",             SOC_BCM_21654,  soc, 40)
+  SOC_EQ(tmp, "BCM21654",             "BCM21654",             SOC_BCM_21654,  soc, 40)
-  SOC_EQ(tmp, "BCM2711",              "2711",              SOC_BCM_2711,   soc, 28)
+  SOC_EQ(tmp, "BCM2711",              "BCM2711",              SOC_BCM_2711,   soc, 28)
-  SOC_EQ(tmp, "BCM2712",              "2712",              SOC_BCM_2712,   soc, 16)
+  SOC_EQ(tmp, "BCM2712",              "BCM2712",              SOC_BCM_2712,   soc, 16)
   SOC_END
 }
 
@@ -134,7 +160,7 @@ bool match_google(char* soc_name, struct system_on_chip* soc) {
   if((tmp = strstr(soc_name, "gs")) == NULL)
     return false;
 
-  soc->soc_vendor = SOC_VENDOR_GOOGLE;
+  soc->vendor = SOC_VENDOR_GOOGLE;
 
   SOC_START
   SOC_EQ(tmp, "gs101", "Tensor",    SOC_GOOGLE_TENSOR,    soc, 5)
@@ -145,13 +171,15 @@ bool match_google(char* soc_name, struct system_on_chip* soc) {
 
 // https://www.techinsights.com/
 // https://datasheetspdf.com/pdf-file/1316605/HiSilicon/Hi3660/1
+// https://github.com/Dr-Noob/cpufetch/issues/259
 bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
   char* tmp;
 
-  if((tmp = strstr(soc_name, "hi")) == NULL)
+  if((tmp = strstr(soc_name, "hi")) != NULL);
-    return false;
+  else if((tmp = strstr(soc_name, "kirin")) != NULL);
+  else return false;
 
-  soc->soc_vendor = SOC_VENDOR_KIRIN;
+  soc->vendor = SOC_VENDOR_KIRIN;
 
   SOC_START
   SOC_EQ(tmp, "hi3620GFC",  "K3V2",  SOC_HISILICON_3620, soc, 40)
@@ -182,6 +210,7 @@ bool match_hisilicon(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "hi3680",     "980",   SOC_HISILICON_3680, soc,  7)
   //SOC_EQ(tmp, "?",        "985",   SOC_KIRIN, soc,  7)
   SOC_EQ(tmp, "hi3690",     "990",   SOC_HISILICON_3690, soc,  7)
+  SOC_EQ(tmp, "kirin9000s", "9000s", SOC_HISILICON_9000S,soc,  7)
   SOC_END
 }
 
@@ -192,7 +221,7 @@ bool match_exynos(char* soc_name, struct system_on_chip* soc) {
   else if((tmp = strstr(soc_name, "exynos")) != NULL);
   else return false;
 
-  soc->soc_vendor = SOC_VENDOR_EXYNOS;
+  soc->vendor = SOC_VENDOR_EXYNOS;
 
   // Because exynos are recently using "exynosXXXX" instead
   // of "universalXXXX" as codenames, SOC_EXY_EQ will check for
@@ -252,7 +281,7 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
   if((tmp = strstr(soc_name_upper, "MT")) == NULL)
     return false;
 
-  soc->soc_vendor = SOC_VENDOR_MEDIATEK;
+  soc->vendor = SOC_VENDOR_MEDIATEK;
 
   SOC_START
   // Dimensity //
@@ -399,6 +428,9 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
 }
 
 /*
+ * Good sources:
+ * https://www.geektopia.es/es/products/company/qualcomm/socs/
+ *
  * APQ: Application Processor Qualcomm
  * MSM: Mobile Station Modem
  * In a APQXXXX or MSMXXXX, the second digit represents:
@@ -432,7 +464,7 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
   else if((tmp = strstr(soc_name_upper, "QSD")) != NULL);
   else return false;
 
-  soc->soc_vendor = SOC_VENDOR_SNAPDRAGON;
+  soc->vendor = SOC_VENDOR_SNAPDRAGON;
 
   SOC_START
   // Snapdragon S1 //
@@ -556,6 +588,25 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "SM8250-AB",      "865+",      SOC_SNAPD_SM8250_AB,      soc,  7)
   SOC_EQ(tmp, "SM8350",         "888",       SOC_SNAPD_SM8350,         soc,  5)
   SOC_EQ(tmp, "SM8350-AC",      "888+",      SOC_SNAPD_SM8350,         soc,  5)
+  // Snapdragon Gen 4 //
+  SOC_EQ(tmp, "SM4375",         "4 Gen 1",   SOC_SNAPD_SM4375,         soc,  6)
+  SOC_EQ(tmp, "SM4450",         "4 Gen 2",   SOC_SNAPD_SM4450,         soc,  4)
+  SOC_EQ(tmp, "SM4635",         "4s Gen 2",  SOC_SNAPD_SM4635,         soc,  4)
+  // Snapdragon Gen 6 //
+  SOC_EQ(tmp, "SM6375-AC",      "6s Gen 3",  SOC_SNAPD_SM6375_AC,      soc,  6)
+  SOC_EQ(tmp, "SM6450",         "6 Gen 1",   SOC_SNAPD_SM6450,         soc,  4)
+  // Snapdragon Gen 7 //
+  SOC_EQ(tmp, "SM7435-AB",      "7s Gen 2",  SOC_SNAPD_SM7435_AB,      soc,  4)
+  SOC_EQ(tmp, "SM7450",         "7 Gen 1",   SOC_SNAPD_SM7450,         soc,  4)
+  SOC_EQ(tmp, "SM7475",         "7+ Gen 2",  SOC_SNAPD_SM7475,         soc,  4)
+  SOC_EQ(tmp, "SM7550-AB",      "7 Gen 3",   SOC_SNAPD_SM7550_AB,      soc,  4)
+  SOC_EQ(tmp, "SM7675-AB",      "7+ Gen 3",  SOC_SNAPD_SM7675_AB,      soc,  4)
+  // Snapdragon Gen 8 //
+  SOC_EQ(tmp, "SM8450",         "8 Gen 1",   SOC_SNAPD_SM8450,         soc,  4)
+  SOC_EQ(tmp, "SM8475",         "8+ Gen 1",  SOC_SNAPD_SM8475,         soc,  4)
+  SOC_EQ(tmp, "SM8550-AB",      "8 Gen 2",   SOC_SNAPD_SM8550_AB,      soc,  4)
+  SOC_EQ(tmp, "SM8635",         "8s Gen 3",  SOC_SNAPD_SM8635,         soc,  4)
+  SOC_EQ(tmp, "SM8650-AB",      "8 Gen 3",   SOC_SNAPD_SM8650_AB,      soc,  4)
   SOC_END
 }
 
@@ -566,7 +617,7 @@ bool match_allwinner(char* soc_name, struct system_on_chip* soc) {
   if((tmp = strstr(soc_name, "sun")) == NULL)
     return false;
 
-  soc->soc_vendor = SOC_VENDOR_ALLWINNER;
+  soc->vendor = SOC_VENDOR_ALLWINNER;
 
   SOC_START
   // SoCs we can detect just with with the name
@@ -602,12 +653,37 @@ bool match_special(char* soc_name, struct system_on_chip* soc) {
     return true;
   }
 
-  // Snapdragon 8 Gen 1 reported as "taro"
+  // New Snapdragon SoCs codenames
+  // https://github.com/sm8450-mainline/fdt?tab=readme-ov-file#chipsets
+  // https://github.com/Dr-Noob/cpufetch/issues/253
+  if (strcmp(soc_name, "cape") == 0) {
+    fill_soc(soc, "8+ Gen 1", SOC_SNAPD_SM8475, 4);
+    return true;
+  }
+
   if(strcmp(soc_name, "taro") == 0) {
     fill_soc(soc, "8 Gen 1", SOC_SNAPD_SM8450, 4);
     return true;
   }
 
+  if(strcmp(soc_name, "ukee") == 0) {
+    fill_soc(soc, "7+ Gen 2", SOC_SNAPD_SM7475, 4);
+    return true;
+  }
+
+  if(strcmp(soc_name, "diwali") == 0) {
+    fill_soc(soc, "7 Gen 1", SOC_SNAPD_SM7450, 4);
+    return true;
+  }
+
+  // parrot can be either SM7435 or SM6450, we need more data
+  // to distingish between those two
+
+  if(strcmp(soc_name, "ravelin") == 0) {
+    fill_soc(soc, "4 Gen 2", SOC_SNAPD_SM4450, 4);
+    return true;
+  }
+
   // Google Pixel 6
   // https://github.com/Dr-Noob/cpufetch/issues/134
   if(strcmp(soc_name, "oriole") == 0) {
@@ -665,7 +741,7 @@ void try_parse_soc_from_string(struct system_on_chip* soc, int soc_len, char* so
   soc->raw_name = emalloc(sizeof(char) * (soc_len + 1));
   strncpy(soc->raw_name, soc_str, soc_len + 1);
   soc->raw_name[soc_len] = '\0';
-  soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+  soc->vendor = SOC_VENDOR_UNKNOWN;
   parse_soc_from_string(soc);
 }
 
@@ -673,24 +749,34 @@ struct system_on_chip* guess_soc_from_android(struct system_on_chip* soc) {
   char tmp[100];
   int property_len = 0;
 
-  property_len = android_property_get("ro.mediatek.platform", (char *) &tmp);
+  property_len = android_property_get(PROP_MTK_PLATFORM, (char *) &tmp);
   if(property_len > 0) {
     try_parse_soc_from_string(soc, property_len, tmp);
-    if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) printWarn("SoC detection failed using Android property ro.mediatek.platform: %s", tmp);
+    if(soc->vendor == SOC_VENDOR_UNKNOWN) printWarn("SoC detection failed using Android property %s: %s", PROP_MTK_PLATFORM, tmp);
     else return soc;
   }
 
-  property_len = android_property_get("ro.product.board", (char *) &tmp);
+  // https://github.com/Dr-Noob/cpufetch/issues/253
+  // ro.soc.model might be more reliable than ro.product.board or
+  // ro.board.platform, so try with it first
+  property_len = android_property_get(PROP_SOC_MODEL, (char *) &tmp);
   if(property_len > 0) {
     try_parse_soc_from_string(soc, property_len, tmp);
-    if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) printWarn("SoC detection failed using Android property ro.product.board: %s", tmp);
+    if(soc->vendor == SOC_VENDOR_UNKNOWN) printWarn("SoC detection failed using Android property %s: %s", PROP_SOC_MODEL, tmp);
     else return soc;
   }
 
-  property_len = android_property_get("ro.board.platform", (char *) &tmp);
+  property_len = android_property_get(PROP_PRODUCT_BOARD, (char *) &tmp);
   if(property_len > 0) {
     try_parse_soc_from_string(soc, property_len, tmp);
-    if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) printWarn("SoC detection failed using Android property ro.board.platform: %s", tmp);
+    if(soc->vendor == SOC_VENDOR_UNKNOWN) printWarn("SoC detection failed using Android property %s: %s", PROP_PRODUCT_BOARD, tmp);
+    else return soc;
+  }
+
+  property_len = android_property_get(PROP_BOARD_PLATFORM, (char *) &tmp);
+  if(property_len > 0) {
+    try_parse_soc_from_string(soc, property_len, tmp);
+    if(soc->vendor == SOC_VENDOR_UNKNOWN) printWarn("SoC detection failed using Android property %s: %s", PROP_BOARD_PLATFORM, tmp);
     else return soc;
   }
 
@@ -734,6 +820,7 @@ bool get_rk_soc_from_efuse(struct system_on_chip* soc, char* efuse) {
   rkToSoC socFromRK[] = {
     // TODO: Add RK2XXX
     // RK3XXX
+    // Reverse order
     {0x2388, {SOC_ROCKCHIP_3288,  SOC_VENDOR_ROCKCHIP, 28, "RK3288",  NULL} },
     {0x2392, {SOC_ROCKCHIP_3229,  SOC_VENDOR_ROCKCHIP, 28, "RK3229",  NULL} }, // https://gadgetversus.com/processor/rockchip-rk3229-vs-rockchip-rk3128/
     {0x3380, {SOC_ROCKCHIP_3308,  SOC_VENDOR_ROCKCHIP, 28, "RK3308",  NULL} }, // https://en.t-firefly.com/product/rocrk3308cc?theme=pc
@@ -742,10 +829,12 @@ bool get_rk_soc_from_efuse(struct system_on_chip* soc, char* efuse) {
     {0x3382, {SOC_ROCKCHIP_3328,  SOC_VENDOR_ROCKCHIP, 28, "RK3328",  NULL} },
     {0x3386, {SOC_ROCKCHIP_3368,  SOC_VENDOR_ROCKCHIP, 28, "RK3368",  NULL} },
     {0x3399, {SOC_ROCKCHIP_3399,  SOC_VENDOR_ROCKCHIP, 28, "RK3399",  NULL} },
-    {0x5366, {SOC_ROCKCHIP_3566,  SOC_VENDOR_ROCKCHIP, 22, "RK3566",  NULL} },
+    // Normal Order (https://github.com/Dr-Noob/cpufetch/issues/209)
-    {0x5386, {SOC_ROCKCHIP_3568,  SOC_VENDOR_ROCKCHIP, 22, "RK3568",  NULL} },
+    {0x3528, {SOC_ROCKCHIP_3528,  SOC_VENDOR_ROCKCHIP, 28, "RK3528",  NULL} },
-    {0x5388, {SOC_ROCKCHIP_3588,  SOC_VENDOR_ROCKCHIP,  8, "RK3588",  NULL} },
+    {0x3562, {SOC_ROCKCHIP_3562,  SOC_VENDOR_ROCKCHIP, 22, "RK3562",  NULL} },
-    {0x3588, {SOC_ROCKCHIP_3588S, SOC_VENDOR_ROCKCHIP,  8, "RK3588S", NULL} }, // https://github.com/Dr-Noob/cpufetch/issues/188
+    {0x3566, {SOC_ROCKCHIP_3566,  SOC_VENDOR_ROCKCHIP, 22, "RK3566",  NULL} },
+    {0x3568, {SOC_ROCKCHIP_3568,  SOC_VENDOR_ROCKCHIP, 22, "RK3568",  NULL} },
+    {0x3588, {SOC_ROCKCHIP_3588,  SOC_VENDOR_ROCKCHIP,  8, "RK3588",  NULL} }, // No known way to distingish between S version: https://github.com/Dr-Noob/cpufetch/issues/188,209
     // Unknown
     {0x0000, {UNKNOWN,            SOC_VENDOR_UNKNOWN,   -1,       "", NULL} }
   };
@@ -753,7 +842,7 @@ bool get_rk_soc_from_efuse(struct system_on_chip* soc, char* efuse) {
   int index = 0;
   while(socFromRK[index].rk_soc != 0x0) {
     if(socFromRK[index].rk_soc == rk_soc) {
-      fill_soc(soc, socFromRK[index].soc.soc_name, socFromRK[index].soc.soc_model, socFromRK[index].soc.process);
+      fill_soc(soc, socFromRK[index].soc.name, socFromRK[index].soc.model, socFromRK[index].soc.process);
       return true;
     }
     index++;
@@ -778,6 +867,169 @@ struct system_on_chip* guess_soc_from_nvmem(struct system_on_chip* soc) {
   return soc;
 }
 
+struct system_on_chip* guess_soc_from_uarch(struct system_on_chip* soc, struct cpuInfo* cpu) {
+  // Currently we only support CPUs with only one uarch (in other words, one socket)
+  struct uarch* arch = cpu->arch;
+  if (arch == NULL) {
+    printWarn("guess_soc_from_uarch: uarch is NULL");
+    return soc;
+  }
+
+  typedef struct {
+    MICROARCH u;
+    struct system_on_chip soc;
+  } uarchToSoC;
+
+  uarchToSoC socFromUarch[] = {
+    {UARCH_TAISHAN_V110, {SOC_KUNPENG_920,  SOC_VENDOR_KUNPENG,  7, "920", NULL} },
+    {UARCH_TAISHAN_V200, {SOC_KUNPENG_930,  SOC_VENDOR_KUNPENG,  7, "930", NULL} }, // manufacturing process is not well-known
+    {UARCH_UNKNOWN,      {UNKNOWN,          SOC_VENDOR_UNKNOWN, -1,    "", NULL} }
+  };
+
+  int index = 0;
+  while(socFromUarch[index].u != UARCH_UNKNOWN) {
+    if(socFromUarch[index].u == get_uarch(arch)) {
+      fill_soc(soc, socFromUarch[index].soc.name, socFromUarch[index].soc.model, socFromUarch[index].soc.process);
+      return soc;
+    }
+    index++;
+  }
+
+  printWarn("guess_soc_from_uarch: No uarch matched the list");
+  return soc;
+}
+
+// Return the dt string without the NULL characters.
+char* get_dt_str(char* dt, int filelen) {
+  char* dt_without_null = (char *) malloc(sizeof(char) * filelen);
+  memcpy(dt_without_null, dt, filelen);
+
+  for (int i=0; i < filelen-1; i++) {
+    if (dt_without_null[i] == '\0')
+      dt_without_null[i] = ',';
+  }
+  return dt_without_null;
+}
+
+bool match_dt(struct system_on_chip* soc, char* dt, int filelen, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
+  // The /proc/device-tree/compatible file (passed by dt) uses NULL
+  // to separate the strings, so we need to make an special case here
+  // and iterate over the NULL characters, thus iterating over each
+  // individual compatible strings.
+
+  if (strstr(dt, expected_name) != NULL) {
+    fill_soc(soc, soc_name, soc_model, process);
+    return true;
+  }
+
+  char *compatible = dt;
+  char *end_of_dt = dt + filelen;
+
+  while ((compatible = strchr(compatible, '\0')) != end_of_dt) {
+    compatible++;
+    if (strstr(compatible, expected_name) != NULL) {
+      fill_soc(soc, soc_name, soc_model, process);
+      return true;
+    }
+  }
+
+  return false;
+}
+
+#define DT_START if (false) {}
+#define DT_EQ(dt, filelen, soc, expected_name, soc_name, soc_model, process) \
+   else if (match_dt(soc, dt, filelen, expected_name, soc_name, soc_model, process)) return soc;
+#define DT_END(dt, filelen) else { printWarn("guess_soc_from_devtree: No match found for '%s'", get_dt_str(dt, filelen)); return soc; }
+
+// TODO: Move this to doc
+// The number of fields seems non-standard, so for now it seems wiser
+// to just get the entire string with all fields and just look for the
+// substring.
+// TODO: Implement this by going trough NULL-separated fields rather than
+// using strstr.
+// https://trac.gateworks.com/wiki/linux/devicetree
+struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
+  int len;
+  char* dt = get_devtree_compatible(&len);
+  if (dt == NULL) {
+    return soc;
+  }
+
+  DT_START
+  // The following are internal codenames of Asahi Linux
+  // https://github.com/AsahiLinux/docs/wiki/Codenames
+  // https://github.com/Dr-Noob/cpufetch/issues/263
+  DT_EQ(dt, len, soc, "apple,t8103", "M1",       SOC_APPLE_M1,       5)
+  DT_EQ(dt, len, soc, "apple,t6000", "M1 Pro",   SOC_APPLE_M1_PRO,   5)
+  DT_EQ(dt, len, soc, "apple,t6001", "M1 Max",   SOC_APPLE_M1_MAX,   5)
+  DT_EQ(dt, len, soc, "apple,t6002", "M1 Ultra", SOC_APPLE_M1_ULTRA, 5)
+  DT_EQ(dt, len, soc, "apple,t8112", "M2",       SOC_APPLE_M2,       5)
+  DT_EQ(dt, len, soc, "apple,t6020", "M2 Pro",   SOC_APPLE_M2_PRO,   5)
+  DT_EQ(dt, len, soc, "apple,t6021", "M2 Max",   SOC_APPLE_M2_MAX,   5)
+  DT_EQ(dt, len, soc, "apple,t6022", "M2 Ultra", SOC_APPLE_M2_ULTRA, 5)
+  DT_EQ(dt, len, soc, "apple,t8122", "M3",       SOC_APPLE_M3,       3)
+  DT_EQ(dt, len, soc, "apple,t6030", "M3 Pro",   SOC_APPLE_M3_PRO,   3)
+  DT_EQ(dt, len, soc, "apple,t6031", "M3 Max",   SOC_APPLE_M3_MAX,   3)
+  DT_EQ(dt, len, soc, "apple,t6034", "M3 Max",   SOC_APPLE_M3_MAX,   3)
+  // Qualcomm now also in devtree...
+  // TODO: Integrate this with SOC_EQ
+  DT_EQ(dt, len, soc, "qcom,sc8280", "8cx Gen 3", SOC_SNAPD_SC8280XP, 5)
+  // grep -oR -h --color -E '"fsl,.*' *.dtsi | sort | uniq | cut -d ',' -f1-2 | grep -v '-'
+  // https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/freescale    
+  DT_EQ(dt, len, soc, "fsl,imx8qm",  "i.MX 8QuadMax",   SOC_NXP_IMX8QM,  28) // https://www.nxp.com/docs/en/fact-sheet/IMX8FAMFS.pdf  
+  DT_EQ(dt, len, soc, "fsl,imx8qp",  "i.MX 8QuadPlus",  SOC_NXP_IMX8QP,  28) // Actually not in dtsi, compatible string is just a guess
+  DT_EQ(dt, len, soc, "fsl,imx8mp",  "i.MX 8M Plus",    SOC_NXP_IMX8MP,  14) // https://www.nxp.com/docs/en/fact-sheet/IMX8MPLUSFS.pdf https://github.com/Dr-Noob/cpufetch/issues/261
+  DT_EQ(dt, len, soc, "fsl,imx8mn",  "i.MX 8M Nano",    SOC_NXP_IMX8MN,  NA)
+  DT_EQ(dt, len, soc, "fsl,imx8mm",  "i.MX 8M Mini",    SOC_NXP_IMX8MM,  NA) // https://www.nxp.com/docs/en/fact-sheet/IMX8MMINIFS.pdf
+  DT_EQ(dt, len, soc, "fsl,imx8dxp", "i.MX 8DualXPlus", SOC_NXP_IMX8DXP, NA)
+  DT_EQ(dt, len, soc, "fsl,imx8qxp", "i.MX 8QuadXPlus", SOC_NXP_IMX8QXP, NA)
+  DT_EQ(dt, len, soc, "fsl,imx93",   "i.MX 93",         SOC_NXP_IMX93,   NA)  
+  // TODO: Add more Amlogic SoCs: https://elixir.bootlin.com/linux/v6.10.6/source/arch/arm64/boot/dts/amlogic
+  // https://github.com/Dr-Noob/cpufetch/issues/268
+  // https://www.amlogic.com/#Products/393/index.html
+  // https://wikimovel.com/index.php/Amlogic_A311D
+  DT_EQ(dt, len, soc, "amlogic,a311d", "A311D", SOC_AMLOGIC_A311D, 12)
+  DT_END(dt, len)
+}
+
+struct system_on_chip* guess_soc_from_pci(struct system_on_chip* soc, struct cpuInfo* cpu) {
+  struct pci_devices * pci = get_pci_devices();
+  if (pci == NULL) {
+    printWarn("guess_soc_from_pci: Unable to find suitable PCI devices");
+    return soc;
+  }
+
+  typedef struct {
+    uint16_t vendor_id;
+    uint16_t device_id;
+    struct system_on_chip soc;
+  } pciToSoC;
+
+  pciToSoC socFromPCI[] = {
+    {PCI_VENDOR_NVIDIA, PCI_DEVICE_TEGRA_X1, {SOC_TEGRA_X1,     SOC_VENDOR_NVIDIA,  20, "Tegra X1", NULL} },
+    // {PCI_VENDOR_NVIDIA, PCI_DEVICE_GH_200,{SOC_GH_200,       SOC_VENDOR_NVIDIA,   ?, "Grace Hopper", NULL} },
+    {PCI_VENDOR_AMPERE, PCI_DEVICE_ALTRA,    {SOC_AMPERE_ALTRA, SOC_VENDOR_AMPERE,   7, "Altra",    NULL} }, // https://www.anandtech.com/show/15575/amperes-altra-80-core-n1-soc-for-hyperscalers-against-rome-and-xeon
+    {0x0000,            0x0000,              {UNKNOWN,          SOC_VENDOR_UNKNOWN, -1,      "",    NULL} }
+  };
+
+  int index = 0;
+  while (socFromPCI[index].vendor_id != 0x0) {
+    for (int i=0; i < pci->num_devices; i++) {
+      struct pci_device * dev = pci->devices[i];
+
+      if (socFromPCI[index].vendor_id == dev->vendor_id &&
+          socFromPCI[index].device_id == dev->device_id) {
+        fill_soc(soc, socFromPCI[index].soc.name, socFromPCI[index].soc.model, socFromPCI[index].soc.process);
+        return soc;
+      }
+    }
+    index++;
+  }
+
+  printWarn("guess_soc_from_pci: No PCI device matched the list");
+  return soc;
+}
+
 int hex2int(char c) {
   if (c >= '0' && c <= '9')
     return c - '0';
@@ -851,12 +1103,12 @@ struct system_on_chip* guess_soc_apple(struct system_on_chip* soc) {
       }
       else {
         printBug("Found invalid physical cpu number: %d", physicalcpu);
-        soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+        soc->vendor = SOC_VENDOR_UNKNOWN;
       }
     }
     else {
-      printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
+      printBugCheckRelease("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
-      soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+      soc->vendor = SOC_VENDOR_UNKNOWN;
     }
   }
   else if(cpu_family == CPUFAMILY_ARM_AVALANCHE_BLIZZARD) {
@@ -878,34 +1130,54 @@ struct system_on_chip* guess_soc_apple(struct system_on_chip* soc) {
       }
       else {
         printBug("Found invalid physical cpu number: %d", physicalcpu);
-        soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+        soc->vendor = SOC_VENDOR_UNKNOWN;
       }
     }
     else {
-      printBug("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
+      printBugCheckRelease("Found invalid cpu_subfamily: 0x%.8X", cpu_subfamily);
-      soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+      soc->vendor = SOC_VENDOR_UNKNOWN;
+    }
+  }
+  else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
+          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_2   ||
+          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
+          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
+    // Check M3 version
+    if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
+       cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_2) {
+      fill_soc(soc, "M3", SOC_APPLE_M3, 3);
+    }
+    else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO) {
+      fill_soc(soc, "M3 Pro", SOC_APPLE_M3_PRO, 3);
+    }
+    else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
+      fill_soc(soc, "M3 Max", SOC_APPLE_M3_MAX, 3);
+    }
+    else {
+      printBugCheckRelease("Found invalid cpu_family: 0x%.8X", cpu_family);
+      soc->vendor = SOC_VENDOR_UNKNOWN;
     }
   }
   else {
-    printBug("Found invalid cpu_family: 0x%.8X", cpu_family);
+    printBugCheckRelease("Found invalid cpu_family: 0x%.8X", cpu_family);
-    soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+    soc->vendor = SOC_VENDOR_UNKNOWN;
   }
   return soc;
 }
 #endif
 
-struct system_on_chip* get_soc(void) {
+struct system_on_chip* get_soc(struct cpuInfo* cpu) {
   struct system_on_chip* soc = emalloc(sizeof(struct system_on_chip));
   soc->raw_name = NULL;
-  soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+  soc->vendor = SOC_VENDOR_UNKNOWN;
-  soc->soc_model = SOC_MODEL_UNKNOWN;
+  soc->model = SOC_MODEL_UNKNOWN;
   soc->process = UNKNOWN;
 
 #ifdef __linux__
   bool isRPi = is_raspberry_pi();
   if(isRPi) {
     soc = guess_soc_raspbery_pi(soc);
-    if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+    if(soc->vendor == SOC_VENDOR_UNKNOWN) {
       printErr("[RPi] SoC detection failed using revision code, falling back to cpuinfo detection");
     }
     else {
@@ -914,7 +1186,7 @@ struct system_on_chip* get_soc(void) {
   }
 
   soc = guess_soc_from_cpuinfo(soc);
-  if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+  if(soc->vendor == SOC_VENDOR_UNKNOWN) {
     if(soc->raw_name != NULL) {
       printWarn("SoC detection failed using /proc/cpuinfo: Found '%s' string", soc->raw_name);
     }
@@ -926,18 +1198,30 @@ struct system_on_chip* get_soc(void) {
     if(soc->raw_name == NULL) {
       printWarn("SoC detection failed using Android: No string found");
     }
-    else if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+    else if(soc->vendor == SOC_VENDOR_UNKNOWN) {
       printWarn("SoC detection failed using Android: Found '%s' string", soc->raw_name);
     }
 #endif // ifdef __ANDROID__
-    // If cpufinfo/Android (if available) detection fails, try with nvmem
+    // If previous steps failed, try with the device tree
-    if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+    if (soc->vendor == SOC_VENDOR_UNKNOWN) {
+      soc = guess_soc_from_devtree(soc);
+    }
+    // If previous steps failed, try with nvmem
+    if(soc->vendor == SOC_VENDOR_UNKNOWN) {
       soc = guess_soc_from_nvmem(soc);
     }
+    // If previous steps failed, try infering it from the microarchitecture
+    if(soc->vendor == SOC_VENDOR_UNKNOWN) {
+      soc = guess_soc_from_uarch(soc, cpu);
+    }
+    // If previous steps failed, try infering it from the pci device id
+    if(soc->vendor == SOC_VENDOR_UNKNOWN) {
+      soc = guess_soc_from_pci(soc, cpu);
+    }
   }
 #elif defined __APPLE__ || __MACH__
   soc = guess_soc_apple(soc);
-  if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+  if(soc->vendor == SOC_VENDOR_UNKNOWN) {
     printWarn("SoC detection failed using cpu_subfamily");
   }
   else {
@@ -945,7 +1229,7 @@ struct system_on_chip* get_soc(void) {
   }
 #endif // ifdef __linux__
 
-  if(soc->soc_model == SOC_MODEL_UNKNOWN) {
+  if(soc->model == SOC_MODEL_UNKNOWN) {
     // raw_name might not be NULL, but if we were unable to find
     // the exact SoC, just print "Unkwnown"
     soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));

src/arm/soc.h

@@ -5,6 +5,6 @@
 #include "../common/soc.h"
 #include <stdint.h>
 
-struct system_on_chip* get_soc(void);
+struct system_on_chip* get_soc(struct cpuInfo* cpu);
 
 #endif

src/arm/socs.h

@@ -29,6 +29,10 @@ enum {
   SOC_HISILICON_3670,
   SOC_HISILICON_3680,
   SOC_HISILICON_3690,
+  SOC_HISILICON_9000S,
+  // Kunpeng //
+  SOC_KUNPENG_920,
+  SOC_KUNPENG_930,
   // Exynos //
   SOC_EXYNOS_3475,
   SOC_EXYNOS_4210,
@@ -267,11 +271,16 @@ enum {
   SOC_SNAPD_SDM660,
   SOC_SNAPD_SM6115,
   SOC_SNAPD_SM6125,
+  SOC_SNAPD_SM6375_AC,
+  SOC_SNAPD_SM6450,
   SOC_SNAPD_SDM670,
   SOC_SNAPD_SM6150,
   SOC_SNAPD_SM6350,
   SOC_SNAPD_SDM710,
   SOC_SNAPD_SDM712,
+  SOC_SNAPD_SM4375,
+  SOC_SNAPD_SM4450,
+  SOC_SNAPD_SM4635,
   SOC_SNAPD_SM7125,
   SOC_SNAPD_SM7150_AA,
   SOC_SNAPD_SM7150_AB,
@@ -280,6 +289,11 @@ enum {
   SOC_SNAPD_SM7250_AA,
   SOC_SNAPD_SM7250_AB,
   SOC_SNAPD_SM7250_AC,
+  SOC_SNAPD_SM7435_AB,
+  SOC_SNAPD_SM7450,
+  SOC_SNAPD_SM7475,
+  SOC_SNAPD_SM7550_AB,
+  SOC_SNAPD_SM7675_AB,
   SOC_SNAPD_MSM8974AA,
   SOC_SNAPD_MSM8974AB,
   SOC_SNAPD_MSM8974AC,
@@ -300,6 +314,11 @@ enum {
   SOC_SNAPD_SM8250_AB,
   SOC_SNAPD_SM8350,
   SOC_SNAPD_SM8450,
+  SOC_SNAPD_SM8475,
+  SOC_SNAPD_SM8550_AB,
+  SOC_SNAPD_SM8635,
+  SOC_SNAPD_SM8650_AB,
+  SOC_SNAPD_SC8280XP,
   // APPLE
   SOC_APPLE_M1,
   SOC_APPLE_M1_PRO,
@@ -309,6 +328,9 @@ enum {
   SOC_APPLE_M2_PRO,
   SOC_APPLE_M2_MAX,
   SOC_APPLE_M2_ULTRA,
+  SOC_APPLE_M3,
+  SOC_APPLE_M3_PRO,
+  SOC_APPLE_M3_MAX,
   // ALLWINNER
   SOC_ALLWINNER_A10,
   SOC_ALLWINNER_A13,
@@ -326,12 +348,14 @@ enum {
   SOC_ALLWINNER_V3S,
   SOC_ALLWINNER_HZP,
   SOC_ALLWINNER_H2PLUS,
+  SOC_ALLWINNER_S3,
   SOC_ALLWINNER_H3,
   SOC_ALLWINNER_H8,
   SOC_ALLWINNER_H5,
   SOC_ALLWINNER_H6,
   SOC_ALLWINNER_H64,
   SOC_ALLWINNER_H616,
+  SOC_ALLWINNER_H618,
   SOC_ALLWINNER_R8,
   SOC_ALLWINNER_R16,
   SOC_ALLWINNER_R40,
@@ -346,28 +370,49 @@ enum {
   SOC_ROCKCHIP_3328,
   SOC_ROCKCHIP_3368,
   SOC_ROCKCHIP_3399,
+  SOC_ROCKCHIP_3528,
+  SOC_ROCKCHIP_3562,
   SOC_ROCKCHIP_3566,
   SOC_ROCKCHIP_3568,
   SOC_ROCKCHIP_3588,
-  SOC_ROCKCHIP_3588S,
   // GOOGLE
   SOC_GOOGLE_TENSOR,
   SOC_GOOGLE_TENSOR_G2,
   SOC_GOOGLE_TENSOR_G3,
+  // NVIDIA,
+  SOC_TEGRA_X1,
+  // ALTRA
+  SOC_AMPERE_ALTRA,
+  // NXP
+  SOC_NXP_IMX8QM,
+  SOC_NXP_IMX8QP,
+  SOC_NXP_IMX8MP,
+  SOC_NXP_IMX8MN,
+  SOC_NXP_IMX8MM,
+  SOC_NXP_IMX8DXP,
+  SOC_NXP_IMX8QXP,
+  SOC_NXP_IMX93,
+  // AMLOGIC
+  SOC_AMLOGIC_A311D,
   // UNKNOWN
   SOC_MODEL_UNKNOWN
 };
 
 inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
   if(soc >= SOC_BCM_2835 && soc <= SOC_BCM_2712) return SOC_VENDOR_BROADCOM;
-  else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_3690) return SOC_VENDOR_KIRIN;
+  else if(soc >= SOC_HISILICON_3620 && soc <= SOC_HISILICON_9000S) return SOC_VENDOR_KIRIN;
+  else if(soc >= SOC_KUNPENG_920 && soc <= SOC_KUNPENG_930) return SOC_VENDOR_KUNPENG;
   else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
   else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
-  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8450) return SOC_VENDOR_SNAPDRAGON;
+  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SC8280XP) return SOC_VENDOR_SNAPDRAGON;
-  else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M2_ULTRA) return SOC_VENDOR_APPLE;
+  else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE;
   else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
-  else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588S) return SOC_VENDOR_ROCKCHIP;
+  else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP;
   else if(soc >= SOC_GOOGLE_TENSOR && soc <= SOC_GOOGLE_TENSOR_G3) return SOC_VENDOR_GOOGLE;
+  else if(soc >= SOC_TEGRA_X1 && soc <= SOC_TEGRA_X1) return SOC_VENDOR_NVIDIA;
+  else if(soc >= SOC_AMPERE_ALTRA && soc <= SOC_AMPERE_ALTRA) return SOC_VENDOR_AMPERE;
+  else if(soc >= SOC_NXP_IMX8QM && soc <= SOC_NXP_IMX93) return SOC_VENDOR_NXP;
+  else if(soc >= SOC_AMLOGIC_A311D && soc <= SOC_AMLOGIC_A311D) return SOC_VENDOR_AMLOGIC;
   return SOC_VENDOR_UNKNOWN;
 }
 

src/arm/sve.c

@@ -0,0 +1,15 @@
+#include <stdint.h>
+#include "../common/global.h"
+
+// https://learn.arm.com/learning-paths/servers-and-cloud-computing/sve/sve_basics/#:~:text=Using%20a%20text%20editor%20of%20your%20choice%2C%20copy,svcntb%28%29%29%3B%20%7D%20This%20program%20prints%20the%20vector%20length
+uint64_t sve_cntb(void) {
+  #ifdef __ARM_FEATURE_SVE
+    uint64_t x0 = 0;
+    __asm volatile("cntb %0"
+         : "=r"(x0));
+    return x0;
+  #else
+    printWarn("sve_cntb: Hardware supports SVE, but it was not enabled by the compiler");
+    return 0;
+  #endif
+}

src/arm/sve.h

@@ -0,0 +1,6 @@
+#ifndef __SVE_DETECTION__
+#define __SVE_DETECTION__
+
+uint64_t sve_cntb(void);
+
+#endif

src/arm/uarch.c

@@ -10,7 +10,6 @@
 // Data not available
 #define NA                   -1
 
-typedef uint32_t MICROARCH;
 typedef uint32_t ISA;
 
 struct uarch {
@@ -34,88 +33,9 @@ enum {
   ISA_ARMv8_3_A,
   ISA_ARMv8_4_A,
   ISA_ARMv8_5_A,
-  ISA_ARMv9_A
+  ISA_ARMv8_6_A,
-};
+  ISA_ARMv9_A,
-
+  ISA_ARMv9_2_A
-enum {
-  UARCH_UNKNOWN,
-  // ARM
-  UARCH_ARM7,
-  UARCH_ARM9,
-  UARCH_ARM1136,
-  UARCH_ARM1156,
-  UARCH_ARM1176,
-  UARCH_ARM11MPCORE,
-  UARCH_CORTEX_A5,
-  UARCH_CORTEX_A7,
-  UARCH_CORTEX_A8,
-  UARCH_CORTEX_A9,
-  UARCH_CORTEX_A12,
-  UARCH_CORTEX_A15,
-  UARCH_CORTEX_A17,
-  UARCH_CORTEX_A32,
-  UARCH_CORTEX_A35,
-  UARCH_CORTEX_A53,
-  UARCH_CORTEX_A55r0, // ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+).
-  UARCH_CORTEX_A55,
-  UARCH_CORTEX_A57,
-  UARCH_CORTEX_A65,
-  UARCH_CORTEX_A72,
-  UARCH_CORTEX_A73,
-  UARCH_CORTEX_A75,
-  UARCH_CORTEX_A76,
-  UARCH_CORTEX_A77,
-  UARCH_CORTEX_A78,
-  UARCH_CORTEX_A510,
-  UARCH_CORTEX_A710,
-  UARCH_CORTEX_A715,
-  UARCH_CORTEX_X1,
-  UARCH_CORTEX_X2,
-  UARCH_CORTEX_X3,
-  UARCH_NEOVERSE_N1,
-  UARCH_NEOVERSE_E1,
-  UARCH_NEOVERSE_V1,
-  UARCH_SCORPION,
-  UARCH_KRAIT,
-  UARCH_KYRO,
-  UARCH_FALKOR,
-  UARCH_SAPHIRA,
-  UARCH_DENVER,
-  UARCH_DENVER2,
-  UARCH_CARMEL,
-  // SAMSUNG
-  UARCH_EXYNOS_M1,  // Samsung Exynos M1 (Exynos 8890 big cores)
-  UARCH_EXYNOS_M2,  // Samsung Exynos M2 (Exynos 8895 big cores)
-  UARCH_EXYNOS_M3,  // Samsung Exynos M3 (Exynos 9810 big cores)
-  UARCH_EXYNOS_M4,  // Samsung Exynos M4 (Exynos 9820 big cores)
-  UARCH_EXYNOS_M5,  // Samsung Exynos M5 (Exynos 9830 big cores)
-  // APPLE
-  UARCH_SWIFT,      // Apple A6 and A6X processors.
-  UARCH_CYCLONE,    // Apple A7 processor.
-  UARCH_TYPHOON,    // Apple A8 and A8X processor
-  UARCH_TWISTER,    // Apple A9 and A9X processor.
-  UARCH_HURRICANE,  // Apple A10 and A10X processor.
-  UARCH_MONSOON,    // Apple A11 processor (big cores).
-  UARCH_MISTRAL,    // Apple A11 processor (little cores).
-  UARCH_VORTEX,     // Apple A12 processor (big cores).
-  UARCH_TEMPEST,    // Apple A12 processor (big cores).
-  UARCH_LIGHTNING,  // Apple A13 processor (big cores).
-  UARCH_THUNDER,    // Apple A13 processor (little cores).
-  UARCH_ICESTORM,   // Apple M1 processor (little cores).
-  UARCH_FIRESTORM,  // Apple M1 processor (big cores).
-  UARCH_BLIZZARD,   // Apple M2 processor (little cores).
-  UARCH_AVALANCHE,  // Apple M2 processor (big cores).
-  // CAVIUM
-  UARCH_THUNDERX,   // Cavium ThunderX
-  UARCH_THUNDERX2,  // Cavium ThunderX2 (originally Broadcom Vulkan).
-  // MARVELL
-  UARCH_PJ4,
-  UARCH_BRAHMA_B15,
-  UARCH_BRAHMA_B53,
-  UARCH_XGENE,        // Applied Micro X-Gene.
-  UARCH_TAISHAN_V110, // HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors).
-  // PHYTIUM
-  UARCH_XIAOMI,       // Not to be confused with Xiaomi Inc
 };
 
 static const ISA isas_uarch[] = {
@@ -143,20 +63,33 @@ static const ISA isas_uarch[] = {
   [UARCH_CORTEX_A76]   = ISA_ARMv8_2_A,
   [UARCH_CORTEX_A77]   = ISA_ARMv8_2_A,
   [UARCH_CORTEX_A78]   = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A78C]  = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_A78AE] = ISA_ARMv8_2_A,
   [UARCH_CORTEX_A510]   = ISA_ARMv9_A,
+  [UARCH_CORTEX_A520]  = ISA_ARMv9_2_A,
   [UARCH_CORTEX_A710]   = ISA_ARMv9_A,
   [UARCH_CORTEX_A715]  = ISA_ARMv9_A,
+  [UARCH_CORTEX_A720]  = ISA_ARMv9_2_A,
+  [UARCH_CORTEX_A725]  = ISA_ARMv9_2_A,
   [UARCH_CORTEX_X1]    = ISA_ARMv8_2_A,
+  [UARCH_CORTEX_X1C]   = ISA_ARMv8_2_A, // Assuming same as X1
   [UARCH_CORTEX_X2]    = ISA_ARMv9_A,
   [UARCH_CORTEX_X3]    = ISA_ARMv9_A,
+  [UARCH_CORTEX_X4]    = ISA_ARMv9_2_A,
+  [UARCH_CORTEX_X925]  = ISA_ARMv9_2_A,
   [UARCH_NEOVERSE_N1]  = ISA_ARMv8_2_A,
+  [UARCH_NEOVERSE_N2]  = ISA_ARMv9_A,
   [UARCH_NEOVERSE_E1]  = ISA_ARMv8_2_A,
   [UARCH_NEOVERSE_V1]  = ISA_ARMv8_4_A,
+  [UARCH_NEOVERSE_V2]  = ISA_ARMv9_A,
+  [UARCH_NEOVERSE_V3]  = ISA_ARMv9_2_A,
   [UARCH_BRAHMA_B15]   = ISA_ARMv7_A,   // Same as Cortex-A15
   [UARCH_BRAHMA_B53]   = ISA_ARMv8_A,   // Same as Cortex-A53
   [UARCH_THUNDERX]     = ISA_ARMv8_A,
   [UARCH_THUNDERX2]    = ISA_ARMv8_1_A,
   [UARCH_TAISHAN_V110] = ISA_ARMv8_2_A,
+  [UARCH_TAISHAN_V120] = ISA_ARMv8_2_A, // Not confirmed
+  [UARCH_TAISHAN_V200] = ISA_ARMv8_2_A, // Not confirmed
   [UARCH_DENVER]       = ISA_ARMv8_A,
   [UARCH_DENVER2]      = ISA_ARMv8_A,
   [UARCH_CARMEL]       = ISA_ARMv8_A,
@@ -173,8 +106,10 @@ static const ISA isas_uarch[] = {
   [UARCH_EXYNOS_M5]    = ISA_ARMv8_2_A,
   [UARCH_ICESTORM]     = ISA_ARMv8_5_A, // https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/AArch64TargetParser.def
   [UARCH_FIRESTORM]    = ISA_ARMv8_5_A,
-  [UARCH_BLIZZARD]     = ISA_ARMv8_5_A, // Not confirmed
+  [UARCH_BLIZZARD]     = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
-  [UARCH_AVALANCHE]    = ISA_ARMv8_5_A,
+  [UARCH_AVALANCHE]    = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
+  [UARCH_SAWTOOTH]     = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
+  [UARCH_EVEREST]      = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
   [UARCH_PJ4]          = ISA_ARMv7_A,
   [UARCH_XIAOMI]       = ISA_ARMv8_A,
 };
@@ -192,14 +127,15 @@ static char* isas_string[] = {
   [ISA_ARMv8_3_A] = "ARMv8.3",
   [ISA_ARMv8_4_A] = "ARMv8.4",
   [ISA_ARMv8_5_A] = "ARMv8.5",
-  [ISA_ARMv9_A] = "ARMv9"
+  [ISA_ARMv8_6_A] = "ARMv8.6",
+  [ISA_ARMv9_A] = "ARMv9",
+  [ISA_ARMv9_2_A] = "ARMv9.2",
 };
 
 #define UARCH_START if (false) {}
 #define CHECK_UARCH(arch, cpu, im_, p_, v_, r_, str, uarch, vendor) \
    else if (im_ == im && p_ == p && (v_ == NA || v_ == v) && (r_ == NA || r_ == r)) fill_uarch(arch, cpu, str, uarch, vendor);
-#define UARCH_END else { printErr("Unknown microarchitecture detected: IM=0x%X P=0x%X V=0x%X R=0x%X", im, p, v, r); \
+#define UARCH_END else { printBugCheckRelease("Unknown microarchitecture detected: IM=0x%X P=0x%X V=0x%X R=0x%X", im, p, v, r); \
-fprintf(stderr, "Please see https://github.com/Dr-Noob/cpufetch#61-unknown-microarchitecture-error to know how to report this error\n"); \
 fill_uarch(arch, cpu, "Unknown", UARCH_UNKNOWN, CPU_VENDOR_UNKNOWN); }
 
 void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u, VENDOR vendor) {
@@ -220,6 +156,7 @@ void fill_uarch(struct uarch* arch, struct cpuInfo* cpu, char* str, MICROARCH u,
  * Other sources:
  * - https://elixir.bootlin.com/linux/latest/source/arch/arm64/include/asm/cputype.h
  * - https://elixir.bootlin.com/linux/latest/source/arch/arm/include/asm/cputype.h
+ * - https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c
  */
 struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   struct uarch* arch = emalloc(sizeof(struct uarch));
@@ -264,13 +201,24 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   CHECK_UARCH(arch, cpu, 'A', 0xD0E, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD40, NA, NA, "Neoverse V1",           UARCH_NEOVERSE_V1,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD41, NA, NA, "Cortex-A78",            UARCH_CORTEX_A78,   CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD42, NA, NA, "Cortex-A78AE",          UARCH_CORTEX_A78AE, CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD44, NA, NA, "Cortex-X1",             UARCH_CORTEX_X1,    CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD46, NA, NA, "Cortex‑A510",           UARCH_CORTEX_A510,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD47, NA, NA, "Cortex‑A710",           UARCH_CORTEX_A710,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD48, NA, NA, "Cortex-X2",             UARCH_CORTEX_X2,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD49, NA, NA, "Neoverse N2",           UARCH_NEOVERSE_N2,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD4A, NA, NA, "Neoverse E1",           UARCH_NEOVERSE_E1,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD4B, NA, NA, "Cortex-A78C",           UARCH_CORTEX_A78C,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD4C, NA, NA, "Cortex-X1C",            UARCH_CORTEX_X1C,   CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD4D, NA, NA, "Cortex-A715",           UARCH_CORTEX_A715,  CPU_VENDOR_ARM)
   CHECK_UARCH(arch, cpu, 'A', 0xD4E, NA, NA, "Cortex-X3",             UARCH_CORTEX_X3,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD4F, NA, NA, "Neoverse V2",           UARCH_NEOVERSE_V2,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD80, NA, NA, "Cortex-A520",           UARCH_CORTEX_A520,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD81, NA, NA, "Cortex-A720",           UARCH_CORTEX_A720,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD82, NA, NA, "Cortex-X4",             UARCH_CORTEX_X4,    CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD84, NA, NA, "Neoverse V3",           UARCH_NEOVERSE_V3,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD85, NA, NA, "Cortex-X925",           UARCH_CORTEX_X925,  CPU_VENDOR_ARM)
+  CHECK_UARCH(arch, cpu, 'A', 0xD87, NA, NA, "Cortex-A725",           UARCH_CORTEX_A725,  CPU_VENDOR_ARM)
 
   CHECK_UARCH(arch, cpu, 'B', 0x00F, NA, NA, "Brahma B15",            UARCH_BRAHMA_B15,   CPU_VENDOR_BROADCOM)
   CHECK_UARCH(arch, cpu, 'B', 0x100, NA, NA, "Brahma B53",            UARCH_BRAHMA_B53,   CPU_VENDOR_BROADCOM)
@@ -282,8 +230,11 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
   CHECK_UARCH(arch, cpu, 'C', 0x0A3, NA, NA, "ThunderX 81XX",         UARCH_THUNDERX,     CPU_VENDOR_CAVIUM)
   CHECK_UARCH(arch, cpu, 'C', 0x0AF, NA, NA, "ThunderX2 99XX",        UARCH_THUNDERX2,    CPU_VENDOR_CAVIUM)
 
-  CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110",          UARCH_TAISHAN_V110, CPU_VENDOR_HUAWUEI) // Kunpeng 920 series
+  CHECK_UARCH(arch, cpu, 'H', 0xD01, NA, NA, "TaiShan v110",          UARCH_TAISHAN_V110, CPU_VENDOR_HUAWEI) // Kunpeng 920 series
+  CHECK_UARCH(arch, cpu, 'H', 0xD02,  2,  2, "TaiShan v120",          UARCH_TAISHAN_V120, CPU_VENDOR_HUAWEI) // Kiring 9000S Big cores (https://github.com/Dr-Noob/cpufetch/issues/259)
+  CHECK_UARCH(arch, cpu, 'H', 0xD02, NA, NA, "TaiShan v200",          UARCH_TAISHAN_V200, CPU_VENDOR_HUAWEI) // Kunpeng 930 series (found in openeuler: https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/XQCV7NX2UKRIUWUFKRF4PO3QENCOUFR3)
   CHECK_UARCH(arch, cpu, 'H', 0xD40, NA, NA, "Cortex-A76",            UARCH_CORTEX_A76,   CPU_VENDOR_ARM)    // Kirin 980 Big/Medium cores -> Cortex-A76
+  CHECK_UARCH(arch, cpu, 'H', 0xD42, NA, NA, "TaiShan v120",          UARCH_TAISHAN_V120, CPU_VENDOR_HUAWEI) // Kiring 9000S Small Cores (https://github.com/Dr-Noob/cpufetch/issues/259)
 
   CHECK_UARCH(arch, cpu, 'N', 0x000, NA, NA, "Denver",                UARCH_DENVER,       CPU_VENDOR_NVIDIA)
   CHECK_UARCH(arch, cpu, 'N', 0x003, NA, NA, "Denver2",               UARCH_DENVER2,      CPU_VENDOR_NVIDIA)
@@ -325,8 +276,12 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
 
   CHECK_UARCH(arch, cpu, 'a', 0x022, NA, NA, "Icestorm",              UARCH_ICESTORM,     CPU_VENDOR_APPLE)
   CHECK_UARCH(arch, cpu, 'a', 0x023, NA, NA, "Firestorm",             UARCH_FIRESTORM,    CPU_VENDOR_APPLE)
+  CHECK_UARCH(arch, cpu, 'a', 0x024, NA, NA, "Icestorm",              UARCH_ICESTORM,     CPU_VENDOR_APPLE)     // https://github.com/Dr-Noob/cpufetch/issues/263
+  CHECK_UARCH(arch, cpu, 'a', 0x025, NA, NA, "Firestorm",             UARCH_FIRESTORM,    CPU_VENDOR_APPLE)     // https://github.com/Dr-Noob/cpufetch/issues/263
   CHECK_UARCH(arch, cpu, 'a', 0x030, NA, NA, "Blizzard",              UARCH_BLIZZARD,     CPU_VENDOR_APPLE)
   CHECK_UARCH(arch, cpu, 'a', 0x031, NA, NA, "Avalanche",             UARCH_AVALANCHE,    CPU_VENDOR_APPLE)
+  CHECK_UARCH(arch, cpu, 'a', 0x048, NA, NA, "Sawtooth",              UARCH_SAWTOOTH,     CPU_VENDOR_APPLE)
+  CHECK_UARCH(arch, cpu, 'a', 0x049, NA, NA, "Everest",               UARCH_EVEREST,      CPU_VENDOR_APPLE)
 
   CHECK_UARCH(arch, cpu, 'V', 0x581, NA, NA, "PJ4",                   UARCH_PJ4,          CPU_VENDOR_MARVELL)
   CHECK_UARCH(arch, cpu, 'V', 0x584, NA, NA, "PJ4B-MP",               UARCH_PJ4,          CPU_VENDOR_MARVELL)
@@ -337,14 +292,7 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
 }
 
 bool is_ARMv8_or_newer(struct cpuInfo* cpu) {
-  return cpu->arch->isa == ISA_ARMv8_A         ||
+  return cpu->arch->isa >= ISA_ARMv8_A;
-         cpu->arch->isa == ISA_ARMv8_A_AArch32 ||
-         cpu->arch->isa == ISA_ARMv8_1_A       ||
-         cpu->arch->isa == ISA_ARMv8_2_A       ||
-         cpu->arch->isa == ISA_ARMv8_3_A       ||
-         cpu->arch->isa == ISA_ARMv8_4_A       ||
-         cpu->arch->isa == ISA_ARMv8_5_A       ||
-         cpu->arch->isa == ISA_ARMv9_A;
 }
 
 bool has_fma_support(struct cpuInfo* cpu) {
@@ -357,19 +305,17 @@ int get_vpus_width(struct cpuInfo* cpu) {
   // If the CPU has NEON, width can be 64 or 128 [1].
   // In >= ARMv8, NEON are 128 bits width [2]
   // If the CPU has SVE/SVE2, width can be between 128-2048 [3],
-  // so we must check the exact width depending on
+  // so we get the exact value from cntb [4]
-  // the exact chip (Neoverse V1 uses 256b implementations.)
   //
   // [1] https://en.wikipedia.org/wiki/ARM_architecture_family#Advanced_SIMD_(Neon)
   // [2] https://developer.arm.com/documentation/102474/0100/Fundamentals-of-Armv8-Neon-technology
   // [3] https://www.anandtech.com/show/16640/arm-announces-neoverse-v1-n2-platforms-cpus-cmn700-mesh/5
+  // [4] https://developer.arm.com/documentation/ddi0596/2020-12/SVE-Instructions/CNTB--CNTD--CNTH--CNTW--Set-scalar-to-multiple-of-predicate-constraint-element-count-
 
-  MICROARCH ua = cpu->arch->uarch;
+  if (cpu->feat->SVE && cpu->feat->cntb > 0) {
-  switch(ua) {
+    return cpu->feat->cntb * 8;
-    case UARCH_NEOVERSE_V1:
+  }
-      return 256;
+  else if (cpu->feat->NEON) {
-    default:
-      if(cpu->feat->NEON) {
     if(is_ARMv8_or_newer(cpu)) {
       return 128;
     }
@@ -381,25 +327,35 @@ int get_vpus_width(struct cpuInfo* cpu) {
     return 32;
   }
 }
-}
 
 int get_number_of_vpus(struct cpuInfo* cpu) {
   MICROARCH ua = cpu->arch->uarch;
 
   switch(ua) {
+    case UARCH_CORTEX_X925: // [https://www.anandtech.com/show/21399/arm-unveils-2024-cpu-core-designs-cortex-x925-a725-and-a520-arm-v9-2-redefined-for-3nm-/2]
+      return 6;
+    case UARCH_EVEREST:     // Just a guess, needs confirmation.
     case UARCH_FIRESTORM:   // [https://dougallj.github.io/applecpu/firestorm-simd.html]
     case UARCH_AVALANCHE:   // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
     case UARCH_CORTEX_X1:   // [https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging/3]
+    case UARCH_CORTEX_X1C:  // Assuming same as X1
     case UARCH_CORTEX_X2:   // [https://www.anandtech.com/show/16693/arm-announces-mobile-armv9-cpu-microarchitectures-cortexx2-cortexa710-cortexa510/2]
     case UARCH_CORTEX_X3:   // [https://www.hwcooling.net/en/cortex-x3-the-new-fastest-arm-core-architecture-analysis: "The FPU and SIMD unit of the core still has four pipelines"]
+    case UARCH_CORTEX_X4:   // [https://www.anandtech.com/show/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive/2]: "Cortex-X4: Out-of-Order Core"
     case UARCH_NEOVERSE_V1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_v1]
+    case UARCH_NEOVERSE_V2: // [https://chipsandcheese.com/2023/09/11/hot-chips-2023-arms-neoverse-v2/]
+    case UARCH_NEOVERSE_V3: // Assuming same as V2
       return 4;
+    case UARCH_SAWTOOTH:    // Needs confirmation, rn this is the best we know: https://mastodon.social/@dougall/111118317031041336
     case UARCH_EXYNOS_M3:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
     case UARCH_EXYNOS_M4:   // [https://en.wikichip.org/wiki/samsung/microarchitectures/m4#Block_Diagram]
     case UARCH_EXYNOS_M5:   // [https://en.wikichip.org/wiki/samsung/microarchitectures/m5]
       return 3;
     case UARCH_ICESTORM:    // [https://dougallj.github.io/applecpu/icestorm-simd.html]
     case UARCH_BLIZZARD:    // [https://en.wikipedia.org/wiki/Comparison_of_ARM_processors]
+    case UARCH_TAISHAN_V110:// [https://www-file.huawei.com/-/media/corp2020/pdf/publications/huawei-research/2022/huawei-research-issue1-en.pdf]: "128-bit x 2 for single precision"
+    case UARCH_TAISHAN_V120:// Not confirmed, asssuming same as v110
+    case UARCH_TAISHAN_V200:// Not confirmed, asssuming same as v110
     case UARCH_CORTEX_A57:  // [https://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/5]
     case UARCH_CORTEX_A72:  // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]
     case UARCH_CORTEX_A73:  // [https://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2]
@@ -407,16 +363,22 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
     case UARCH_CORTEX_A76:  // [https://www.anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse/3]
     case UARCH_CORTEX_A77:  // [https://fuse.wikichip.org/news/2339/arm-unveils-cortex-a77-emphasizes-single-thread-performance]
     case UARCH_CORTEX_A78:  // [https://fuse.wikichip.org/news/3536/arm-unveils-the-cortex-a78-when-less-is-more]
+    case UARCH_CORTEX_A78C: // Assuming same as A78
+    case UARCH_CORTEX_A78AE:// Assuming same as A78
     case UARCH_EXYNOS_M1:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
     case UARCH_EXYNOS_M2:   // [https://www.anandtech.com/show/12361/samsung-exynos-m3-architecture]
     case UARCH_NEOVERSE_N1: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/neoverse_n1#Individual_Core]
+    case UARCH_NEOVERSE_N2: // [https://chipsandcheese.com/2023/08/18/arms-neoverse-n2-cortex-a710-for-servers/]
     case UARCH_CORTEX_A710: // [https://chipsandcheese.com/2023/08/11/arms-cortex-a710-winning-by-default/]: Fig in Core Overview. Table in Instruction Scheduling and Execution
     case UARCH_CORTEX_A715: // [https://www.hwcooling.net/en/arm-introduces-new-cortex-a715-core-architecture-analysis/]: "the numbers of ALU and FPU execution units themselves >
+    case UARCH_CORTEX_A720: // Assuming same as A715: https://www.anandtech.com/show/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive/3
+    case UARCH_CORTEX_A725: // Assuming same as A720
       return 2;
     case UARCH_NEOVERSE_E1: // [https://www.anandtech.com/show/13959/arm-announces-neoverse-n1-platform/5]
     // A510 is integrated as part of a Complex. Normally, each complex would incorporate two Cortex-A510 cores.
     // Each complex incorporates a single VPU with 2 ports, so for each A510 there is theoretically 1 port.
     case UARCH_CORTEX_A510: // [https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a510#Vector_Processing_Unit_.28VPU.29]
+    case UARCH_CORTEX_A520: // Assuming same as A50: https://www.anandtech.com/show/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive/4
       return 1;
     default:
       // ARMv6
@@ -431,6 +393,10 @@ char* get_str_uarch(struct cpuInfo* cpu) {
   return cpu->arch->uarch_str;
 }
 
+MICROARCH get_uarch(struct uarch* arch) {
+  return arch->uarch;
+}
+
 void free_uarch_struct(struct uarch* arch) {
   free(arch->uarch_str);
   free(arch);

src/arm/uarch.h

@@ -5,11 +5,111 @@
 
 #include "midr.h"
 
+enum {
+  UARCH_UNKNOWN,
+  // ARM
+  UARCH_ARM7,
+  UARCH_ARM9,
+  UARCH_ARM1136,
+  UARCH_ARM1156,
+  UARCH_ARM1176,
+  UARCH_ARM11MPCORE,
+  UARCH_CORTEX_A5,
+  UARCH_CORTEX_A7,
+  UARCH_CORTEX_A8,
+  UARCH_CORTEX_A9,
+  UARCH_CORTEX_A12,
+  UARCH_CORTEX_A15,
+  UARCH_CORTEX_A17,
+  UARCH_CORTEX_A32,
+  UARCH_CORTEX_A35,
+  UARCH_CORTEX_A53,
+  UARCH_CORTEX_A55r0, // ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+).
+  UARCH_CORTEX_A55,
+  UARCH_CORTEX_A57,
+  UARCH_CORTEX_A65,
+  UARCH_CORTEX_A72,
+  UARCH_CORTEX_A73,
+  UARCH_CORTEX_A75,
+  UARCH_CORTEX_A76,
+  UARCH_CORTEX_A77,
+  UARCH_CORTEX_A78,
+  UARCH_CORTEX_A78AE,
+  UARCH_CORTEX_A78C,
+  UARCH_CORTEX_A510,
+  UARCH_CORTEX_A520,
+  UARCH_CORTEX_A710,
+  UARCH_CORTEX_A715,
+  UARCH_CORTEX_A720,
+  UARCH_CORTEX_A725,
+  UARCH_CORTEX_X1,
+  UARCH_CORTEX_X1C,
+  UARCH_CORTEX_X2,
+  UARCH_CORTEX_X3,
+  UARCH_CORTEX_X4,
+  UARCH_CORTEX_X925,
+  UARCH_NEOVERSE_N1,
+  UARCH_NEOVERSE_N2,
+  UARCH_NEOVERSE_E1,
+  UARCH_NEOVERSE_V1,
+  UARCH_NEOVERSE_V2,
+  UARCH_NEOVERSE_V3,
+  UARCH_SCORPION,
+  UARCH_KRAIT,
+  UARCH_KYRO,
+  UARCH_FALKOR,
+  UARCH_SAPHIRA,
+  UARCH_DENVER,
+  UARCH_DENVER2,
+  UARCH_CARMEL,
+  // SAMSUNG
+  UARCH_EXYNOS_M1,  // Samsung Exynos M1 (Exynos 8890 big cores)
+  UARCH_EXYNOS_M2,  // Samsung Exynos M2 (Exynos 8895 big cores)
+  UARCH_EXYNOS_M3,  // Samsung Exynos M3 (Exynos 9810 big cores)
+  UARCH_EXYNOS_M4,  // Samsung Exynos M4 (Exynos 9820 big cores)
+  UARCH_EXYNOS_M5,  // Samsung Exynos M5 (Exynos 9830 big cores)
+  // APPLE
+  UARCH_SWIFT,      // Apple A6 and A6X processors.
+  UARCH_CYCLONE,    // Apple A7 processor.
+  UARCH_TYPHOON,    // Apple A8 and A8X processor
+  UARCH_TWISTER,    // Apple A9 and A9X processor.
+  UARCH_HURRICANE,  // Apple A10 and A10X processor.
+  UARCH_MONSOON,    // Apple A11 processor (big cores).
+  UARCH_MISTRAL,    // Apple A11 processor (little cores).
+  UARCH_VORTEX,     // Apple A12 processor (big cores).
+  UARCH_TEMPEST,    // Apple A12 processor (big cores).
+  UARCH_LIGHTNING,  // Apple A13 processor (big cores).
+  UARCH_THUNDER,    // Apple A13 processor (little cores).
+  UARCH_ICESTORM,   // Apple M1 processor (little cores).
+  UARCH_FIRESTORM,  // Apple M1 processor (big cores).
+  UARCH_BLIZZARD,   // Apple M2 processor (little cores).
+  UARCH_AVALANCHE,  // Apple M2 processor (big cores).
+  UARCH_SAWTOOTH,   // Apple M3 processor (little cores).
+  UARCH_EVEREST,    // Apple M3 processor (big cores).
+  // CAVIUM
+  UARCH_THUNDERX,   // Cavium ThunderX
+  UARCH_THUNDERX2,  // Cavium ThunderX2 (originally Broadcom Vulkan).
+  // MARVELL
+  UARCH_PJ4,
+  UARCH_BRAHMA_B15,
+  UARCH_BRAHMA_B53,
+  UARCH_XGENE,        // Applied Micro X-Gene.
+  // HUAWEI
+  UARCH_TAISHAN_V110, // HiSilicon TaiShan v110
+  UARCH_TAISHAN_V120, // HiSilicon TaiShan v120
+  UARCH_TAISHAN_V200, // HiSilicon TaiShan v200
+  // PHYTIUM
+  UARCH_XIAOMI,       // Not to be confused with Xiaomi Inc
+};
+
+typedef uint32_t MICROARCH;
+
 struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu);
 int get_number_of_vpus(struct cpuInfo* cpu);
 int get_vpus_width(struct cpuInfo* cpu);
 bool has_fma_support(struct cpuInfo* cpu);
 char* get_str_uarch(struct cpuInfo* cpu);
 void free_uarch_struct(struct uarch* arch);
+MICROARCH get_uarch(struct uarch* arch);
 
 #endif

src/common/args.c

@@ -28,6 +28,7 @@ struct args_struct {
   bool help_flag;
   bool raw_flag;
   bool accurate_pp;
+  bool measure_max_frequency_flag;
   bool full_cpu_name_flag;
   bool logo_long;
   bool logo_short;
@@ -50,6 +51,7 @@ const char args_chr[] = {
   /* [ARG_LOGO_INTEL_NEW]   = */ 3,
   /* [ARG_LOGO_INTEL_OLD]   = */ 4,
   /* [ARG_ACCURATE_PP]      = */ 5,
+  /* [ARG_MEASURE_MAX_FREQ] = */ 6,
   /* [ARG_DEBUG]            = */ 'd',
   /* [ARG_VERBOSE]          = */ 'v',
   /* [ARG_VERSION]          = */ 'V',
@@ -66,6 +68,7 @@ const char *args_str[] = {
   /* [ARG_LOGO_INTEL_NEW]   = */ "logo-intel-new",
   /* [ARG_LOGO_INTEL_OLD]   = */ "logo-intel-old",
   /* [ARG_ACCURATE_PP]      = */ "accurate-pp",
+  /* [ARG_MEASURE_MAX_FREQ] = */ "measure-max-freq",
   /* [ARG_DEBUG]            = */ "debug",
   /* [ARG_VERBOSE]          = */ "verbose",
   /* [ARG_VERSION]          = */ "version",
@@ -101,6 +104,10 @@ bool accurate_pp(void) {
   return args.accurate_pp;
 }
 
+bool measure_max_frequency_flag(void) {
+  return args.measure_max_frequency_flag;
+}
+
 bool show_full_cpu_name(void) {
   return args.full_cpu_name_flag;
 }
@@ -218,16 +225,23 @@ bool parse_color(char* optarg_str, struct color*** cs) {
 char* build_short_options(void) {
   const char *c = args_chr;
   int len = sizeof(args_chr) / sizeof(args_chr[0]);
-  char* str = (char *) emalloc(sizeof(char) * (len*2 + 1));
+  char* str = (char *) ecalloc(len*2 + 1, sizeof(char));
-  memset(str, 0, sizeof(char) * (len*2 + 1));
 
 #ifdef ARCH_X86
-  sprintf(str, "%c:%c:%c%c%c%c%c%c%c%c%c%c%c",
+  sprintf(str, "%c:%c:%c%c%c%c%c%c%c%c%c%c%c%c",
   c[ARG_STYLE], c[ARG_COLOR], c[ARG_HELP],
   c[ARG_RAW], c[ARG_FULLCPUNAME],
   c[ARG_LOGO_SHORT], c[ARG_LOGO_LONG],
   c[ARG_LOGO_INTEL_NEW], c[ARG_LOGO_INTEL_OLD],
-  c[ARG_ACCURATE_PP], c[ARG_DEBUG], c[ARG_VERBOSE],
+  c[ARG_ACCURATE_PP], c[ARG_MEASURE_MAX_FREQ],
+  c[ARG_DEBUG], c[ARG_VERBOSE],
+  c[ARG_VERSION]);
+#elif ARCH_ARM
+  sprintf(str, "%c:%c:%c%c%c%c%c%c%c",
+  c[ARG_STYLE], c[ARG_COLOR], c[ARG_HELP],
+  c[ARG_LOGO_SHORT], c[ARG_LOGO_LONG],
+  c[ARG_MEASURE_MAX_FREQ],
+  c[ARG_DEBUG], c[ARG_VERBOSE],
   c[ARG_VERSION]);
 #else
   sprintf(str, "%c:%c:%c%c%c%c%c%c",
@@ -270,8 +284,11 @@ bool parse_args(int argc, char* argv[]) {
     {args_str[ARG_LOGO_INTEL_NEW],   no_argument,       0, args_chr[ARG_LOGO_INTEL_NEW]   },
     {args_str[ARG_LOGO_INTEL_OLD],   no_argument,       0, args_chr[ARG_LOGO_INTEL_OLD]   },
     {args_str[ARG_ACCURATE_PP],      no_argument,       0, args_chr[ARG_ACCURATE_PP]      },
+    {args_str[ARG_MEASURE_MAX_FREQ], no_argument,       0, args_chr[ARG_MEASURE_MAX_FREQ] },
     {args_str[ARG_FULLCPUNAME],      no_argument,       0, args_chr[ARG_FULLCPUNAME]      },
     {args_str[ARG_RAW],              no_argument,       0, args_chr[ARG_RAW]              },
+#elif ARCH_ARM
+    {args_str[ARG_MEASURE_MAX_FREQ], no_argument,       0, args_chr[ARG_MEASURE_MAX_FREQ] },
 #endif
     {args_str[ARG_LOGO_SHORT],       no_argument,       0, args_chr[ARG_LOGO_SHORT]       },
     {args_str[ARG_LOGO_LONG],        no_argument,       0, args_chr[ARG_LOGO_LONG]        },
@@ -313,6 +330,9 @@ bool parse_args(int argc, char* argv[]) {
     else if(opt == args_chr[ARG_ACCURATE_PP]) {
        args.accurate_pp = true;
     }
+    else if(opt == args_chr[ARG_MEASURE_MAX_FREQ]) {
+       args.measure_max_frequency_flag = true;
+    }
     else if(opt == args_chr[ARG_FULLCPUNAME]) {
        args.full_cpu_name_flag = true;
     }

src/common/args.h

@@ -29,6 +29,7 @@ enum {
   ARG_LOGO_INTEL_NEW,
   ARG_LOGO_INTEL_OLD,
   ARG_ACCURATE_PP,
+  ARG_MEASURE_MAX_FREQ,
   ARG_DEBUG,
   ARG_VERBOSE,
   ARG_VERSION
@@ -43,6 +44,7 @@ int max_arg_str_length(void);
 bool parse_args(int argc, char* argv[]);
 bool show_help(void);
 bool accurate_pp(void);
+bool measure_max_frequency_flag(void);
 bool show_full_cpu_name(void);
 bool show_logo_long(void);
 bool show_logo_short(void);

src/common/ascii.h

@@ -105,6 +105,19 @@ $C1  MMM  :MMM      NMM  dMMK   dMMX            MMN   \
 $C1  MMM  :MMM      NMM  dMMMoo  OMM0....:Nx.   MMN   \
 $C1  MMM  :WWW      XWW   lONMM   'xXMMMMNOc    MMN   "
 
+#define ASCII_HYGON \
+"$C1                                                   \
+$C1                                                   \
+$C1                                                   \
+$C1 ##    ##  ##    ##  ######     ######    ##    #  \
+$C1 ##....##   ##  ##  ##        ##      ##  ####  #  \
+$C1 ########     ##    ##    ##. ##      ##  #  ####  \
+$C1 ##    ##     ##    *######.    ######    #    ##  \
+$C1                                                   \
+$C1                                                   \
+$C1                                                   \
+$C1                                                   "
+
 #define ASCII_SNAPD \
 "              $C1@@$C2########               \
            $C1@@@@@$C2###########            \
@@ -145,6 +158,25 @@ $C2     Exynos           \
 $C2                      \
 $C2                      "
 
+#define ASCII_KUNPENG \
+"$C2                                             .  \
+$C2                                          ..    \
+$C2                                       .##      \
+$C1                                 .$CR  $C2.###.       \
+$C1                            ..$CR   $C2#####.         \
+$C1                       .#.$CR   $C2.#######.          \
+$C1                 .####.$CR   $C2.#######.             \
+$C1           ..######*$CR  $C2.#######.   .             \
+$C1      .#########*$CR  $C2.#######*   .                \
+$C1      ######*$CR  $C2.#######.   .#.                  \
+$C1*#######*$CR   $C2.#######.   *##.                    \
+$C1    ##*$CR $C2.#######.   #######                     \
+$C2          ###.$CR $C1#####$C2   *###                     \
+$C1              *##########                       \
+$C1                    *########                   \
+$C1                          #####.                \
+$C1                             *###.              "
+
 #define ASCII_KIRIN \
 "$C1                                #######              \
 $C1    #####             ####################           \
@@ -341,6 +373,66 @@ $C1##########@@@@@@@@@@@@@@@@############## \
 $C1######################################## \
 $C1  ####################################   "
 
+#define ASCII_NVIDIA \
+"$C1               'cccccccccccccccccccccccccc   \
+$C1               ;oooooooooooooooooooooooool   \
+$C1           .:::.     .oooooooooooooooooool   \
+$C1      .:cll;   ,c:::.     cooooooooooooool   \
+$C1   ,clo'      ;.   oolc:     ooooooooooool   \
+$C1.cloo    ;cclo .      .olc.    coooooooool   \
+$C1oooo   :lo,    ;ll;    looc    :oooooooool   \
+$C1 oooc   ool.   ;oooc;clol    :looooooooool   \
+$C1  :ooc   ,ol;  ;oooooo.   .cloo;     loool   \
+$C1    ool;   .olc.       ,:lool        .lool   \
+$C1      ool:.    ,::::ccloo.        :clooool   \
+$C1         oolc::.            ':cclooooooool   \
+$C1               ;oooooooooooooooooooooooool   \
+$C1                                             \
+$C1                                             \
+$C2######.  ##   ##  ##  ######   ##    ###     \
+$C2##   ##  ##   ##  ##  ##   ##  ##   #: :#    \
+$C2##   ##   ## ##   ##  ##   ##  ##  #######   \
+$C2##   ##    ###    ##  ######   ## ##     ##  "
+
+#define ASCII_AMPERE \
+"$C1                                                  \
+$C1                                                  \
+$C1                             ##                   \
+$C1                            ####                  \
+$C1                           ### ##                 \
+$C1                          ###   ###               \
+$C1                         ###     ###              \
+$C1                        ###        ###            \
+$C1                       ##           ###           \
+$C1                 #######   ###       ###          \
+$C1            ######  ##        ######   ###        \
+$C1        ####      ###              ########       \
+$C1      ####       ###                    ####      \
+$C1    ###         ###                       ####    \
+$C1  ##           ###                          ###   \
+$C1                                                  \
+$C1                                                  "
+
+#define ASCII_NXP \
+"$C1#####          # $C2#######      ####### $C3##########       \
+$C1#######        ## $C2#######    ####### $C3###############   \
+$C1##########     #### $C2######  ######  $C3###        ######  \
+$C1############   ##### $C2############ $C3#####         #####  \
+$C1#####  ####### #####  $C2########## $C3###################   \
+$C1#####     ######### $C2############## $C3###############     \
+$C1#####       ###### $C2######    ###### $C3####               \
+$C1#####         ## $C2######        ###### $C3##               "
+
+#define ASCII_AMLOGIC \
+"$C1      .#####.             ###                  ###        \
+$C1     ########             ###                             \
+$C1    ####..###  ########## ###   ###     #####  ###   ###  \
+$C1  .## #.  ###  ##  ##  ## ### ##   ## ##   ##  ### ##     \
+$C1 #### #.# ###  ##  ##  ## ### ##   ## ##   ##  ### ##     \
+$C1#########.###  ##  ##  ##  ##   ###    ######   ##   ###  \
+$C1                                          ###             \
+$C1                                       ###                "
+
 // --------------------- LONG LOGOS ------------------------- //
 #define ASCII_AMD_L \
 "$C1                                                              \
@@ -473,6 +565,23 @@ $C1        ###########. ############                 \
 $C1            ################                      \
 $C1                 #######                          "
 
+#define ASCII_NVIDIA_L \
+"$C1                  MMMMMMMMMMMMMMMMMMMMMMMMMMMMMM  \
+$C1                  MMMMMMMMMMMMMMMMMMMMMMMMMMMMMM  \
+$C1                .::   'MMMMMMMMMMMMMMMMMMMMMMMMM  \
+$C1           ccllooo;:;.       ;MMMMMMMMMMMMMMMMMM  \
+$C1       cloc       :ooollcc:     :MMMMMMMMMMMMMMM  \
+$C1    cloc      :ccl;      lolc,     ;MMMMMMMMMMMM  \
+$C1.cloo:    :clo    ;c:      .ool;     MMMMMMMMMMM  \
+$C1  ooo:    ooo     :ool,  .cloo.    ;lMMMMMMMMMMM  \
+$C1   ooo:    ooc    :ooooccooo.    :MMMM  lMMMMMMM  \
+$C1     ooc.   ool:  :oooooo'    ,cloo.        MMMM  \
+$C1      ool:.    olc:       .:cloo.          :MMMM  \
+$C1         olc,     ;:::cccloo.          :MMMMMMMM  \
+$C1            olcc::;              ,:ccloMMMMMMMMM  \
+$C1                  :......oMMMMMMMMMMMMMMMMMMMMMM  \
+$C1                  :lllMMMMMMMMMMMMMMMMMMMMMMMMMM  "
+
 typedef struct ascii_logo asciiL;
 
 //                        +-----------------------------------------------------------------------------------------------------------------+
@@ -481,10 +590,12 @@ typedef struct ascii_logo asciiL;
 asciiL logo_amd         = { ASCII_AMD,         39, 15, false, {C_FG_WHITE, C_FG_GREEN},                       {C_FG_WHITE,   C_FG_GREEN}   };
 asciiL logo_intel       = { ASCII_INTEL,       48, 14, false, {C_FG_CYAN},                                    {C_FG_CYAN,    C_FG_WHITE}   };
 asciiL logo_intel_new   = { ASCII_INTEL_NEW,   51,  9, false, {C_FG_CYAN},                                    {C_FG_CYAN,    C_FG_WHITE}   };
+asciiL logo_hygon       = { ASCII_HYGON,       51, 11, false, {C_FG_RED},                                     {C_FG_RED,     C_FG_WHITE}   };
 asciiL logo_snapd       = { ASCII_SNAPD,       39, 16, false, {C_FG_RED, C_FG_WHITE},                         {C_FG_RED,     C_FG_WHITE}   };
 asciiL logo_mtk         = { ASCII_MTK,         59,  5, false, {C_FG_BLUE, C_FG_YELLOW},                       {C_FG_BLUE,    C_FG_YELLOW}  };
 asciiL logo_exynos      = { ASCII_EXYNOS,      22, 13, true,  {C_BG_BLUE, C_FG_WHITE},                        {C_FG_BLUE,    C_FG_WHITE}   };
 asciiL logo_kirin       = { ASCII_KIRIN,       53, 12, false, {C_FG_RED},                                     {C_FG_WHITE,   C_FG_RED}     };
+asciiL logo_kunpeng     = { ASCII_KUNPENG,     48, 17, false, {C_FG_RED, C_FG_WHITE},                         {C_FG_WHITE,   C_FG_RED}     };
 asciiL logo_broadcom    = { ASCII_BROADCOM,    44, 19, false, {C_FG_WHITE, C_FG_RED},                         {C_FG_WHITE,   C_FG_RED}     };
 asciiL logo_arm         = { ASCII_ARM,         42,  5, false, {C_FG_CYAN},                                    {C_FG_WHITE,   C_FG_CYAN}    };
 asciiL logo_ibm         = { ASCII_IBM,         42,  9, false, {C_FG_CYAN, C_FG_WHITE},                        {C_FG_CYAN,    C_FG_WHITE}   };
@@ -496,6 +607,10 @@ asciiL logo_riscv       = { ASCII_RISCV,       63, 18, false, {C_FG_CYAN, C_FG_Y
 asciiL logo_sifive      = { ASCII_SIFIVE,      48, 19, true,  {C_BG_WHITE, C_BG_BLACK},                       {C_FG_WHITE,   C_FG_BLUE}    };
 asciiL logo_starfive    = { ASCII_STARFIVE,    33, 17, false, {C_FG_WHITE},                                   {C_FG_WHITE,   C_FG_BLUE}    };
 asciiL logo_sipeed      = { ASCII_SIPEED,      41, 16, true,  {C_BG_RED, C_BG_WHITE},                         {C_FG_RED,     C_FG_WHITE}   };
+asciiL logo_nvidia      = { ASCII_NVIDIA,      45, 19, false, {C_FG_GREEN, C_FG_WHITE},                       {C_FG_WHITE,   C_FG_GREEN}   };
+asciiL logo_ampere      = { ASCII_AMPERE,      50, 17, false, {C_FG_RED},                                     {C_FG_WHITE,   C_FG_RED}     };
+asciiL logo_nxp         = { ASCII_NXP,         55,  8, false, {C_FG_YELLOW, C_FG_CYAN, C_FG_GREEN},           {C_FG_CYAN,    C_FG_WHITE}   };
+asciiL logo_amlogic     = { ASCII_AMLOGIC,     58,  8, false, {C_FG_BLUE},                                    {C_FG_BLUE,    C_FG_B_WHITE} };
 
 // Long variants          | ----------------------------------------------------------------------------------------------------------------|
 asciiL logo_amd_l       = { ASCII_AMD_L,       62, 19, true,  {C_BG_WHITE, C_BG_GREEN},                       {C_FG_WHITE, C_FG_GREEN}     };
@@ -505,6 +620,7 @@ asciiL logo_arm_l       = { ASCII_ARM_L,       60,  8, true,  {C_BG_CYAN},
 asciiL logo_ibm_l       = { ASCII_IBM_L,       62, 13, true,  {C_BG_CYAN, C_FG_WHITE},                        {C_FG_CYAN,  C_FG_WHITE}     };
 asciiL logo_starfive_l  = { ASCII_STARFIVE_L,  50, 22, false, {C_FG_WHITE},                                   {C_FG_WHITE, C_FG_BLUE}      };
 asciiL logo_sifive_l    = { ASCII_SIFIVE_L,    53, 21, true,  {C_BG_WHITE, C_BG_BLACK},                       {C_FG_WHITE, C_FG_CYAN}      };
+asciiL logo_nvidia_l    = { ASCII_NVIDIA_L,    50, 15, false, {C_FG_GREEN, C_FG_WHITE},                       {C_FG_WHITE, C_FG_GREEN}     };
 asciiL logo_unknown     = { NULL,               0,  0, false, {COLOR_NONE},                                   {COLOR_NONE, COLOR_NONE}     };
 
 #endif

src/common/cpu.c

@@ -145,17 +145,25 @@ char* get_str_l3(struct cache* cach) {
 
 char* get_str_freq(struct frequency* freq) {
   //Max 3 digits and 3 for '(M/G)Hz' plus 1 for '\0'
-  uint32_t size = (5+1+3+1);
+  uint32_t size = (1+5+1+3+1);
   assert(strlen(STRING_UNKNOWN)+1 <= size);
-  char* string = emalloc(sizeof(char)*size);
+  char* string = ecalloc(size, sizeof(char));
-  memset(string, 0, sizeof(char)*size);
 
-  if(freq->max == UNKNOWN_DATA || freq->max < 0)
+  if(freq->max == UNKNOWN_DATA || freq->max < 0) {
     snprintf(string,strlen(STRING_UNKNOWN)+1,STRING_UNKNOWN);
-  else if(freq->max >= 1000)
+  }
+  else if(freq->max >= 1000) {
+    if (freq->measured)
+      snprintf(string,size,"~%.3f "STRING_GIGAHERZ,(float)(freq->max)/1000);
+    else
       snprintf(string,size,"%.3f "STRING_GIGAHERZ,(float)(freq->max)/1000);
+  }
+  else {
+    if (freq->measured)
+      snprintf(string,size,"~%d "STRING_MEGAHERZ,freq->max);
     else
       snprintf(string,size,"%d "STRING_MEGAHERZ,freq->max);
+  }
 
   return string;
 }

src/common/cpu.h

@@ -8,6 +8,7 @@ enum {
 // ARCH_X86
   CPU_VENDOR_INTEL,
   CPU_VENDOR_AMD,
+  CPU_VENDOR_HYGON,
 // ARCH_ARM
   CPU_VENDOR_ARM,
   CPU_VENDOR_APPLE,
@@ -16,7 +17,7 @@ enum {
   CPU_VENDOR_NVIDIA,
   CPU_VENDOR_APM,
   CPU_VENDOR_QUALCOMM,
-  CPU_VENDOR_HUAWUEI,
+  CPU_VENDOR_HUAWEI,
   CPU_VENDOR_SAMSUNG,
   CPU_VENDOR_MARVELL,
   CPU_VENDOR_PHYTIUM,
@@ -32,12 +33,14 @@ enum {
 enum {
   HV_VENDOR_KVM,
   HV_VENDOR_QEMU,
+  HV_VENDOR_VBOX,
   HV_VENDOR_HYPERV,
   HV_VENDOR_VMWARE,
   HV_VENDOR_XEN,
   HV_VENDOR_PARALLELS,
   HV_VENDOR_PHYP,
   HV_VENDOR_BHYVE,
+  HV_VENDOR_APPLEVZ,
   HV_VENDOR_INVALID
 };
 
@@ -55,6 +58,8 @@ typedef int32_t VENDOR;
 struct frequency {
   int32_t base;
   int32_t max;
+  // Indicates if max frequency was measured
+  bool measured;
 };
 
 struct hypervisor {
@@ -119,6 +124,9 @@ struct features {
   bool SHA1;
   bool SHA2;
   bool CRC32;
+  bool SVE;
+  bool SVE2;
+  uint64_t cntb;
 #endif  
 };
 

src/common/freq.c

@@ -0,0 +1,195 @@
+#ifdef __linux__
+
+#define _GNU_SOURCE
+
+#include <time.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <errno.h>
+#include <unistd.h>
+#include <asm/unistd.h>
+#include <sys/ioctl.h>
+#include <linux/perf_event.h>
+
+#include "global.h"
+#include "cpu.h"
+
+static long
+perf_event_open(struct perf_event_attr *hw_event, pid_t pid,
+                int cpu, int group_fd, unsigned long flags) {
+    int ret;
+    ret = syscall(__NR_perf_event_open, hw_event, pid, cpu,
+                    group_fd, flags);
+    return ret;
+}
+
+#define INSERT_ASM_ONCE __asm volatile("nop");
+#define INSERT_ASM_10_TIMES \
+    INSERT_ASM_ONCE         \
+    INSERT_ASM_ONCE         \
+    INSERT_ASM_ONCE         \
+    INSERT_ASM_ONCE         \
+    INSERT_ASM_ONCE         \
+    INSERT_ASM_ONCE         \
+    INSERT_ASM_ONCE         \
+    INSERT_ASM_ONCE         \
+    INSERT_ASM_ONCE         \
+    INSERT_ASM_ONCE         \
+
+#define INSERT_ASM_100_TIMES \
+    INSERT_ASM_10_TIMES      \
+    INSERT_ASM_10_TIMES      \
+    INSERT_ASM_10_TIMES      \
+    INSERT_ASM_10_TIMES      \
+    INSERT_ASM_10_TIMES      \
+    INSERT_ASM_10_TIMES      \
+    INSERT_ASM_10_TIMES      \
+    INSERT_ASM_10_TIMES      \
+    INSERT_ASM_10_TIMES      \
+    INSERT_ASM_10_TIMES
+
+#define INSERT_ASM_1000_TIMES \
+    INSERT_ASM_100_TIMES     \
+    INSERT_ASM_100_TIMES     \
+    INSERT_ASM_100_TIMES     \
+    INSERT_ASM_100_TIMES     \
+    INSERT_ASM_100_TIMES     \
+    INSERT_ASM_100_TIMES     \
+    INSERT_ASM_100_TIMES     \
+    INSERT_ASM_100_TIMES     \
+    INSERT_ASM_100_TIMES     \
+    INSERT_ASM_100_TIMES     \
+
+void nop_function(uint64_t iters) {
+  for (uint64_t i = 0; i < iters; i++) {
+    INSERT_ASM_1000_TIMES
+    INSERT_ASM_1000_TIMES
+    INSERT_ASM_1000_TIMES
+    INSERT_ASM_1000_TIMES
+  }
+}
+
+// Run the nop_function with the number of iterations specified and
+// measure both the time and number of cycles
+int measure_freq_iters(uint64_t iters, uint32_t core, double* freq) {
+  clockid_t clock = CLOCK_PROCESS_CPUTIME_ID;
+  struct timespec start, end;
+  struct perf_event_attr pe;
+  uint64_t cycles;
+  int fd;
+  int pid = 0;
+  memset(&pe, 0, sizeof(struct perf_event_attr));
+  pe.type = PERF_TYPE_HARDWARE;
+  pe.size = sizeof(struct perf_event_attr);
+  pe.config = PERF_COUNT_HW_CPU_CYCLES;
+  pe.disabled = 1;
+  pe.exclude_kernel = 1;
+  pe.exclude_hv = 1;
+
+  fd = perf_event_open(&pe, pid, core, -1, 0);
+  if (fd == -1) {
+    perror("perf_event_open");
+    if (errno == EPERM || errno == EACCES) {
+      printErr("You may not have permission to collect stats.\n"\
+      "Consider tweaking /proc/sys/kernel/perf_event_paranoid or running as root");
+    }
+    return -1;
+  }
+
+  if (clock_gettime(clock, &start) == -1) {
+    perror("clock_gettime");
+    return -1;
+  }
+  if(ioctl(fd, PERF_EVENT_IOC_RESET, 0) == -1) {
+    perror("ioctl");
+    return -1;
+  }
+  if(ioctl(fd, PERF_EVENT_IOC_ENABLE, 0) == -1) {
+    perror("ioctl");
+    return -1;
+  }
+
+  nop_function(iters);
+
+  ssize_t ret = read(fd, &cycles, sizeof(uint64_t));
+  if (ret == -1) {
+    perror("read");
+    return -1;
+  }
+  if (ret != sizeof(uint64_t)) {
+    printErr("Read returned %d, expected %d", ret, sizeof(uint64_t));
+    return -1;
+  }
+  if(ioctl(fd, PERF_EVENT_IOC_DISABLE, 0) == -1) {
+    perror("ioctl");
+    return -1;
+  }
+  if (clock_gettime(clock, &end) == -1) {
+    perror("clock_gettime");
+    return -1;
+  }
+
+  uint64_t nsecs = (end.tv_sec*1e9 + end.tv_nsec) - (start.tv_sec*1e9 + start.tv_nsec);
+  uint64_t usecs = nsecs/1000;  
+  *freq = cycles/((double)usecs);
+  return 0;
+}
+
+// Return a good number of iterations to run the nop_function in
+// order to get a precise measurement of the frequency without taking
+// too much time.
+uint64_t get_num_iters_from_freq(double frequency) {
+  // Truncate to reduce variability
+  uint64_t freq_trunc = ((uint64_t) frequency / 100) * 100;
+  uint64_t osp_per_iter = 4 * 1000;
+
+  return freq_trunc * 1e7 * 1/osp_per_iter;
+}
+
+// Differences between x86 measure_frequency and this measure_max_frequency:
+// - measure_frequency employs all cores simultaneously whereas
+//   measure_max_frequency only employs 1.
+// - measure_frequency runs the computation and checks /proc/cpuinfo whereas
+//   measure_max_frequency does not rely on /proc/cpuinfo and simply
+//   counts cpu cycles to measure frequency.
+// - measure_frequency uses actual computation while measuring the frequency
+//   whereas measure_max_frequency uses nop instructions. This makes the former
+//   x86 dependant whereas the latter is architecture independant.
+int64_t measure_max_frequency(uint32_t core) {
+  if (!bind_to_cpu(core)) {
+    printErr("Failed binding the process to CPU %d", core);
+    return UNKNOWN_DATA;
+  }
+
+  // First, get very rough estimation of clock cycle to
+  // compute a reasonable value for the iterations
+  double estimation_freq, frequency;
+  uint64_t iters = 100000;
+  if (measure_freq_iters(iters, core, &estimation_freq) == -1)
+    return UNKNOWN_DATA;
+
+  if (estimation_freq <= 0.0) {
+    printErr("First frequency measurement yielded an invalid value: %f", estimation_freq);
+    return UNKNOWN_DATA;
+  }
+  iters = get_num_iters_from_freq(estimation_freq);
+  printWarn("Running frequency measurement with %ld iterations on core %d...", iters, core);
+
+  // Now perform actual measurement
+  const char* frequency_banner = "cpufetch is measuring the max frequency...";
+  printf("%s", frequency_banner);
+  fflush(stdout);
+
+  if (measure_freq_iters(iters, core, &frequency) == -1)
+    return UNKNOWN_DATA;
+  
+  // Clean screen once measurement is finished
+  printf("\r%*c\r", (int) strlen(frequency_banner), ' ');
+  
+  // Discard last digit in the frequency, which should help providing
+  // more reliable and predictable values.
+  return (((int) frequency + 5)/10) * 10;
+}
+
+#endif // #ifdef __linux__

src/common/freq.h

@@ -0,0 +1,6 @@
+#ifndef __COMMON_FREQ__
+#define __COMMON_FREQ__
+
+int64_t measure_max_frequency(uint32_t core);
+
+#endif

src/common/global.c

@@ -1,3 +1,14 @@
+#ifdef _WIN32
+  #define NOMINMAX
+  #include <windows.h>
+#elif defined __linux__
+  #define _GNU_SOURCE
+  #include <sched.h>
+#elif defined __FreeBSD__
+  #include <sys/param.h>
+  #include <sys/cpuset.h>
+#endif
+
 #include <stdarg.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -21,7 +32,7 @@
 #endif
 
 #ifdef ARCH_X86
-  static const char* ARCH_STR = "x86_64 build";
+  static const char* ARCH_STR = "x86 / x86_64 build";
   #include "../x86/cpuid.h"
 #elif ARCH_PPC
   static const char* ARCH_STR = "PowerPC build";
@@ -51,7 +62,7 @@
 #endif
 
 #ifndef GIT_FULL_VERSION
-  static const char* VERSION = "1.04";
+  static const char* VERSION = "1.06";
 #endif
 
 enum {
@@ -61,6 +72,14 @@ enum {
 
 int LOG_LEVEL;
 
+void printBugMessage(FILE *restrict stream) {
+  #if defined(ARCH_X86) || defined(ARCH_PPC)
+    fprintf(stream, "Please, create a new issue with this error message, the output of 'cpufetch' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
+  #elif ARCH_ARM
+    fprintf(stream, "Please, create a new issue with this error message, your smartphone/computer model, the output of 'cpufetch --verbose' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
+  #endif
+}
+
 void printWarn(const char *fmt, ...) {
   if(LOG_LEVEL == LOG_LEVEL_VERBOSE) {
     int buffer_size = 4096;
@@ -95,10 +114,40 @@ void printBug(const char *fmt, ...) {
   fprintf(stderr,RED "[ERROR]: "RESET "%s\n",buffer);
   fprintf(stderr,"[VERSION]: ");
   print_version(stderr);
-#if defined(ARCH_X86) || defined(ARCH_PPC)
+  printBugMessage(stderr);
-  fprintf(stderr, "Please, create a new issue with this error message, the output of 'cpufetch' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
+}
-#elif ARCH_ARM
+
-  fprintf(stderr, "Please, create a new issue with this error message, your smartphone/computer model, the output of 'cpufetch --verbose' and 'cpufetch --debug' on https://github.com/Dr-Noob/cpufetch/issues\n");
+bool isReleaseVersion(char *git_full_version) {
+  return strstr(git_full_version, "-") == NULL;
+}
+
+/// The unknown uarch errors are by far the most common error a user will encounter.
+/// Rather than using the generic printBug function, which asks the user to report
+/// the problem on the issues webpage, this function will check if the program is
+/// the release version. In such case, support for this feature is most likely already
+/// in the last version, so just tell the user to compile that one and not report this
+/// in github.
+void printBugCheckRelease(const char *fmt, ...) {
+  int buffer_size = 4096;
+  char buffer[buffer_size];
+  va_list args;
+  va_start(args, fmt);
+  vsnprintf(buffer,buffer_size, fmt, args);
+  va_end(args);
+
+  fprintf(stderr, RED "[ERROR]: "RESET "%s\n", buffer);
+  fprintf(stderr, "[VERSION]: ");
+  print_version(stderr);
+
+#ifdef GIT_FULL_VERSION
+  if (isReleaseVersion(GIT_FULL_VERSION)) {
+    fprintf(stderr, RED "[ERROR]: "RESET "You are using an outdated version of cpufetch. Please compile cpufetch from source (see https://github.com/Dr-Noob/cpufetch?tab=readme-ov-file#22-building-from-source)");
+  }
+  else {
+    printBugMessage(stderr);
+  }
+#else
+  printBugMessage(stderr);
 #endif
 }
 
@@ -161,6 +210,34 @@ void* erealloc(void *ptr, size_t size) {
   return newptr;
 }
 
+#ifndef __APPLE__
+bool bind_to_cpu(int cpu_id) {
+  #ifdef _WIN32
+    HANDLE process = GetCurrentProcess();
+    DWORD_PTR processAffinityMask = 1 << cpu_id;
+    return SetProcessAffinityMask(process, processAffinityMask);
+  #elif defined __linux__
+    cpu_set_t currentCPU;
+    CPU_ZERO(&currentCPU);
+    CPU_SET(cpu_id, &currentCPU);
+    if (sched_setaffinity (0, sizeof(currentCPU), &currentCPU) == -1) {
+      printWarn("sched_setaffinity: %s", strerror(errno));
+      return false;
+    }
+    return true;
+  #elif defined __FreeBSD__
+    cpuset_t currentCPU;
+    CPU_ZERO(&currentCPU);
+    CPU_SET(cpu_id, &currentCPU);
+    if(cpuset_setaffinity(CPU_LEVEL_WHICH, CPU_WHICH_TID, -1, sizeof(cpuset_t), &currentCPU) == -1) {
+      printWarn("cpuset_setaffinity: %s", strerror(errno));
+      return false;
+    }
+    return true;
+  #endif
+}
+#endif
+
 void print_version(FILE *restrict stream) {
 #ifdef GIT_FULL_VERSION
   fprintf(stream, "cpufetch %s (%s %s)\n", GIT_FULL_VERSION, OS_STR, ARCH_STR);

src/common/global.h

@@ -12,12 +12,16 @@ void set_log_level(bool verbose);
 void printWarn(const char *fmt, ...);
 void printErr(const char *fmt, ...);
 void printBug(const char *fmt, ...);
+void printBugCheckRelease(const char *fmt, ...);
 int min(int a, int b);
 int max(int a, int b);
 char *strremove(char *str, const char *sub);
 void* emalloc(size_t size);
 void* ecalloc(size_t nmemb, size_t size);
 void* erealloc(void *ptr, size_t size);
+#ifndef __APPLE__
+bool bind_to_cpu(int cpu_id);
+#endif
 void print_version(FILE *restrict stream);
 
 #endif

src/common/main.c

@@ -30,11 +30,17 @@ void print_help(char *argv[]) {
 #ifdef ARCH_X86
 #ifdef __linux__
   printf("      --%s %*s Compute the peak performance accurately (measure the CPU frequency instead of using the maximum)\n", t[ARG_ACCURATE_PP], (int) (max_len-strlen(t[ARG_ACCURATE_PP])), "");
-#endif
+  printf("      --%s %*s Measure the max CPU frequency instead of reading it\n", t[ARG_MEASURE_MAX_FREQ], (int) (max_len-strlen(t[ARG_MEASURE_MAX_FREQ])), "");
+#endif // __linux__
   printf("      --%s %*s Show the old Intel logo\n", t[ARG_LOGO_INTEL_OLD], (int) (max_len-strlen(t[ARG_LOGO_INTEL_OLD])), "");
   printf("      --%s %*s Show the new Intel logo\n", t[ARG_LOGO_INTEL_NEW], (int) (max_len-strlen(t[ARG_LOGO_INTEL_NEW])), "");
   printf("  -%c, --%s %*s Show the full CPU name (do not abbreviate it)\n", c[ARG_FULLCPUNAME], t[ARG_FULLCPUNAME], (int) (max_len-strlen(t[ARG_FULLCPUNAME])), "");
   printf("  -%c, --%s %*s Print raw cpuid data (debug purposes)\n", c[ARG_RAW], t[ARG_RAW], (int) (max_len-strlen(t[ARG_RAW])), "");
+#endif // ARCH_X86
+#ifdef ARCH_ARM
+#ifdef __linux__
+  printf("      --%s %*s Measure the max CPU frequency instead of reading it\n", t[ARG_MEASURE_MAX_FREQ], (int) (max_len-strlen(t[ARG_MEASURE_MAX_FREQ])), "");
+#endif
 #endif
   printf("  -%c, --%s %*s Print this help and exit\n", c[ARG_HELP], t[ARG_HELP], (int) (max_len-strlen(t[ARG_HELP])), "");
   printf("  -%c, --%s %*s Print cpufetch version and exit\n", c[ARG_VERSION], t[ARG_VERSION], (int) (max_len-strlen(t[ARG_VERSION])), "");
@@ -45,7 +51,7 @@ void print_help(char *argv[]) {
   printf("  * \"amd\":       Use AMD color scheme \n");
   printf("  * \"ibm\",       Use IBM color scheme \n");
   printf("  * \"arm\":       Use ARM color scheme \n");
-  printf("  * \"rockchip\":  Use ARM color scheme \n");
+  printf("  * \"rockchip\":  Use Rockchip color scheme \n");
   printf("  * \"sifive\":    Use SiFive color scheme \n");
   printf("  * custom:      If the argument of --color does not match any of the previous strings, a custom scheme can be specified.\n");
   printf("                 5 colors must be given in RGB with the format: R,G,B:R,G,B:...\n");
@@ -80,6 +86,11 @@ void print_help(char *argv[]) {
   printf("    --accurate-pp option, which will measure the AVX frequency and show a more precise estimation\n");
   printf("    (this option is only available in x86 architectures).\n");
   printf("    To precisely measure peak performance, see: https://github.com/Dr-Noob/peakperf\n");
+  printf("\n");
+  printf("    Both --accurate-pp and --measure-max-freq measure the actual frequency of the CPU. However,\n");
+  printf("    they differ slightly. The former measures the max frequency while running vectorized SSE/AVX\n");
+  printf("    instructions and it is thus x86 only, whereas the latter simply measures the max clock cycle\n");
+  printf("    and is architecture independent.\n");
 }
 
 int main(int argc, char* argv[]) {

src/common/pci.c

@@ -0,0 +1,133 @@
+#define _GNU_SOURCE
+
+#include <sys/stat.h>
+#include <dirent.h>
+
+#include "udev.h"
+#include "global.h"
+#include "pci.h"
+
+#ifndef PATH_MAX
+  #define PATH_MAX 1024
+#endif
+
+#define PCI_PATH "/sys/bus/pci/devices/"
+#define MAX_LENGTH_PCI_DIR_NAME 1024
+
+// Return a list of PCI devices containing only
+// the sysfs path
+struct pci_devices * get_pci_paths(void) {
+  DIR *dirp;
+
+  if ((dirp = opendir(PCI_PATH)) == NULL) {
+    perror("opendir");
+    return NULL;
+  }
+
+  struct dirent *dp;
+  int numDirs = 0;  
+  errno = 0;
+
+  while ((dp = readdir(dirp)) != NULL) {
+    if (strcmp(dp->d_name, ".") != 0 && strcmp(dp->d_name, "..") != 0)
+      numDirs++;
+  }  
+  if (errno != 0) {
+    perror("readdir");
+    return NULL;
+  }
+
+  rewinddir(dirp);
+
+  struct pci_devices * pci = emalloc(sizeof(struct pci_devices));
+  pci->num_devices = numDirs;
+  pci->devices = emalloc(sizeof(struct pci_device) * pci->num_devices);
+  char * full_path = emalloc(PATH_MAX * sizeof(char));
+  struct stat stbuf;
+  int i = 0;
+
+  while ((dp = readdir(dirp)) != NULL) {
+    if (strcmp(dp->d_name, ".") == 0 || strcmp(dp->d_name, "..") == 0)
+      continue;
+
+    if (strlen(dp->d_name) > MAX_LENGTH_PCI_DIR_NAME) {
+      printErr("Directory name is too long: %s", dp->d_name);
+      return NULL;
+    }
+
+    memset(full_path, 0, PATH_MAX * sizeof(char));
+    snprintf(full_path, min(strlen(PCI_PATH) + strlen(dp->d_name) + 1, PATH_MAX), "%s%s", PCI_PATH, dp->d_name);    
+
+    if (stat(full_path, &stbuf) == -1) {
+      perror("stat");
+      return NULL;
+    }
+
+    if ((stbuf.st_mode & S_IFMT) == S_IFDIR) {
+      int strLen = min(MAX_LENGTH_PCI_DIR_NAME, strlen(dp->d_name)) + 1;
+      pci->devices[i] = emalloc(sizeof(struct pci_device));
+      pci->devices[i]->path = ecalloc(strLen, sizeof(char));
+      strncpy(pci->devices[i]->path, dp->d_name, strLen);
+      i++;
+    }        
+  }
+  if (errno != 0) {
+    perror("readdir");
+    return NULL;
+  }
+
+  return pci;
+}
+
+// For each PCI device in the list pci, fetch its vendor and 
+// device id using sysfs (e.g., /sys/bus/pci/devices/XXX/{vendor/device})
+void populate_pci_devices(struct pci_devices * pci) {
+  int filelen;
+  char* buf;
+
+  for (int i=0; i < pci->num_devices; i++) {
+    struct pci_device* dev = pci->devices[i];
+    int path_size = strlen(PCI_PATH) + strlen(dev->path) + 2;
+
+    // Read vendor_id
+    char *vendor_id_path = emalloc(sizeof(char) * (path_size + strlen("vendor") + 1));
+    sprintf(vendor_id_path, "%s/%s/%s", PCI_PATH, dev->path, "vendor");
+
+    if ((buf = read_file(vendor_id_path, &filelen)) == NULL) {
+      printWarn("read_file: %s: %s\n", vendor_id_path, strerror(errno));
+      dev->vendor_id = 0;
+    }
+    else {
+      dev->vendor_id = strtol(buf, NULL, 16);
+    }
+
+    // Read device_id
+    char *device_id_path = emalloc(sizeof(char) * (path_size + strlen("device") + 1));
+    sprintf(device_id_path, "%s/%s/%s", PCI_PATH, dev->path, "device");
+
+    if ((buf = read_file(device_id_path, &filelen)) == NULL) {
+      printWarn("read_file: %s: %s\n", device_id_path, strerror(errno));
+      dev->device_id = 0;
+    }
+    else {
+      dev->device_id = strtol(buf, NULL, 16);
+    }
+
+    free(vendor_id_path);
+    free(device_id_path);
+  }
+}
+
+// Return a list of PCI devices that could be used to infer the SoC.
+// The criteria to determine which devices are suitable for this task
+// is decided in filter_pci_devices.
+struct pci_devices * get_pci_devices(void) {
+  struct pci_devices * pci = get_pci_paths();
+
+  if (pci == NULL)
+    return NULL;
+
+  populate_pci_devices(pci);  
+
+  return pci;
+}

src/common/pci.h

@@ -0,0 +1,23 @@
+#ifndef __PCI__
+#define __PCI__
+
+#define PCI_VENDOR_NVIDIA   0x10de
+#define PCI_VENDOR_AMPERE   0x1def
+
+#define PCI_DEVICE_TEGRA_X1 0x0faf
+#define PCI_DEVICE_ALTRA    0xe100
+
+struct pci_device {
+  char * path;
+  uint16_t vendor_id;
+  uint16_t device_id;
+};
+
+struct pci_devices {
+  struct pci_device ** devices;
+  int num_devices;
+};
+
+struct pci_devices * get_pci_devices(void);
+
+#endif

src/common/printer.c

@@ -61,6 +61,7 @@ enum {
   ATTRIBUTE_NCORES,
   ATTRIBUTE_NCORES_DUAL,
 #ifdef ARCH_X86
+  ATTRIBUTE_SSE,
   ATTRIBUTE_AVX,
   ATTRIBUTE_FMA,
 #elif ARCH_PPC
@@ -96,6 +97,7 @@ static const char* ATTRIBUTE_FIELDS [] = {
   "Cores:",
   "Cores (Total):",
 #ifdef ARCH_X86
+  "SSE:",
   "AVX:",
   "FMA:",
 #elif ARCH_PPC
@@ -131,6 +133,7 @@ static const char* ATTRIBUTE_FIELDS_SHORT [] = {
   "Cores:",
   "Cores (Total):",
 #ifdef ARCH_X86
+  "SSE:",
   "AVX:",
   "FMA:",
 #elif ARCH_PPC
@@ -336,6 +339,13 @@ struct ascii_logo* choose_ascii_art_aux(struct ascii_logo* logo_long, struct asc
   }
 }
 
+// https://no-color.org/
+bool is_color_enabled(void) {
+  const char *var_name = "NO_COLOR";
+  char *no_color = getenv(var_name);
+  return no_color == NULL || no_color[0] == '\0';
+}
+
 void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* term, int lf) {
   // 1. Choose logo
 #ifdef ARCH_X86
@@ -350,6 +360,9 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
   else if(art->vendor == CPU_VENDOR_AMD) {
     art->art = choose_ascii_art_aux(&logo_amd_l, &logo_amd, term, lf);
   }
+  else if(art->vendor == CPU_VENDOR_HYGON) {
+    art->art = &logo_hygon;
+  }
   else {
     art->art = &logo_unknown;
   }
@@ -364,6 +377,8 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
     art->art = &logo_exynos;
   else if(art->vendor == SOC_VENDOR_KIRIN)
     art->art = &logo_kirin;
+  else if(art->vendor == SOC_VENDOR_KUNPENG)
+    art->art = &logo_kunpeng;
   else if(art->vendor == SOC_VENDOR_BROADCOM)
     art->art = &logo_broadcom;
   else if(art->vendor == SOC_VENDOR_APPLE)
@@ -374,6 +389,14 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
     art->art = &logo_allwinner;
   else if(art->vendor == SOC_VENDOR_ROCKCHIP)
     art->art = &logo_rockchip;
+  else if(art->vendor == SOC_VENDOR_AMPERE)
+    art->art = &logo_ampere;
+  else if(art->vendor == SOC_VENDOR_NXP)
+    art->art = &logo_nxp;
+  else if(art->vendor == SOC_VENDOR_AMLOGIC)
+    art->art = &logo_amlogic;
+  else if(art->vendor == SOC_VENDOR_NVIDIA)
+    art->art = choose_ascii_art_aux(&logo_nvidia_l, &logo_nvidia, term, lf);
   else {
     art->art = choose_ascii_art_aux(&logo_arm_l, &logo_arm, term, lf);
   }
@@ -392,6 +415,9 @@ void choose_ascii_art(struct ascii* art, struct color** cs, struct terminal* ter
 
   // 2. Choose colors
   struct ascii_logo* logo = art->art;
+  bool color = is_color_enabled();
+  if (!color)
+    art->style = STYLE_LEGACY;
 
   switch(art->style) {
     case STYLE_LEGACY:
@@ -577,6 +603,7 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
   for(int i = 0; i < cpu->num_cpus; ptr = ptr->next_cpu, i++) {
     char* max_frequency = get_str_freq(ptr->freq);
     char* avx = get_str_avx(ptr);
+    char* sse = get_str_sse(ptr);
     char* fma = get_str_fma(ptr);
     char* cpu_num = emalloc(sizeof(char) * 9);
 
@@ -611,8 +638,18 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
         setAttribute(art, ATTRIBUTE_NCORES, n_cores);
       }
     }
+
+    // Show the most modern vector instructions.
+    if (strcmp(avx, "No") == 0) {
+      if (strcmp(sse, "No") != 0) {
+        setAttribute(art, ATTRIBUTE_SSE, sse);
+      }
+    }
+    else {
       setAttribute(art, ATTRIBUTE_AVX, avx);
       setAttribute(art, ATTRIBUTE_FMA, fma);
+    }
+
     if(l1i != NULL) setAttribute(art, ATTRIBUTE_L1i, l1i);
     if(l1d != NULL) setAttribute(art, ATTRIBUTE_L1d, l1d);
     if(l2 != NULL) setAttribute(art, ATTRIBUTE_L2, l2);

src/common/soc.c

@@ -15,10 +15,15 @@ static char* soc_trademark_string[] = {
   [SOC_VENDOR_MEDIATEK]   = "MediaTek ",
   [SOC_VENDOR_EXYNOS]     = "Exynos ",
   [SOC_VENDOR_KIRIN]      = "Kirin ",
-  [SOC_VENDOR_BROADCOM]   = "Broadcom BCM",
+  [SOC_VENDOR_KUNPENG]    = "Kunpeng ",
+  [SOC_VENDOR_BROADCOM]   = "Broadcom ",
   [SOC_VENDOR_APPLE]      = "Apple ",
   [SOC_VENDOR_ROCKCHIP]   = "Rockchip ",
   [SOC_VENDOR_GOOGLE]     = "Google ",
+  [SOC_VENDOR_NVIDIA]     = "NVIDIA ",
+  [SOC_VENDOR_AMPERE]     = "Ampere ",
+  [SOC_VENDOR_NXP]        = "NXP ",
+  [SOC_VENDOR_AMLOGIC]    = "Amlogic ",
   // RISC-V
   [SOC_VENDOR_SIFIVE]     = "SiFive ",
   [SOC_VENDOR_STARFIVE]   = "StarFive ",
@@ -28,7 +33,7 @@ static char* soc_trademark_string[] = {
 };
 
 VENDOR get_soc_vendor(struct system_on_chip* soc) {
-  return soc->soc_vendor;
+  return soc->vendor;
 }
 
 char* get_str_process(struct system_on_chip* soc) {
@@ -39,39 +44,37 @@ char* get_str_process(struct system_on_chip* soc) {
     snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
   }
   else {
-    str = emalloc(sizeof(char) * 5);
+    int max_process_len = 5 + 1;
-    memset(str, 0, sizeof(char) * 5);
+    str = ecalloc(max_process_len, sizeof(char));
-    snprintf(str, 5, "%dnm", soc->process);
+    snprintf(str, max_process_len, "%dnm", soc->process);
   }
   return str;
 }
 
 char* get_soc_name(struct system_on_chip* soc) {
-  if(soc->soc_model == SOC_MODEL_UNKNOWN)
+  if(soc->model == SOC_MODEL_UNKNOWN)
     return soc->raw_name;
-  return soc->soc_name;
+  return soc->name;
 }
 
 void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t process) {
-  soc->soc_model = soc_model;
+  soc->model = soc_model;
-  soc->soc_vendor = get_soc_vendor_from_soc(soc_model);
+  soc->vendor = get_soc_vendor_from_soc(soc_model);
   soc->process = process;
-  if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+  if(soc->vendor == SOC_VENDOR_UNKNOWN) {
-    printBug("fill_soc: soc->soc_vendor == SOC_VENDOR_UNKOWN");
+    printBug("fill_soc: soc->vendor == SOC_VENDOR_UNKOWN");
     // If we fall here there is a bug in socs.h
     // Reset everything to avoid segfault
-    soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+    soc->vendor = SOC_VENDOR_UNKNOWN;
-    soc->soc_model = SOC_MODEL_UNKNOWN;
+    soc->model = SOC_MODEL_UNKNOWN;
     soc->process = UNKNOWN;
     soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));
     snprintf(soc->raw_name, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
   }
   else {
-    soc->process = process;
+    int len = strlen(soc_name) + strlen(soc_trademark_string[soc->vendor]) + 1;
-    int len = strlen(soc_name) + strlen(soc_trademark_string[soc->soc_vendor]) + 1;
+    soc->name = emalloc(sizeof(char) * len);
-    soc->soc_name = emalloc(sizeof(char) * len);
+    sprintf(soc->name, "%s%s", soc_trademark_string[soc->vendor], soc_name);
-    memset(soc->soc_name, 0, sizeof(char) * len);
-    sprintf(soc->soc_name, "%s%s", soc_trademark_string[soc->soc_vendor], soc_name);
   }
 }
 

src/common/soc.h

@@ -19,10 +19,15 @@ enum {
   SOC_VENDOR_MEDIATEK,
   SOC_VENDOR_EXYNOS,
   SOC_VENDOR_KIRIN,
+  SOC_VENDOR_KUNPENG,
   SOC_VENDOR_BROADCOM,
   SOC_VENDOR_APPLE,
   SOC_VENDOR_ROCKCHIP,
   SOC_VENDOR_GOOGLE,
+  SOC_VENDOR_NVIDIA,
+  SOC_VENDOR_AMPERE,
+  SOC_VENDOR_NXP,
+  SOC_VENDOR_AMLOGIC,
   // RISC-V
   SOC_VENDOR_SIFIVE,
   SOC_VENDOR_STARFIVE,
@@ -32,14 +37,14 @@ enum {
 };
 
 struct system_on_chip {
-  SOC soc_model;
+  SOC model;
-  VENDOR soc_vendor;
+  VENDOR vendor;
   int32_t process;
-  char* soc_name;
+  char* name;
   char* raw_name;
 };
 
-struct system_on_chip* get_soc(void);
+struct system_on_chip* get_soc(struct cpuInfo* cpu);
 char* get_soc_name(struct system_on_chip* soc);
 VENDOR get_soc_vendor(struct system_on_chip* soc);
 bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process);

src/common/sysctl.c

@@ -4,8 +4,8 @@
 #include <string.h>
 #include <errno.h>
 
-#include "../common/global.h"
+#include "global.h"
-#include "../common/cpu.h"
+#include "cpu.h"
 
 uint32_t get_sys_info_by_name(char* name) {
   size_t size = 0;

src/common/sysctl.h

@@ -8,6 +8,9 @@
 // APPLE_CPU_PART_M2_BLIZZARD=0x30,M2_AVALANCHE=0x31
 #define MIDR_APPLE_M2_BLIZZARD  0x610F0300
 #define MIDR_APPLE_M2_AVALANCHE 0x610F0310
+// https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c
+#define MIDR_APPLE_M3_SAWTOOTH  0x610F0480
+#define MIDR_APPLE_M3_EVEREST   0x610F0490
 
 // M1 / A14
 #ifndef CPUFAMILY_ARM_FIRESTORM_ICESTORM
@@ -17,6 +20,15 @@
 #ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD
   #define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D
 #endif
+// M3 / A16 / A17
+// M3:   https://ratfactor.com/zig/stdlib-browseable2/c/darwin.zig.html
+// M3_2: https://github.com/Dr-Noob/cpufetch/issues/230
+// PRO:  https://github.com/Dr-Noob/cpufetch/issues/225
+// MAX:  https://github.com/Dr-Noob/cpufetch/issues/210
+#define CPUFAMILY_ARM_EVEREST_SAWTOOTH     0x8765EDEA
+#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_2   0xFA33415E
+#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO 0x5F4DEA93
+#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX 0x72015832
 
 // For detecting different M1 types
 // NOTE: Could also be achieved detecting different
@@ -31,6 +43,14 @@
   #define CPUSUBFAMILY_ARM_HC_HD 5
 #endif
 
+// For alternative way to get CPU frequency on macOS and *BSD
+#ifdef __APPLE__
+  #define CPUFREQUENCY_SYSCTL "hw.cpufrequency_max"
+#else
+  // For FreeBSD, not sure about other *BSD
+  #define CPUFREQUENCY_SYSCTL "dev.cpu.0.freq"
+#endif
+
 uint32_t get_sys_info_by_name(char* name);
 
 #endif

src/common/udev.c

@@ -1,7 +1,10 @@
+#include "../common/global.h"
 #include "udev.h"
 #include "global.h"
 #include "cpu.h"
 
+#define _PATH_DEVTREE          "/proc/device-tree/compatible"
+
 // https://www.kernel.org/doc/html/latest/core-api/cpu_hotplug.html
 int get_ncores_from_cpuinfo(void) {
   // Examples:
@@ -143,8 +146,7 @@ char* get_field_from_cpuinfo(char* CPUINFO_FIELD) {
   char* tmp2 = strstr(tmp1, "\n");
 
   int strlen = (1 + (tmp2-tmp1));
-  char* hardware = emalloc(sizeof(char) * strlen);
+  char* hardware = ecalloc(strlen, sizeof(char));
-  memset(hardware, 0, sizeof(char) * strlen);
   strncpy(hardware, tmp1, tmp2-tmp1);
 
   return hardware;
@@ -349,3 +351,13 @@ bool is_devtree_compatible(char* str) {
   }
   return true;
 }
+
+char* get_devtree_compatible(int *filelen) {
+  char* buf;
+
+  if ((buf = read_file(_PATH_DEVTREE, filelen)) == NULL) {
+    printWarn("read_file: %s: %s", _PATH_DEVTREE, strerror(errno));
+  }
+
+  return buf;
+}

src/common/udev.h

@@ -43,5 +43,6 @@ int get_num_sockets_package_cpus(struct topology* topo);
 int get_ncores_from_cpuinfo(void);
 char* get_field_from_cpuinfo(char* CPUINFO_FIELD);
 bool is_devtree_compatible(char* str);
+char* get_devtree_compatible(int *filelen);
 
 #endif

src/ppc/ppc.c

@@ -14,12 +14,14 @@
 static char *hv_vendors_name[] = {
   [HV_VENDOR_KVM]       = "KVM",
   [HV_VENDOR_QEMU]      = "QEMU",
+  [HV_VENDOR_VBOX]      = "VirtualBox",
   [HV_VENDOR_HYPERV]    = "Microsoft Hyper-V",
   [HV_VENDOR_VMWARE]    = "VMware",
   [HV_VENDOR_XEN]       = "Xen",
   [HV_VENDOR_PARALLELS] = "Parallels",
   [HV_VENDOR_PHYP]      = "pHyp",
   [HV_VENDOR_BHYVE]     = "bhyve",
+  [HV_VENDOR_APPLEVZ]   = "Apple VZ",
   [HV_VENDOR_INVALID]   = STRING_UNKNOWN
 };
 
@@ -79,9 +81,13 @@ struct topology* get_topology_info(struct cache* cach) {
   if(!fill_package_ids_from_sys(package_ids, topo->total_cores)) {
     printWarn("fill_package_ids_from_sys failed, output may be incomplete/invalid");
     for(int i=0; i < topo->total_cores; i++) package_ids[i] = 0;
-    // fill_package_ids_from_sys failed, use a
+    // fill_package_ids_from_sys failed, use udev to try
-    // more sophisticated wat to find the number of sockets
+    // to find the number of sockets
     topo->sockets = get_num_sockets_package_cpus(topo);
+    if (topo->sockets == UNKNOWN_DATA) {
+      printWarn("get_num_sockets_package_cpus failed: assuming 1 socket");
+      topo->sockets = 1;
+    }
   }
   else {
     // fill_package_ids_from_sys succeeded, use the
@@ -144,6 +150,7 @@ struct uarch* get_cpu_uarch(struct cpuInfo* cpu) {
 struct frequency* get_frequency_info(void) {
   struct frequency* freq = emalloc(sizeof(struct frequency));
 
+  freq->measured = false;
   freq->max = get_max_freq_from_file(0);
   freq->base = get_min_freq_from_file(0);
 

src/ppc/uarch.c

@@ -25,6 +25,7 @@ enum {
   UARCH_PPC603,
   UARCH_PPC440,
   UARCH_PPC470,
+  UARCH_ESPRESSO, // Not exactly an uarch, but the codename of Wii U
   UARCH_PPC970,
   UARCH_PPC970FX,
   UARCH_PPC970MP,
@@ -75,6 +76,7 @@ void fill_uarch(struct uarch* arch, MICROARCH u) {
   FILL_UARCH(arch->uarch, UARCH_PPC603,      "PowerPC 603",   UNK) // varies
   FILL_UARCH(arch->uarch, UARCH_PPC440,      "PowerPC 440",   UNK)
   FILL_UARCH(arch->uarch, UARCH_PPC470,      "PowerPC 470",    45) // strange...
+  FILL_UARCH(arch->uarch, UARCH_ESPRESSO,    "Espresso",       45) // https://en.wikipedia.org/wiki/PowerPC_7xx#Espresso, https://en.wikipedia.org/wiki/Espresso_(processor), https://github.com/Dr-Noob/cpufetch/issues/231
   FILL_UARCH(arch->uarch, UARCH_PPC970,      "PowerPC 970",   130)
   FILL_UARCH(arch->uarch, UARCH_PPC970FX,    "PowerPC 970FX",  90)
   FILL_UARCH(arch->uarch, UARCH_PPC970MP,    "PowerPC 970MP",  90)
@@ -234,6 +236,7 @@ struct uarch* get_uarch_from_pvr(uint32_t pvr) {
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x7ff50000, UARCH_PPC470)
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x00050000, UARCH_PPC470)
   CHECK_UARCH(arch, pvr, 0xffff0000, 0x11a50000, UARCH_PPC470)
+  CHECK_UARCH(arch, pvr, 0xffffffff, 0x70010201, UARCH_ESPRESSO)
   UARCH_END
 
   return arch;
@@ -280,9 +283,6 @@ char* get_str_process(struct cpuInfo* cpu) {
   if(process == UNK) {
     snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
   }
-  else if(process > 100) {
-    sprintf(str, "%.2fum", (double)process/100);
-  }
   else if(process > 0){
     sprintf(str, "%dnm", process);
   }

src/ppc/udev.c

@@ -13,7 +13,7 @@ bool fill_array_from_sys(int *core_ids, int total_cores, char* SYS_PATH) {
   char* buf;
   char* end;
   char path[128];
-  memset(path, 0, 128);
+  memset(name, 0, sizeof(char) * 128);
 
   for(int i=0; i < total_cores; i++) {
     sprintf(path, "%s%s/cpu%d/%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, i, SYS_PATH);

src/riscv/riscv.c

@@ -19,6 +19,7 @@
 struct frequency* get_frequency_info(uint32_t core) {
   struct frequency* freq = emalloc(sizeof(struct frequency));
 
+  freq->measured = false;
   freq->base = UNKNOWN_DATA;
   freq->max = get_max_freq_from_file(core);
 
@@ -99,9 +100,8 @@ struct extensions* get_extensions_from_str(char* str) {
     return ext;
   }
 
-  int len = sizeof(char) * (strlen(str)+1);
+  int len = strlen(str);
-  ext->str = emalloc(sizeof(char) * len);
+  ext->str = ecalloc(len+1, sizeof(char));
-  memset(ext->str, 0, len);
   strncpy(ext->str, str, sizeof(char) * len);
 
   // Code inspired in Linux kernel (riscv_fill_hwcap):
@@ -163,7 +163,7 @@ struct cpuInfo* get_cpu_info(void) {
   cpu->ext = get_extensions_from_str(ext_str);
   if(cpu->ext->str != NULL && cpu->ext->mask == 0) return NULL;
   cpu->arch = get_uarch_from_cpuinfo_str(cpuinfo_str, cpu);
-  cpu->soc = get_soc();
+  cpu->soc = get_soc(cpu);
   cpu->freq = get_frequency_info(0);
   cpu->peak_performance = get_peak_performance(cpu);
 

src/riscv/soc.c

@@ -12,7 +12,7 @@ bool match_sifive(char* soc_name, struct system_on_chip* soc) {
   /*if((tmp = strstr(soc_name, "???")) == NULL)
     return false;*/
 
-  //soc->soc_vendor = ???
+  //soc->vendor = ???
 
   SOC_START
   SOC_EQ(tmp, "fu740", "Freedom U740",  SOC_SIFIVE_U740, soc, 40)
@@ -65,15 +65,15 @@ struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
   return soc;
 }
 
-struct system_on_chip* get_soc(void) {
+struct system_on_chip* get_soc(struct cpuInfo* cpu) {
   struct system_on_chip* soc = emalloc(sizeof(struct system_on_chip));
   soc->raw_name = NULL;
-  soc->soc_vendor = SOC_VENDOR_UNKNOWN;
+  soc->vendor = SOC_VENDOR_UNKNOWN;
-  soc->soc_model = SOC_MODEL_UNKNOWN;
+  soc->model = SOC_MODEL_UNKNOWN;
   soc->process = UNKNOWN;
 
   soc = guess_soc_from_devtree(soc);
-  if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+  if(soc->vendor == SOC_VENDOR_UNKNOWN) {
     if(soc->raw_name != NULL) {
       printWarn("SoC detection failed using device tree: Found '%s' string", soc->raw_name);
     }
@@ -82,7 +82,7 @@ struct system_on_chip* get_soc(void) {
     }
   }
 
-  if(soc->soc_model == SOC_MODEL_UNKNOWN) {
+  if(soc->model == SOC_MODEL_UNKNOWN) {
     // raw_name might not be NULL, but if we were unable to find
     // the exact SoC, just print "Unkwnown"
     soc->raw_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN)+1));

src/riscv/soc.h

@@ -5,6 +5,6 @@
 #include "../common/cpu.h"
 #include <stdint.h>
 
-struct system_on_chip* get_soc(void);
+struct system_on_chip* get_soc(struct cpuInfo* cpu);
 
 #endif

src/riscv/udev.c

@@ -40,8 +40,7 @@ char* get_field_from_devtree(int DEVTREE_FIELD) {
 
   tmp1++;
   int strlen = filelen-(tmp1-buf);
-  char* hardware = emalloc(sizeof(char) * strlen);
+  char* hardware = ecalloc(strlen, sizeof(char));
-  memset(hardware, 0, sizeof(char) * strlen);
   strncpy(hardware, tmp1, strlen-1);
 
   return hardware;
@@ -70,9 +69,8 @@ char* parse_cpuinfo_field(char* field_str) {
   }
 
   int ret_strlen = (end-tmp);
-  char* ret = emalloc(sizeof(char) * (ret_strlen+1));
+  char* ret = ecalloc(ret_strlen+1, sizeof(char));
-  memset(ret, 0, sizeof(char) * (ret_strlen+1));
+  strncpy(ret, tmp, sizeof(char) * ret_strlen);
-  strncpy(ret, tmp, ret_strlen);
 
   return ret;
 }

src/x86/apic.c

@@ -72,34 +72,6 @@ uint32_t get_apic_id(bool x2apic_id) {
   }
 }
 
-#ifndef __APPLE__
-bool bind_to_cpu(int cpu_id) {
-  #ifdef _WIN32
-    HANDLE process = GetCurrentProcess();
-    DWORD_PTR processAffinityMask = 1 << cpu_id;
-    return SetProcessAffinityMask(process, processAffinityMask);
-  #elif defined __linux__
-    cpu_set_t currentCPU;
-    CPU_ZERO(&currentCPU);
-    CPU_SET(cpu_id, &currentCPU);
-    if (sched_setaffinity (0, sizeof(currentCPU), &currentCPU) == -1) {
-      printWarn("sched_setaffinity: %s", strerror(errno));
-      return false;
-    }
-    return true;
-  #elif defined __FreeBSD__
-    cpuset_t currentCPU;
-    CPU_ZERO(&currentCPU);
-    CPU_SET(cpu_id, &currentCPU);
-    if(cpuset_setaffinity(CPU_LEVEL_WHICH, CPU_WHICH_TID, -1, sizeof(cpuset_t), &currentCPU) == -1) {
-      printWarn("cpuset_setaffinity: %s", strerror(errno));
-      return false;
-    }
-    return true;
-  #endif
-}
-#endif
-
 #ifdef __linux__
 int get_total_cores_module(int total_cores, int module) {
   int total_modules = 2;
@@ -262,15 +234,11 @@ uint32_t max_apic_id_size(uint32_t** cache_id_apic, struct topology* topo) {
 
 bool build_topo_from_apic(uint32_t* apic_pkg, uint32_t* apic_smt, uint32_t** cache_id_apic, struct topology* topo) {
   uint32_t size = max_apic_id_size(cache_id_apic, topo);
-  uint32_t* sockets = emalloc(sizeof(uint32_t) * size);
+  uint32_t* sockets = ecalloc(size, sizeof(uint32_t));
-  uint32_t* smt = emalloc(sizeof(uint32_t) * size);
+  uint32_t* smt = ecalloc(size, sizeof(uint32_t));
-  uint32_t* apic_id = emalloc(sizeof(uint32_t) * size);
+  uint32_t* apic_id = ecalloc(size, sizeof(uint32_t));
   uint32_t num_caches = 0;
 
-  memset(sockets, 0, sizeof(uint32_t) * size);
-  memset(smt, 0, sizeof(uint32_t) * size);  
-  memset(apic_id, 0, sizeof(uint32_t) * size);
-
   // System topology
   for(int i=0; i < topo->total_cores_module; i++) {
     sockets[apic_pkg[i]] = 1;
@@ -397,6 +365,11 @@ bool fill_apic_ids(uint32_t* apic_ids, int first_core, int n, bool x2apic_id) {
 }
 
 bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
+  if (topo->cach == NULL) {
+    printWarn("get_topology_from_apic: cach is NULL");
+    return false;
+  }
+
   uint32_t apic_id;
   uint32_t* apic_ids = emalloc(sizeof(uint32_t) * topo->total_cores_module);
   uint32_t* apic_pkg = emalloc(sizeof(uint32_t) * topo->total_cores_module);

src/x86/apic.h

@@ -17,10 +17,6 @@ struct apic {
 bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo);
 uint32_t is_smt_enabled_amd(struct topology* topo);
 
-#ifndef __APPLE__
-bool bind_to_cpu(int cpu_id);
-#endif
-
 #ifdef __linux__
 int get_total_cores_module(int total_cores, int module);
 #endif

src/x86/cpuid.c

@@ -5,6 +5,13 @@
   #include "../common/udev.h"
   #include <unistd.h>
 #endif
+#if defined (__FreeBSD__) || defined (__APPLE__)
+  #include "../common/sysctl.h"
+#endif
+
+#ifdef __linux__
+  #include "../common/freq.h"
+#endif
 
 #include <stdio.h>
 #include <stdlib.h>
@@ -22,27 +29,32 @@
 
 #define CPU_VENDOR_INTEL_STRING "GenuineIntel"
 #define CPU_VENDOR_AMD_STRING   "AuthenticAMD"
+#define CPU_VENDOR_HYGON_STRING "HygonGenuine"
 
 static const char *hv_vendors_string[] = {
   [HV_VENDOR_KVM]       = "KVMKVMKVM",
   [HV_VENDOR_QEMU]      = "TCGTCGTCGTCG",
+  [HV_VENDOR_VBOX]      = "VBoxVBoxVBox",
   [HV_VENDOR_HYPERV]    = "Microsoft Hv",
   [HV_VENDOR_VMWARE]    = "VMwareVMware",
   [HV_VENDOR_XEN]       = "XenVMMXenVMM",
   [HV_VENDOR_PARALLELS] = "lrpepyh vr",
+  [HV_VENDOR_PHYP]      = NULL,
   [HV_VENDOR_BHYVE]     = "bhyve bhyve ",
-  [HV_VENDOR_PHYP]      = NULL
+  [HV_VENDOR_APPLEVZ]   = "Apple VZ"
 };
 
 static char *hv_vendors_name[] = {
   [HV_VENDOR_KVM]       = "KVM",
   [HV_VENDOR_QEMU]      = "QEMU",
+  [HV_VENDOR_VBOX]      = "VirtualBox",
   [HV_VENDOR_HYPERV]    = "Microsoft Hyper-V",
   [HV_VENDOR_VMWARE]    = "VMware",
   [HV_VENDOR_XEN]       = "Xen",
   [HV_VENDOR_PARALLELS] = "Parallels",
   [HV_VENDOR_PHYP]      = "pHyp",
   [HV_VENDOR_BHYVE]     = "bhyve",
+  [HV_VENDOR_APPLEVZ]   = "Apple VZ",
   [HV_VENDOR_INVALID]   = STRING_UNKNOWN
 };
 
@@ -79,8 +91,7 @@ char* get_str_cpu_name_internal(void) {
   uint32_t edx = 0;
   uint32_t c = 0;
 
-  char * name = emalloc(sizeof(char) * CPU_NAME_MAX_LENGTH);
+  char * name = ecalloc(CPU_NAME_MAX_LENGTH, sizeof(char));
-  memset(name, 0, CPU_NAME_MAX_LENGTH);
 
   for(int i=0; i < 3; i++) {
     eax = 0x80000002 + i;
@@ -214,7 +225,7 @@ int64_t get_peak_performance(struct cpuInfo* cpu, bool accurate_pp) {
   #endif
 
     //First, check we have consistent data
-    if(freq == UNKNOWN_DATA || topo->logical_cores == UNKNOWN_DATA) {
+    if(freq == UNKNOWN_DATA || topo == NULL || topo->logical_cores == UNKNOWN_DATA) {
       return -1;
     }
 
@@ -269,7 +280,7 @@ struct hypervisor* get_hp_info(bool hv_present) {
   }
   else {
     char name[13];
-    memset(name, 0, 13);
+    memset(name, 0, sizeof(char) * 13);
     get_name_cpuid(name, ebx, ecx, edx);
 
     bool found = false;
@@ -284,7 +295,7 @@ struct hypervisor* get_hp_info(bool hv_present) {
 
     if(!found) {
       hv->hv_vendor = HV_VENDOR_INVALID;
-      printBug("Unknown hypervisor vendor: %s", name);
+      printBug("Unknown hypervisor vendor: '%s'", name);
     }
   }
 
@@ -447,7 +458,7 @@ struct cpuInfo* get_cpu_info(void) {
   cpu->cach = NULL;
   cpu->feat = NULL;
 
-  uint32_t modules = 1;
+  cpu->num_cpus = 1;
   uint32_t eax = 0;
   uint32_t ebx = 0;
   uint32_t ecx = 0;
@@ -459,13 +470,15 @@ struct cpuInfo* get_cpu_info(void) {
 
   //Fill vendor
   char name[13];
-  memset(name,0,13);
+  memset(name, 0, sizeof(char) * 13);
   get_name_cpuid(name, ebx, edx, ecx);
 
   if(strcmp(CPU_VENDOR_INTEL_STRING,name) == 0)
     cpu->cpu_vendor = CPU_VENDOR_INTEL;
   else if (strcmp(CPU_VENDOR_AMD_STRING,name) == 0)
     cpu->cpu_vendor = CPU_VENDOR_AMD;
+  else if (strcmp(CPU_VENDOR_HYGON_STRING,name) == 0)
+    cpu->cpu_vendor = CPU_VENDOR_HYGON;
   else {
     cpu->cpu_vendor = CPU_VENDOR_INVALID;
     printErr("Unknown CPU vendor: %s", name);
@@ -484,9 +497,8 @@ struct cpuInfo* get_cpu_info(void) {
     cpu->cpu_name = get_str_cpu_name_internal();
   }
   else {
-    cpu->cpu_name = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN) + 1));
+    cpu->cpu_name = NULL;
-    strcpy(cpu->cpu_name, STRING_UNKNOWN);
+    printWarn("Can't read CPU name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);
-    printWarn("Can't read cpu name from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000004, cpu->maxExtendedLevels);
   }
 
   cpu->topology_extensions = false;
@@ -504,12 +516,12 @@ struct cpuInfo* get_cpu_info(void) {
     cpu->hybrid_flag = (edx >> 15) & 0x1;
   }
 
-  if(cpu->hybrid_flag) modules = 2;
+  if(cpu->hybrid_flag) cpu->num_cpus = 2;
 
   struct cpuInfo* ptr = cpu;
-  for(uint32_t i=0; i < modules; i++) {
+  for(uint32_t i=0; i < cpu->num_cpus; i++) {
     int32_t first_core;
-    set_cpu_module(i, modules, &first_core);
+    set_cpu_module(i, cpu->num_cpus, &first_core);
 
     if(i > 0) {
       ptr->next_cpu = emalloc(sizeof(struct cpuInfo));
@@ -536,14 +548,15 @@ struct cpuInfo* get_cpu_info(void) {
     ptr->first_core_id = first_core;
     ptr->feat = get_features_info(ptr);
 
-    // If any field of the struct is NULL,
-    // return inmideately, as further functions
-    // require valid fields (cach, topo, etc)
     ptr->arch = get_cpu_uarch(ptr);
     ptr->freq = get_frequency_info(ptr);
 
+    if (cpu->cpu_name == NULL && ptr == cpu) {
+      // If we couldnt read CPU name from cpuid, infer it now
+      cpu->cpu_name = infer_cpu_name_from_uarch(cpu->arch);
+    }
+
     ptr->cach = get_cache_info(ptr);
-    if(ptr->cach == NULL) return cpu;
 
     if(cpu->hybrid_flag) {
       ptr->topo = get_topology_info(ptr, ptr->cach, i);
@@ -551,16 +564,23 @@ struct cpuInfo* get_cpu_info(void) {
     else {
       ptr->topo = get_topology_info(ptr, ptr->cach, -1);
     }
-    if(cpu->topo == NULL) return cpu;
+
+    // If topo is NULL, return early, as get_peak_performance
+    // requries non-NULL topology.
+    if(ptr->topo == NULL) return cpu;
   }
 
-  cpu->num_cpus = modules;
   cpu->peak_performance = get_peak_performance(cpu, accurate_pp());
 
   return cpu;
 }
 
 bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
+  if (topo->cach == NULL) {
+    printWarn("get_cache_topology_amd: cach is NULL");
+    return false;
+  }
+
   if(cpu->maxExtendedLevels >= 0x8000001D && cpu->topology_extensions) {
     uint32_t i, eax, ebx, ecx, edx, num_sharing_cache, cache_type, cache_level;
 
@@ -636,10 +656,17 @@ bool get_cache_topology_amd(struct cpuInfo* cpu, struct topology* topo) {
 
 #ifdef __linux__
 void get_topology_from_udev(struct topology* topo) {
-  // TODO: To be improved in the future
   topo->total_cores = get_ncores_from_cpuinfo();
+  // TODO: To be improved in the future
+  if (topo->total_cores == 1) {
+    // We can assume it's a single core CPU
     topo->logical_cores = topo->total_cores;
     topo->physical_cores = topo->total_cores;
+  }
+  else {
+    topo->logical_cores = UNKNOWN_DATA;
+    topo->physical_cores = UNKNOWN_DATA;
+  }
   topo->smt_available = 1;
   topo->smt_supported = 1;
   topo->sockets = 1;
@@ -684,32 +711,31 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
     topo->total_cores_module = topo->total_cores;
   }
 
+  bool toporet = false;
   switch(cpu->cpu_vendor) {
     case CPU_VENDOR_INTEL:
       if (cpu->maxLevels >= 0x00000004) {
-        bool toporet = get_topology_from_apic(cpu, topo);
+        toporet = get_topology_from_apic(cpu, topo);
+      }
+      else {
+        printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000004, cpu->maxLevels);
+      }
       if(!toporet) {
         #ifdef __linux__
-            printWarn("Failed to retrieve topology from APIC, using udev...\n");
+          printWarn("Failed to retrieve topology from APIC, using udev...");
           get_topology_from_udev(topo);
         #else
-            printErr("Failed to retrieve topology from APIC, assumming default values...\n");
+          if (cpu->maxLevels >= 0x00000004)
+            printErr("Failed to retrieve topology from APIC, assumming default values...");
           topo->logical_cores = UNKNOWN_DATA;
           topo->physical_cores = UNKNOWN_DATA;
           topo->smt_available = 1;
           topo->smt_supported = 1;
         #endif
       }
-      }
-      else {
-        printWarn("Can't read topology information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000001, cpu->maxLevels);
-        topo->physical_cores = 1;
-        topo->logical_cores = 1;
-        topo->smt_available = 1;
-        topo->smt_supported = 1;
-      }
       break;
     case CPU_VENDOR_AMD:
+    case CPU_VENDOR_HYGON:
       if (cpu->maxExtendedLevels >= 0x80000008) {
         eax = 0x80000008;
         cpuid(&eax, &ebx, &ecx, &edx);
@@ -726,10 +752,15 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
         }
       }
       else {
+        #ifdef __linux__
+          printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X), using udev...", 0x80000008, cpu->maxExtendedLevels);
+          get_topology_from_udev(topo);
+        #else
           printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000008, cpu->maxExtendedLevels);
           topo->physical_cores = 1;
           topo->logical_cores = 1;
           topo->smt_supported = 1;
+        #endif
       }
 
       if (cpu->maxLevels >= 0x00000001) {
@@ -906,16 +937,27 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
 
 struct frequency* get_frequency_info(struct cpuInfo* cpu) {
   struct frequency* freq = emalloc(sizeof(struct frequency));
+  freq->measured = false;
 
   if(cpu->maxLevels < 0x00000016) {
-    #if defined (_WIN32) || defined (__APPLE__)
+    #if defined (_WIN32)
       printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000016, cpu->maxLevels);
       freq->base = UNKNOWN_DATA;
       freq->max = UNKNOWN_DATA;
+    #elif defined (__FreeBSD__) || defined (__APPLE__)
+      printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X). Using sysctl", 0x00000016, cpu->maxLevels);
+      uint32_t freq_hz = get_sys_info_by_name(CPUFREQUENCY_SYSCTL);
+      if (freq_hz == 0) {
+        printWarn("Read max CPU frequency from sysctl and got 0 MHz");
+        freq->max = UNKNOWN_DATA;
+      }
+
+      freq->base = UNKNOWN_DATA;
+      freq->max = freq_hz;
     #else
       printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X). Using udev", 0x00000016, cpu->maxLevels);
       freq->base = UNKNOWN_DATA;
-      freq->max = get_max_freq_from_file(0);
+      freq->max = get_max_freq_from_file(cpu->first_core_id);
 
       if(freq->max == 0) {
         printWarn("Read max CPU frequency from udev and got 0 MHz");
@@ -942,7 +984,7 @@ struct frequency* get_frequency_info(struct cpuInfo* cpu) {
       printWarn("Read max CPU frequency from CPUID and got 0 MHz");
       #ifdef __linux__
         printWarn("Using udev to detect frequency");
-        freq->max = get_max_freq_from_file(0);
+        freq->max = get_max_freq_from_file(cpu->first_core_id);
 
         if(freq->max == 0) {
           printWarn("Read max CPU frequency from udev and got 0 MHz");
@@ -954,6 +996,15 @@ struct frequency* get_frequency_info(struct cpuInfo* cpu) {
     }
   }
 
+  #ifdef __linux__
+    if (freq->max == UNKNOWN_DATA || measure_max_frequency_flag()) {
+      if (freq->max == UNKNOWN_DATA)
+        printWarn("All previous methods failed, measuring CPU frequency");
+      freq->max = measure_max_frequency(cpu->first_core_id);
+      freq->measured = true;
+    }
+  #endif
+
   return freq;
 }
 
@@ -975,24 +1026,33 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_soc
     string = emalloc(sizeof(char) * (strlen(STRING_UNKNOWN) + 1));
     strcpy(string, STRING_UNKNOWN);
   }
-  else if(topo->smt_supported > 1) {
+  else {
+    char cores_str[6];
+    memset(cores_str, 0, sizeof(char) * 6);
+    if (topo->physical_cores * topo_sockets > 1)
+      strcpy(cores_str, "cores");
+    else
+      strcpy(cores_str, "core");
+
+    if(topo->smt_supported > 1) {
       // 4 for digits, 21 for ' cores (SMT disabled)' which is the longest possible output
       uint32_t max_size = 4+21+1;
       string = emalloc(sizeof(char) * max_size);
 
       if(topo->smt_available > 1)
-      snprintf(string, max_size, "%d cores (%d threads)", topo->physical_cores * topo_sockets, topo->logical_cores * topo_sockets);
+        snprintf(string, max_size, "%d %s (%d threads)", topo->physical_cores * topo_sockets, cores_str, topo->logical_cores * topo_sockets);
       else {
         if(cpu->cpu_vendor == CPU_VENDOR_AMD)
-        snprintf(string, max_size, "%d cores (SMT disabled)", topo->physical_cores * topo_sockets);
+          snprintf(string, max_size, "%d %s (SMT disabled)", topo->physical_cores * topo_sockets, cores_str);
         else
-        snprintf(string, max_size, "%d cores (HT disabled)", topo->physical_cores * topo_sockets);
+          snprintf(string, max_size, "%d %s (HT disabled)", topo->physical_cores * topo_sockets, cores_str);
       }
     }
     else {
       uint32_t max_size = 4+7+1;
       string = emalloc(sizeof(char) * max_size);
-    snprintf(string, max_size, "%d cores",topo->physical_cores * topo_sockets);
+      snprintf(string, max_size, "%d %s",topo->physical_cores * topo_sockets, cores_str);
+    }
   }
 
   return string;
@@ -1053,8 +1113,14 @@ char* get_str_sse(struct cpuInfo* cpu) {
       last+=SSE4_2_sl;
   }
 
+  if (last == 0) {
+    snprintf(string, 2+1, "No");
+  }
+  else {
     //Purge last comma
     string[last-1] = '\0';
+  }
+
   return string;
 }
 
@@ -1170,9 +1236,7 @@ void print_raw(struct cpuInfo* cpu) {
 }
 
 void free_topo_struct(struct topology* topo) {
-  if(topo->apic->cache_select_mask != NULL)
   free(topo->apic->cache_select_mask);
-  if(topo->apic->cache_id_apic != NULL)
   free(topo->apic->cache_id_apic);
   free(topo->apic);
   free(topo);

src/x86/freq/freq.c

@@ -116,8 +116,25 @@ int64_t measure_frequency(struct cpuInfo* cpu) {
   }
 
   pthread_t* compute_th = malloc(sizeof(pthread_t) * cpu->topo->total_cores);
+  cpu_set_t cpus;
+  pthread_attr_t attr;
+  if ((ret = pthread_attr_init(&attr)) != 0) {
+    printErr("pthread_attr_init: %s", strerror(ret));
+    return -1;
+  }
+
   for(int i=0; i < cpu->topo->total_cores; i++) {
-    ret = pthread_create(&compute_th[i], NULL, compute_function, NULL);
+    // We might have called bind_to_cpu previously, binding the threads
+    // to a specific core, so now we must make sure we run the new thread
+    // on the correct core.
+    CPU_ZERO(&cpus);
+    CPU_SET(i, &cpus);
+    if ((ret = pthread_attr_setaffinity_np(&attr, sizeof(cpu_set_t), &cpus)) != 0) {
+      printErr("pthread_attr_setaffinity_np: %s", strerror(ret));
+      return -1;
+    }
+
+    ret = pthread_create(&compute_th[i], &attr, compute_function, NULL);
 
     if(ret != 0) {
       fprintf(stderr, "Error creating thread\n");

src/x86/uarch.c

@@ -47,8 +47,12 @@ typedef uint32_t MICROARCH;
 enum {
   UARCH_UNKNOWN,
   // INTEL //
+  UARCH_I486,
   UARCH_P5,
-  UARCH_P6,
+  UARCH_P5_MMX,
+  UARCH_P6_PRO,
+  UARCH_P6_PENTIUM_II,
+  UARCH_P6_PENTIUM_III,
   UARCH_DOTHAN,
   UARCH_YONAH,
   UARCH_MEROM,
@@ -95,6 +99,8 @@ enum {
   // AMD //
   UARCH_AM486,
   UARCH_AM5X86,
+  UARCH_SSA5,
+  UARCH_K5,
   UARCH_K6,
   UARCH_K7,
   UARCH_K8,
@@ -125,8 +131,7 @@ struct uarch {
 #define UARCH_START if (false) {}
 #define CHECK_UARCH(arch, ef_, f_, em_, m_, s_, str, uarch, process) \
    else if (ef_ == ef && f_ == f && (em_ == NA || em_ == em) && (m_ == NA || m_ == m) && (s_ == NA || s_ == s)) fill_uarch(arch, str, uarch, process);
-#define UARCH_END else { printErr("Unknown microarchitecture detected: M=0x%X EM=0x%X F=0x%X EF=0x%X S=0x%X", m, em, f, ef, s); \
+#define UARCH_END else { printBugCheckRelease("Unknown microarchitecture detected: M=0x%X EM=0x%X F=0x%X EF=0x%X S=0x%X", m, em, f, ef, s); \
-fprintf(stderr, "Please see https://github.com/Dr-Noob/cpufetch#61-unknown-microarchitecture-error to know how to report this error\n"); \
 fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK); }
 
 void fill_uarch(struct uarch* arch, char* str, MICROARCH u, uint32_t process) {
@@ -145,31 +150,45 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   // EM: Extended Model                                                              //
   // M: Model                                                                        //
   // S: Stepping                                                                     //
-  // ----------------------------------------------------------------------------- //
+  // ------------------------------------------------------------------------------- //
   //                EF  F  EM   M   S                                                //
   UARCH_START
+  CHECK_UARCH(arch, 0,  4,  0,  0, NA, "i80486DX",          UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  1, NA, "i80486DX-50",       UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  2, NA, "i80486SX",          UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  3, NA, "i80486DX2",         UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  4, NA, "i80486SL",          UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  5, NA, "i80486SX2",         UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  7, NA, "i80486DX2WB",       UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  8, NA, "i80486DX4",         UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  9, NA, "i80486DX4WB",       UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
   CHECK_UARCH(arch, 0,  5,  0,  0, NA, "P5",                UARCH_P5,              800)
   CHECK_UARCH(arch, 0,  5,  0,  1, NA, "P5",                UARCH_P5,              800)
-  CHECK_UARCH(arch, 0,  5,  0,  2, NA, "P5",              UARCH_P5,              UNK)
+  CHECK_UARCH(arch, 0,  5,  0,  2, NA, "P54C",              UARCH_P5,              UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
-  CHECK_UARCH(arch, 0,  5,  0,  3, NA, "P5",              UARCH_P5,              600)
+  CHECK_UARCH(arch, 0,  5,  0,  3, NA, "P24T (Overdrive)",  UARCH_P5,              600) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
-  CHECK_UARCH(arch, 0,  5,  0,  4, NA, "P5 MMX",          UARCH_P5,              UNK)
+  CHECK_UARCH(arch, 0,  5,  0,  4, NA, "P55C (MMX)",        UARCH_P5_MMX,          350) // https://www.cpu-world.com/CPUs/Pentium/TYPE-Pentium%20MMX.html
-  CHECK_UARCH(arch, 0,  5,  0,  7, NA, "P5 MMX",          UARCH_P5,              UNK)
+  CHECK_UARCH(arch, 0,  5,  0,  7, NA, "P54C",              UARCH_P5,              350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
-  CHECK_UARCH(arch, 0,  5,  0,  8, NA, "P5 MMX",          UARCH_P5,              250)
+  CHECK_UARCH(arch, 0,  5,  0,  8, NA, "Tillamook",         UARCH_P5_MMX,          250) // http://instlatx64.atw.hu./
   CHECK_UARCH(arch, 0,  5,  0,  9,  0, "Lakemont",          UARCH_LAKEMONT,         32)
-  CHECK_UARCH(arch, 0,  5,  0,  9, NA, "P5 MMX",          UARCH_P5,              UNK)
+  CHECK_UARCH(arch, 0,  5,  0,  9, NA, "P5 (MMX)",          UARCH_P5_MMX,          UNK)
   CHECK_UARCH(arch, 0,  5,  0, 10,  0, "Lakemont",          UARCH_LAKEMONT,         32)
-  CHECK_UARCH(arch, 0,  6,  0,  0, NA, "P6 Pentium II",   UARCH_P6,              UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  1,  1, "P6",                UARCH_P6_PRO,          UNK)
-  CHECK_UARCH(arch, 0,  6,  0,  1, NA, "P6 Pentium II",   UARCH_P6,              UNK) // process depends on core
+  CHECK_UARCH(arch, 0,  6,  0,  1,  2, "P6",                UARCH_P6_PRO,          UNK)
-  CHECK_UARCH(arch, 0,  6,  0,  2, NA, "P6 Pentium II",   UARCH_P6,              UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  1,  6, "P6",                UARCH_P6_PRO,          350)
-  CHECK_UARCH(arch, 0,  6,  0,  3, NA, "P6 Pentium II",   UARCH_P6,              350)
+  CHECK_UARCH(arch, 0,  6,  0,  1,  7, "P6",                UARCH_P6_PRO,          350)
-  CHECK_UARCH(arch, 0,  6,  0,  4, NA, "P6 Pentium II",   UARCH_P6,              UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  1,  9, "P6",                UARCH_P6_PRO,          350)
-  CHECK_UARCH(arch, 0,  6,  0,  5, NA, "P6 Pentium II",   UARCH_P6,              250)
+  CHECK_UARCH(arch, 0,  6,  0,  0, NA, "P6 (Pentium II)",   UARCH_P6_PENTIUM_II,   UNK)
-  CHECK_UARCH(arch, 0,  6,  0,  6, NA, "P6 Pentium II",   UARCH_P6,              UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  1, NA, "P6 (Pentium II)",   UARCH_P6_PENTIUM_II,   UNK) // process depends on core
-  CHECK_UARCH(arch, 0,  6,  0,  7, NA, "P6 Pentium III",  UARCH_P6,              250)
+  CHECK_UARCH(arch, 0,  6,  0,  2, NA, "P6 (Pentium II)",   UARCH_P6_PENTIUM_II,   UNK)
-  CHECK_UARCH(arch, 0,  6,  0,  8, NA, "P6 Pentium III",  UARCH_P6,              180)
+  CHECK_UARCH(arch, 0,  6,  0,  3, NA, "P6 (Klamath)",      UARCH_P6_PENTIUM_II,   350) // http://instlatx64.atw.hu.
-  CHECK_UARCH(arch, 0,  6,  0,  9, NA, "P6 Pentium M",    UARCH_P6,              130)
+  CHECK_UARCH(arch, 0,  6,  0,  4, NA, "P6 (Pentium II)",   UARCH_P6_PENTIUM_II,   UNK)
-  CHECK_UARCH(arch, 0,  6,  0, 10, NA, "P6 Pentium III",  UARCH_P6,              180)
+  CHECK_UARCH(arch, 0,  6,  0,  5, NA, "P6 (Deschutes)",    UARCH_P6_PENTIUM_II,   250) // http://instlatx64.atw.hu.
-  CHECK_UARCH(arch, 0,  6,  0, 11, NA, "P6 Pentium III",  UARCH_P6,              130)
+  CHECK_UARCH(arch, 0,  6,  0,  6, NA, "P6 (Dixon)",        UARCH_P6_PENTIUM_II,   UNK) // http://instlatx64.atw.hu.
+  CHECK_UARCH(arch, 0,  6,  0,  7, NA, "P6 (Katmai)",       UARCH_P6_PENTIUM_III,  250) // Core names from: https://en.wikichip.org/wiki/intel/cpuid. NOTE: Xeon core names are different! https://www.techpowerup.com/cpu-specs/?generation=Intel+Pentium+III+Xeon
+  CHECK_UARCH(arch, 0,  6,  0,  8, NA, "P6 (Coppermine)",   UARCH_P6_PENTIUM_III,  180) // Also: https://en.wikipedia.org/wiki/Pentium_III
+  CHECK_UARCH(arch, 0,  6,  0,  9, NA, "P6 (Pentium M)",    UARCH_P6_PENTIUM_III,  130)
+  CHECK_UARCH(arch, 0,  6,  0, 10, NA, "P6 (Coppermine T)", UARCH_P6_PENTIUM_III,  180)
+  CHECK_UARCH(arch, 0,  6,  0, 11, NA, "P6 (Tualatin)",     UARCH_P6_PENTIUM_III,  130)
   CHECK_UARCH(arch, 0,  6,  0, 13, NA, "Dothan",            UARCH_DOTHAN,          UNK)  // process depends on core
   CHECK_UARCH(arch, 0,  6,  0, 14, NA, "Yonah",             UARCH_YONAH,            65)
   CHECK_UARCH(arch, 0,  6,  0, 15, NA, "Merom",             UARCH_MEROM,            65)
@@ -278,11 +297,16 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
   // ----------------------------------------------------------------------------- //
   //                 EF  F  EM   M   S                                             //
   UARCH_START
-  CHECK_UARCH(arch,  0,  4,  0,  3, NA, "Am486",       UARCH_AM486,      UNK)
+  CHECK_UARCH(arch,  0,  4,  0,  3, NA, "Am486DX2",    UARCH_AM486,      UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
-  CHECK_UARCH(arch,  0,  4,  0,  7, NA, "Am486",       UARCH_AM486,      UNK)
+  CHECK_UARCH(arch,  0,  4,  0,  7, NA, "Am486DX2WB",  UARCH_AM486,      UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
-  CHECK_UARCH(arch,  0,  4,  0,  8, NA, "Am486",       UARCH_AM486,      UNK)
+  CHECK_UARCH(arch,  0,  4,  0,  8, NA, "Am486DX4",    UARCH_AM486,      UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
-  CHECK_UARCH(arch,  0,  4,  0,  9, NA, "Am486",       UARCH_AM486,      UNK)
+  CHECK_UARCH(arch,  0,  4,  0,  9, NA, "Am486DX4WB",  UARCH_AM486,      UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
-  CHECK_UARCH(arch,  0,  4, NA, NA, NA, "Am5x86",      UARCH_AM5X86,     UNK)
+  CHECK_UARCH(arch,  0,  4,  0, 14, NA, "Am5x86",      UARCH_AM5X86,     350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  4,  0, 15, NA, "Am5x86WB",    UARCH_AM5X86,     350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  5,  0,  0, NA, "SSA5 (K5)",   UARCH_SSA5,       350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  5,  0,  1, NA, "K5",          UARCH_K5,         350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  5,  0,  2, NA, "K5",          UARCH_K5,         350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  5,  0,  3, NA, "K5",          UARCH_K5,         350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
   CHECK_UARCH(arch,  0,  5,  0,  6, NA, "K6",          UARCH_K6,         300)
   CHECK_UARCH(arch,  0,  5,  0,  7, NA, "K6",          UARCH_K6,         250) // *p from sandpile.org
   CHECK_UARCH(arch,  0,  5,  0, 10, NA, "K7",          UARCH_K7,         130) // Geode NX
@@ -381,6 +405,7 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
   CHECK_UARCH(arch, 10, 15,  5,  0, NA, "Zen 3",       UARCH_ZEN3,         7) // instlatx64
   CHECK_UARCH(arch, 10, 15,  6,  1,  2, "Zen 4",       UARCH_ZEN4,         5) // instlatx64
   CHECK_UARCH(arch, 10, 15,  7,  4,  1, "Zen 4",       UARCH_ZEN4,         4) // instlatx64
+  CHECK_UARCH(arch, 10, 15,  7,  5,  2, "Zen 4",       UARCH_ZEN4,         4) // instlatx64
   CHECK_UARCH(arch, 10, 15,  7,  8,  0, "Zen 4",       UARCH_ZEN4,         4) // instlatx64
   CHECK_UARCH(arch, 10, 15,  8, NA, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64 (AMD MI300C)
   CHECK_UARCH(arch, 10, 15,  9, NA, NA, "Zen 4",       UARCH_ZEN4,         5) // instlatx64 (AMD MI300A)
@@ -390,13 +415,37 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
   return arch;
 }
 
-struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
+struct uarch* get_uarch_from_cpuid_hygon(uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
-  if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
-    if(dump == 0x000806E9) {
-      // It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
-      // See issue https://github.com/Dr-Noob/cpufetch/issues/122
   struct uarch* arch = emalloc(sizeof(struct uarch));
 
+  // EF: Extended Family                                                           //
+  // F:  Family                                                                    //
+  // EM: Extended Model                                                            //
+  // M: Model                                                                      //
+  // S: Stepping                                                                   //
+  // ----------------------------------------------------------------------------- //
+  //                 EF  F  EM   M   S                                             //
+  UARCH_START
+  // https://www.phoronix.com/news/Hygon-Dhyana-AMD-China-CPUs
+  CHECK_UARCH(arch,  9,  15,  0,  1, NA, "Zen",       UARCH_ZEN,      UNK) // https://github.com/Dr-Noob/cpufetch/issues/244
+  // CHECK_UARCH(arch,  9,  15,  0,  2, NA, "???",       ?????????,      UNK) // http://instlatx64.atw.hu/
+  UARCH_END
+
+  return arch;
+}
+
+struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
+  if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
+    struct uarch* arch = emalloc(sizeof(struct uarch));
+    if(dump == 0x000806E9) {
+      if (cpu->cpu_name == NULL) {
+        printErr("Unable to find uarch without CPU name");
+        fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK);
+        return arch;
+      }
+
+      // It is not possible to determine uarch only from CPUID dump (can be Kaby Lake or Amber Lake)
+      // See issue https://github.com/Dr-Noob/cpufetch/issues/122
       if(strstr(cpu->cpu_name, "Y") != NULL) {
         fill_uarch(arch, "Amber Lake", UARCH_AMBER_LAKE, 14);
       }
@@ -407,10 +456,14 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
       return arch;
     }
     else if (dump == 0x000806EA) {
+      if (cpu->cpu_name == NULL) {
+        printErr("Unable to find uarch without CPU name");
+        fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, UNK);
+        return arch;
+      }
+
       // It is not possible to determine uarch only from CPUID dump (can be Kaby Lake R or Coffee Lake U)
       // See issue https://github.com/Dr-Noob/cpufetch/issues/149
-      struct uarch* arch = emalloc(sizeof(struct uarch));
-
       if(strstr(cpu->cpu_name, "i5-8250U") != NULL ||
          strstr(cpu->cpu_name, "i5-8350U") != NULL ||
          strstr(cpu->cpu_name, "i7-8550U") != NULL ||
@@ -425,9 +478,78 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t
     }
     return get_uarch_from_cpuid_intel(ef, f, em, m, s);
   }
-  else
+  else if(cpu->cpu_vendor == CPU_VENDOR_AMD) {
     return get_uarch_from_cpuid_amd(ef, f, em, m, s);
   }
+  else if(cpu->cpu_vendor == CPU_VENDOR_HYGON) {
+    return get_uarch_from_cpuid_hygon(ef, f, em, m, s);
+  }
+  else {
+    printBug("Invalid CPU vendor: %d", cpu->cpu_vendor);
+    return NULL;
+  }
+}
+
+// If we cannot get the CPU name from CPUID, try to infer it from uarch
+char* infer_cpu_name_from_uarch(struct uarch* arch) {
+  char* cpu_name = NULL;
+  if (arch == NULL) {
+    printErr("infer_cpu_name_from_uarch: Unable to find CPU name");
+    cpu_name = ecalloc(strlen(STRING_UNKNOWN) + 1, sizeof(char));
+    strcpy(cpu_name, STRING_UNKNOWN);
+    return cpu_name;
+  }
+
+  char *str = NULL;
+
+  switch (arch->uarch) {
+    // Intel
+    case UARCH_I486:
+      str = "Intel 486";
+      break;
+    case UARCH_P5:
+      str = "Intel Pentium";
+      break;
+    case UARCH_P5_MMX:
+      str = "Intel Pentium MMX";
+      break;
+    case UARCH_P6_PRO:
+      str = "Intel Pentium Pro";
+      break;
+    case UARCH_P6_PENTIUM_II:
+      str = "Intel Pentium II";
+      break;
+    case UARCH_P6_PENTIUM_III:
+      str = "Intel Pentium III";
+      break;
+
+    // AMD
+    case UARCH_AM486:
+      str = "AMD 486";
+      break;
+    case UARCH_AM5X86:
+      str = "AMD 5x86";
+      break;
+    case UARCH_SSA5:
+      str = "AMD 5k86";
+      break;
+
+    default:
+      printErr("Unable to find name from uarch: %d", arch->uarch);
+      break;
+  }
+
+  if (str == NULL) {
+    cpu_name = ecalloc(strlen(STRING_UNKNOWN) + 1, sizeof(char));
+    strcpy(cpu_name, STRING_UNKNOWN);
+  }
+  else {
+    cpu_name = ecalloc(strlen(str) + 1, sizeof(char));
+    strcpy(cpu_name, str);
+  }
+
+  return cpu_name;
+}
 
 bool vpus_are_AVX512(struct cpuInfo* cpu) {
   return cpu->arch->uarch != UARCH_ICE_LAKE &&
@@ -499,9 +621,6 @@ char* get_str_process(struct cpuInfo* cpu) {
   if(process == UNK) {
     snprintf(str, strlen(STRING_UNKNOWN)+1, STRING_UNKNOWN);
   }
-  else if(process > 100) {
-    sprintf(str, "%.2fum", (double)process/100);
-  }
   else if(process > 0){
     sprintf(str, "%dnm", process);
   }

src/x86/uarch.h

@@ -8,6 +8,7 @@
 struct uarch;
 
 struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t dump, uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s);
+char* infer_cpu_name_from_uarch(struct uarch* arch);
 bool vpus_are_AVX512(struct cpuInfo* cpu);
 bool is_knights_landing(struct cpuInfo* cpu);
 int get_number_of_vpus(struct cpuInfo* cpu);