[v1.06][ARM] Added the right ARM version for Apple M2/M3 microarchitectures

* Add Intel and AMD 486, Intel Pentium Pro, and AMD K5 chips
* Update infer_cpu_name_from_uarch to support added CPU uarches
* Add sources for more of the legacy chip data
* Add the more specific codename for Intel Pentium MMX Mobile chips
* Document source of AMD 486/K5 variants
* Add link to documentation for Intel 486

---------

Co-authored-by: Timothy Warren <tim@timshomepage.net>

Makefile

@@ -30,6 +30,10 @@ ifneq ($(OS),Windows_NT)
 			HEADERS += $(SRC_DIR)freq/freq.h
 			CFLAGS += -pthread
 		endif
+		ifeq ($(os), FreeBSD)
+			SOURCE += $(SRC_COMMON)sysctl.c
+			HEADERS += $(SRC_COMMON)sysctl.h
+		endif
 		CFLAGS += -DARCH_X86 -std=c99 -fstack-protector-all
 	else ifeq ($(arch), $(filter $(arch), ppc64le ppc64 ppcle ppc))
 		SRC_DIR=src/ppc/

src/arm/midr.c

@@ -412,6 +412,7 @@ struct cpuInfo* get_cpu_info_mach(struct cpuInfo* cpu) {
     cpu->peak_performance = get_peak_performance(cpu);
   }
   else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
+          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_2   ||
           cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
           cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
     fill_cpu_info_everest_sawtooth(cpu, pcores, ecores);
@@ -448,7 +449,7 @@ char* get_str_topology(struct cpuInfo* cpu, struct topology* topo, bool dual_soc
 
 char* get_str_features(struct cpuInfo* cpu) {
   struct features* feat = cpu->feat;
-  uint32_t max_len = strlen("NEON,SHA1,SHA2,AES,CRC32,SVE,SVE2") + 1;
+  uint32_t max_len = strlen("NEON,SHA1,SHA2,AES,CRC32,SVE,SVE2,") + 1;
   uint32_t len = 0;
   char* string = ecalloc(max_len, sizeof(char));
 

src/arm/soc.c

@@ -895,6 +895,79 @@ struct system_on_chip* guess_soc_from_uarch(struct system_on_chip* soc, struct c
   return soc;
 }
 
+// Return the dt string without the NULL characters.
+char* get_dt_str(char* dt, int filelen) {
+  char* dt_without_null = (char *) malloc(sizeof(char) * filelen);
+  memcpy(dt_without_null, dt, filelen);
+
+  for (int i=0; i < filelen-1; i++) {
+    if (dt_without_null[i] == '\0')
+      dt_without_null[i] = ',';
+  }
+  return dt_without_null;
+}
+
+bool match_dt(struct system_on_chip* soc, char* dt, int filelen, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {
+  // The /proc/device-tree/compatible file (passed by dt) uses NULL
+  // to separate the strings, so we need to make an special case here
+  // and iterate over the NULL characters, thus iterating over each
+  // individual compatible strings.
+
+  if (strstr(dt, expected_name) != NULL) {
+    fill_soc(soc, soc_name, soc_model, process);
+    return true;
+  }
+
+  char *compatible = dt;
+  char *end_of_dt = dt + filelen;
+
+  while ((compatible = strchr(compatible, '\0')) != end_of_dt) {
+    compatible++;
+    if (strstr(compatible, expected_name) != NULL) {
+      fill_soc(soc, soc_name, soc_model, process);
+      return true;
+    }
+  }
+
+  return false;
+}
+
+#define DT_START if (false) {}
+#define DT_EQ(dt, filelen, soc, expected_name, soc_name, soc_model, process) \
+   else if (match_dt(soc, dt, filelen, expected_name, soc_name, soc_model, process)) return soc;
+#define DT_END(dt, filelen) else { printWarn("guess_soc_from_devtree: No match found for '%s'", get_dt_str(dt, filelen)); return soc; }
+
+// TODO: Move this to doc
+// The number of fields seems non-standard, so for now it seems wiser
+// to just get the entire string with all fields and just look for the
+// substring.
+// TODO: Implement this by going trough NULL-separated fields rather than
+// using strstr.
+struct system_on_chip* guess_soc_from_devtree(struct system_on_chip* soc) {
+  int len;
+  char* dt = get_devtree_compatible(&len);
+  if (dt == NULL) {
+    return soc;
+  }
+
+  // The following are internal codenames of Asahi Linux
+  // https://github.com/AsahiLinux/docs/wiki/Codenames
+  DT_START
+  DT_EQ(dt, len, soc, "apple,t8103", "M1",       SOC_APPLE_M1,       5)
+  DT_EQ(dt, len, soc, "apple,t6000", "M1 Pro",   SOC_APPLE_M1_PRO,   5)
+  DT_EQ(dt, len, soc, "apple,t6001", "M1 Max",   SOC_APPLE_M1_MAX,   5)
+  DT_EQ(dt, len, soc, "apple,t6002", "M1 Ultra", SOC_APPLE_M1_ULTRA, 5)
+  DT_EQ(dt, len, soc, "apple,t8112", "M2",       SOC_APPLE_M2,       5)
+  DT_EQ(dt, len, soc, "apple,t6020", "M2 Pro",   SOC_APPLE_M2_PRO,   5)
+  DT_EQ(dt, len, soc, "apple,t6021", "M2 Max",   SOC_APPLE_M2_MAX,   5)
+  DT_EQ(dt, len, soc, "apple,t6022", "M2 Ultra", SOC_APPLE_M2_ULTRA, 5)
+  DT_EQ(dt, len, soc, "apple,t8122", "M3",       SOC_APPLE_M3,       3)
+  DT_EQ(dt, len, soc, "apple,t6030", "M3 Pro",   SOC_APPLE_M3_PRO,   3)
+  DT_EQ(dt, len, soc, "apple,t6031", "M3 Max",   SOC_APPLE_M3_MAX,   3)
+  DT_EQ(dt, len, soc, "apple,t6034", "M3 Max",   SOC_APPLE_M3_MAX,   3)
+  DT_END(dt, len)
+}
+
 struct system_on_chip* guess_soc_from_pci(struct system_on_chip* soc, struct cpuInfo* cpu) {
   struct pci_devices * pci = get_pci_devices();
   if (pci == NULL) {
@@ -1042,10 +1115,12 @@ struct system_on_chip* guess_soc_apple(struct system_on_chip* soc) {
     }
   }
   else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
+          cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_2   ||
           cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO ||
           cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX) {
     // Check M3 version
-    if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH) {
+    if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH ||
+       cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_2) {
       fill_soc(soc, "M3", SOC_APPLE_M3, 3);
     }
     else if(cpu_family == CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO) {
@@ -1103,6 +1178,10 @@ struct system_on_chip* get_soc(struct cpuInfo* cpu) {
       printWarn("SoC detection failed using Android: Found '%s' string", soc->raw_name);
     }
 #endif // ifdef __ANDROID__
+    // If previous steps failed, try with the device tree
+    if (soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
+      soc = guess_soc_from_devtree(soc);
+    }
     // If previous steps failed, try with nvmem
     if(soc->soc_vendor == SOC_VENDOR_UNKNOWN) {
       soc = guess_soc_from_nvmem(soc);

src/arm/uarch.c

@@ -33,6 +33,7 @@ enum {
   ISA_ARMv8_3_A,
   ISA_ARMv8_4_A,
   ISA_ARMv8_5_A,
+  ISA_ARMv8_6_A,
   ISA_ARMv9_A
 };
 
@@ -93,8 +94,10 @@ static const ISA isas_uarch[] = {
   [UARCH_EXYNOS_M5]    = ISA_ARMv8_2_A,
   [UARCH_ICESTORM]     = ISA_ARMv8_5_A, // https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/AArch64TargetParser.def
   [UARCH_FIRESTORM]    = ISA_ARMv8_5_A,
-  [UARCH_BLIZZARD]     = ISA_ARMv8_5_A, // Not confirmed
-  [UARCH_AVALANCHE]    = ISA_ARMv8_5_A,
+  [UARCH_BLIZZARD]     = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
+  [UARCH_AVALANCHE]    = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
+  [UARCH_SAWTOOTH]     = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
+  [UARCH_EVEREST]      = ISA_ARMv8_6_A, // https://github.com/llvm/llvm-project/blob/main/llvm/unittests/TargetParser/TargetParserTest.cpp
   [UARCH_PJ4]          = ISA_ARMv7_A,
   [UARCH_XIAOMI]       = ISA_ARMv8_A,
 };
@@ -112,6 +115,7 @@ static char* isas_string[] = {
   [ISA_ARMv8_3_A] = "ARMv8.3",
   [ISA_ARMv8_4_A] = "ARMv8.4",
   [ISA_ARMv8_5_A] = "ARMv8.5",
+  [ISA_ARMv8_6_A] = "ARMv8.6",
   [ISA_ARMv9_A] = "ARMv9"
 };
 
@@ -248,6 +252,8 @@ struct uarch* get_uarch_from_midr(uint32_t midr, struct cpuInfo* cpu) {
 
   CHECK_UARCH(arch, cpu, 'a', 0x022, NA, NA, "Icestorm",              UARCH_ICESTORM,     CPU_VENDOR_APPLE)
   CHECK_UARCH(arch, cpu, 'a', 0x023, NA, NA, "Firestorm",             UARCH_FIRESTORM,    CPU_VENDOR_APPLE)
+  CHECK_UARCH(arch, cpu, 'a', 0x024, NA, NA, "Icestorm",              UARCH_ICESTORM,     CPU_VENDOR_APPLE)     // https://github.com/Dr-Noob/cpufetch/issues/263
+  CHECK_UARCH(arch, cpu, 'a', 0x025, NA, NA, "Firestorm",             UARCH_FIRESTORM,    CPU_VENDOR_APPLE)     // https://github.com/Dr-Noob/cpufetch/issues/263
   CHECK_UARCH(arch, cpu, 'a', 0x030, NA, NA, "Blizzard",              UARCH_BLIZZARD,     CPU_VENDOR_APPLE)
   CHECK_UARCH(arch, cpu, 'a', 0x031, NA, NA, "Avalanche",             UARCH_AVALANCHE,    CPU_VENDOR_APPLE)
   CHECK_UARCH(arch, cpu, 'a', 0x048, NA, NA, "Sawtooth",              UARCH_SAWTOOTH,     CPU_VENDOR_APPLE)
@@ -269,6 +275,7 @@ bool is_ARMv8_or_newer(struct cpuInfo* cpu) {
          cpu->arch->isa == ISA_ARMv8_3_A       ||
          cpu->arch->isa == ISA_ARMv8_4_A       ||
          cpu->arch->isa == ISA_ARMv8_5_A       ||
+         cpu->arch->isa == ISA_ARMv8_6_A       ||
          cpu->arch->isa == ISA_ARMv9_A;
 }
 

src/common/global.c

@@ -62,7 +62,7 @@
 #endif
 
 #ifndef GIT_FULL_VERSION
-  static const char* VERSION = "1.05";
+  static const char* VERSION = "1.06";
 #endif
 
 enum {

src/common/pci.c

@@ -90,9 +90,9 @@ void populate_pci_devices(struct pci_devices * pci) {
     int path_size = strlen(PCI_PATH) + strlen(dev->path) + 2;
 
     // Read vendor_id
-    char *vendor_id_path = emalloc(sizeof(char) * (path_size + strlen("vendor")));
+    char *vendor_id_path = emalloc(sizeof(char) * (path_size + strlen("vendor") + 1));
     sprintf(vendor_id_path, "%s/%s/%s", PCI_PATH, dev->path, "vendor");
-    
+
     if ((buf = read_file(vendor_id_path, &filelen)) == NULL) {
       printWarn("read_file: %s: %s\n", vendor_id_path, strerror(errno));
       dev->vendor_id = 0;
@@ -102,7 +102,7 @@ void populate_pci_devices(struct pci_devices * pci) {
     }
 
     // Read device_id
-    char *device_id_path = emalloc(sizeof(char) * (path_size + strlen("device")));
+    char *device_id_path = emalloc(sizeof(char) * (path_size + strlen("device") + 1));
     sprintf(device_id_path, "%s/%s/%s", PCI_PATH, dev->path, "device");
 
     if ((buf = read_file(device_id_path, &filelen)) == NULL) {

src/common/sysctl.h

@@ -21,9 +21,12 @@
   #define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D
 #endif
 // M3 / A16 / A17
-// https://ratfactor.com/zig/stdlib-browseable2/c/darwin.zig.html
-// https://github.com/Dr-Noob/cpufetch/issues/210
+// M3:   https://ratfactor.com/zig/stdlib-browseable2/c/darwin.zig.html
+// M3_2: https://github.com/Dr-Noob/cpufetch/issues/230
+// PRO:  https://github.com/Dr-Noob/cpufetch/issues/225
+// MAX:  https://github.com/Dr-Noob/cpufetch/issues/210
 #define CPUFAMILY_ARM_EVEREST_SAWTOOTH     0x8765EDEA
+#define CPUFAMILY_ARM_EVEREST_SAWTOOTH_2   0xFA33415E
 #define CPUFAMILY_ARM_EVEREST_SAWTOOTH_PRO 0x5F4DEA93
 #define CPUFAMILY_ARM_EVEREST_SAWTOOTH_MAX 0x72015832
 
@@ -40,6 +43,14 @@
   #define CPUSUBFAMILY_ARM_HC_HD 5
 #endif
 
+// For alternative way to get CPU frequency on macOS and *BSD
+#ifdef __APPLE__
+  #define CPUFREQUENCY_SYSCTL "hw.cpufrequency_max"
+#else
+  // For FreeBSD, not sure about other *BSD
+  #define CPUFREQUENCY_SYSCTL "dev.cpu.0.freq"
+#endif
+
 uint32_t get_sys_info_by_name(char* name);
 
 #endif

src/common/udev.c

@@ -1,7 +1,10 @@
+#include "../common/global.h"
 #include "udev.h"
 #include "global.h"
 #include "cpu.h"
 
+#define _PATH_DEVTREE          "/proc/device-tree/compatible"
+
 // https://www.kernel.org/doc/html/latest/core-api/cpu_hotplug.html
 int get_ncores_from_cpuinfo(void) {
   // Examples:
@@ -349,3 +352,13 @@ bool is_devtree_compatible(char* str) {
   }
   return true;
 }
+
+char* get_devtree_compatible(int *filelen) {
+  char* buf;
+
+  if ((buf = read_file(_PATH_DEVTREE, filelen)) == NULL) {
+    printWarn("read_file: %s: %s", _PATH_DEVTREE, strerror(errno));
+  }
+
+  return buf;
+}

src/common/udev.h

@@ -43,5 +43,6 @@ int get_num_sockets_package_cpus(struct topology* topo);
 int get_ncores_from_cpuinfo(void);
 char* get_field_from_cpuinfo(char* CPUINFO_FIELD);
 bool is_devtree_compatible(char* str);
+char* get_devtree_compatible(int *filelen);
 
 #endif

src/x86/cpuid.c

@@ -5,6 +5,9 @@
   #include "../common/udev.h"
   #include <unistd.h>
 #endif
+#if defined (__FreeBSD__) || defined (__APPLE__)
+  #include "../common/sysctl.h"
+#endif
 
 #ifdef __linux__
   #include "../common/freq.h"
@@ -938,10 +941,20 @@ struct frequency* get_frequency_info(struct cpuInfo* cpu) {
   freq->measured = false;
 
   if(cpu->maxLevels < 0x00000016) {
-    #if defined (_WIN32) || defined (__APPLE__)
+    #if defined (_WIN32)
       printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000016, cpu->maxLevels);
       freq->base = UNKNOWN_DATA;
       freq->max = UNKNOWN_DATA;
+    #elif defined (__FreeBSD__) || defined (__APPLE__)
+      printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X). Using sysctl", 0x00000016, cpu->maxLevels);
+      uint32_t freq_hz = get_sys_info_by_name(CPUFREQUENCY_SYSCTL);
+      if (freq_hz == 0) {
+        printWarn("Read max CPU frequency from sysctl and got 0 MHz");
+        freq->max = UNKNOWN_DATA;
+      }
+
+      freq->base = UNKNOWN_DATA;
+      freq->max = freq_hz;
     #else
       printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X). Using udev", 0x00000016, cpu->maxLevels);
       freq->base = UNKNOWN_DATA;

src/x86/uarch.c

@@ -47,8 +47,10 @@ typedef uint32_t MICROARCH;
 enum {
   UARCH_UNKNOWN,
   // INTEL //
+  UARCH_I486,
   UARCH_P5,
   UARCH_P5_MMX,
+  UARCH_P6_PRO,
   UARCH_P6_PENTIUM_II,
   UARCH_P6_PENTIUM_III,
   UARCH_DOTHAN,
@@ -97,6 +99,8 @@ enum {
   // AMD //
   UARCH_AM486,
   UARCH_AM5X86,
+  UARCH_SSA5,
+  UARCH_K5,
   UARCH_K6,
   UARCH_K7,
   UARCH_K8,
@@ -149,16 +153,30 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   // ------------------------------------------------------------------------------- //
   //                EF  F  EM   M   S                                                //
   UARCH_START
+  CHECK_UARCH(arch, 0,  4,  0,  0, NA, "i80486DX",          UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  1, NA, "i80486DX-50",       UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  2, NA, "i80486SX",          UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  3, NA, "i80486DX2",         UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  4, NA, "i80486SL",          UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  5, NA, "i80486SX2",         UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  7, NA, "i80486DX2WB",       UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  8, NA, "i80486DX4",         UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  4,  0,  9, NA, "i80486DX4WB",       UARCH_I486,            UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
   CHECK_UARCH(arch, 0,  5,  0,  0, NA, "P5",                UARCH_P5,              800)
   CHECK_UARCH(arch, 0,  5,  0,  1, NA, "P5",                UARCH_P5,              800)
-  CHECK_UARCH(arch, 0,  5,  0,  2, NA, "P5",                UARCH_P5,              UNK)
-  CHECK_UARCH(arch, 0,  5,  0,  3, NA, "P5",                UARCH_P5,              600)
-  CHECK_UARCH(arch, 0,  5,  0,  4, NA, "P5 (MMX)",          UARCH_P5_MMX,          UNK)
-  CHECK_UARCH(arch, 0,  5,  0,  7, NA, "P5 (MMX)",          UARCH_P5_MMX,          UNK)
-  CHECK_UARCH(arch, 0,  5,  0,  8, NA, "P5 (MMX)",          UARCH_P5_MMX,          250)
+  CHECK_UARCH(arch, 0,  5,  0,  2, NA, "P54C",              UARCH_P5,              UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  5,  0,  3, NA, "P24T (Overdrive)",  UARCH_P5,              600) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  5,  0,  4, NA, "P55C (MMX)",        UARCH_P5_MMX,          350) // https://www.cpu-world.com/CPUs/Pentium/TYPE-Pentium%20MMX.html
+  CHECK_UARCH(arch, 0,  5,  0,  7, NA, "P54C",              UARCH_P5,              350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch, 0,  5,  0,  8, NA, "Tillamook",         UARCH_P5_MMX,          250) // http://instlatx64.atw.hu./
   CHECK_UARCH(arch, 0,  5,  0,  9,  0, "Lakemont",          UARCH_LAKEMONT,         32)
   CHECK_UARCH(arch, 0,  5,  0,  9, NA, "P5 (MMX)",          UARCH_P5_MMX,          UNK)
   CHECK_UARCH(arch, 0,  5,  0, 10,  0, "Lakemont",          UARCH_LAKEMONT,         32)
+  CHECK_UARCH(arch, 0,  6,  0,  1,  1, "P6",                UARCH_P6_PRO,          UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  1,  2, "P6",                UARCH_P6_PRO,          UNK)
+  CHECK_UARCH(arch, 0,  6,  0,  1,  6, "P6",                UARCH_P6_PRO,          350)
+  CHECK_UARCH(arch, 0,  6,  0,  1,  7, "P6",                UARCH_P6_PRO,          350)
+  CHECK_UARCH(arch, 0,  6,  0,  1,  9, "P6",                UARCH_P6_PRO,          350)
   CHECK_UARCH(arch, 0,  6,  0,  0, NA, "P6 (Pentium II)",   UARCH_P6_PENTIUM_II,   UNK)
   CHECK_UARCH(arch, 0,  6,  0,  1, NA, "P6 (Pentium II)",   UARCH_P6_PENTIUM_II,   UNK) // process depends on core
   CHECK_UARCH(arch, 0,  6,  0,  2, NA, "P6 (Pentium II)",   UARCH_P6_PENTIUM_II,   UNK)
@@ -279,11 +297,16 @@ struct uarch* get_uarch_from_cpuid_amd(uint32_t ef, uint32_t f, uint32_t em, uin
   // ----------------------------------------------------------------------------- //
   //                 EF  F  EM   M   S                                             //
   UARCH_START
-  CHECK_UARCH(arch,  0,  4,  0,  3, NA, "Am486",       UARCH_AM486,      UNK)
-  CHECK_UARCH(arch,  0,  4,  0,  7, NA, "Am486",       UARCH_AM486,      UNK)
-  CHECK_UARCH(arch,  0,  4,  0,  8, NA, "Am486",       UARCH_AM486,      UNK)
-  CHECK_UARCH(arch,  0,  4,  0,  9, NA, "Am486",       UARCH_AM486,      UNK)
-  CHECK_UARCH(arch,  0,  4, NA, NA, NA, "Am5x86",      UARCH_AM5X86,     UNK)
+  CHECK_UARCH(arch,  0,  4,  0,  3, NA, "Am486DX2",    UARCH_AM486,      UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  4,  0,  7, NA, "Am486DX2WB",  UARCH_AM486,      UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  4,  0,  8, NA, "Am486DX4",    UARCH_AM486,      UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  4,  0,  9, NA, "Am486DX4WB",  UARCH_AM486,      UNK) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  4,  0, 14, NA, "Am5x86",      UARCH_AM5X86,     350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  4,  0, 15, NA, "Am5x86WB",    UARCH_AM5X86,     350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  5,  0,  0, NA, "SSA5 (K5)",   UARCH_SSA5,       350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  5,  0,  1, NA, "K5",          UARCH_K5,         350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  5,  0,  2, NA, "K5",          UARCH_K5,         350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
+  CHECK_UARCH(arch,  0,  5,  0,  3, NA, "K5",          UARCH_K5,         350) // https://sandpile.org/x86/cpuid.htm#level_0000_0001h
   CHECK_UARCH(arch,  0,  5,  0,  6, NA, "K6",          UARCH_K6,         300)
   CHECK_UARCH(arch,  0,  5,  0,  7, NA, "K6",          UARCH_K6,         250) // *p from sandpile.org
   CHECK_UARCH(arch,  0,  5,  0, 10, NA, "K7",          UARCH_K7,         130) // Geode NX
@@ -479,16 +502,42 @@ char* infer_cpu_name_from_uarch(struct uarch* arch) {
 
   char *str = NULL;
 
-  if (arch->uarch == UARCH_P5)
-    str = "Intel Pentium";
-  else if (arch->uarch == UARCH_P5_MMX)
-    str = "Intel Pentium MMX";
-  else if (arch->uarch == UARCH_P6_PENTIUM_II)
-    str = "Intel Pentium II";
-  else if (arch->uarch == UARCH_P6_PENTIUM_III)
-    str = "Intel Pentium III";
-  else
-    printErr("Unable to find name from uarch: %d", arch->uarch);
+  switch (arch->uarch) {
+    // Intel
+    case UARCH_I486:
+      str = "Intel 486";
+      break;
+    case UARCH_P5:
+      str = "Intel Pentium";
+      break;
+    case UARCH_P5_MMX:
+      str = "Intel Pentium MMX";
+      break;
+    case UARCH_P6_PRO:
+      str = "Intel Pentium Pro";
+      break;
+    case UARCH_P6_PENTIUM_II:
+      str = "Intel Pentium II";
+      break;
+    case UARCH_P6_PENTIUM_III:
+      str = "Intel Pentium III";
+      break;
+
+    // AMD
+    case UARCH_AM486:
+      str = "AMD 486";
+      break;
+    case UARCH_AM5X86:
+      str = "AMD 5x86";
+      break;
+    case UARCH_SSA5:
+      str = "AMD 5k86";
+      break;
+
+    default:
+      printErr("Unable to find name from uarch: %d", arch->uarch);
+      break;
+  }
 
   if (str == NULL) {
     cpu_name = ecalloc(strlen(STRING_UNKNOWN) + 1, sizeof(char));