[0.95][x86] Print output to a file instead of printing it to stdout

README.md

@@ -4,38 +4,34 @@ Simplistic yet fancy CPU architecture fetching tool
 ![cpu1](pictures/i9.png)
 
 ### Platforms
-cpufetch currently supports x86_64 CPUs (both Intel and AMD) and ARM (experimental support)
+cpufetch currently supports x86_64 CPUs (both Intel and AMD) and ARM.
 
-| Platform  | Intel                     | AMD                      | ARM                      | Notes             |
-|:---------:|:-------------------------:|:------------------------:|:------------------------:|:-----------------:|
-| Linux     | :heavy_check_mark:        | :heavy_check_mark:       | :heavy_check_mark:       | Prefered platform. <br> Experimental ARM support |
-| Windows   | :heavy_check_mark:        | :heavy_check_mark:       | :x:                      | Some information may be missing. <br> Colors will be used if supported |
-| Android   | :heavy_exclamation_mark:  | :heavy_exclamation_mark: | :heavy_check_mark:       | Experimental ARM support |
-| macOS     | :heavy_exclamation_mark:  | :heavy_exclamation_mark: | :heavy_exclamation_mark: | Untested |
+| Platform  | x86_64                    | ARM                | Notes             |
+|:---------:|:------------------------:|:-------------------:|:-----------------:|
+| Linux     | :heavy_check_mark:        | :heavy_check_mark: | Prefered platform. <br> Experimental ARM support |
+| Windows   | :heavy_check_mark:        | :x:                | Some information may be missing. <br> Colors will be used if supported |
+| Android   | :heavy_exclamation_mark:  | :heavy_check_mark: | Experimental ARM support |
+| macOS     | :heavy_check_mark:        | :x:                | Some information may be missing |
 
 | Emoji                   | Meaning       |
 |:-----------------------:|:-------------:|
 |:heavy_check_mark:       | Supported     |
-|:x:                      | Not Supported |
-|:heavy_exclamation_mark: | Unested       |
-
-
+|:x:                      | Not supported |
+|:heavy_exclamation_mark: | Not tested    |
 
 
 ### Usage and installation
 #### Linux
 There is a cpufetch package available in Arch Linux ([cpufetch-git](https://aur.archlinux.org/packages/cpufetch-git)).
 
-If you are in other distro, you can build `cpufetch` from source (see below)
+If you are in another distro, you can build `cpufetch` from source (see below)
 
 #### Windows
 In the [releases](https://github.com/Dr-Noob/cpufetch/releases) section you will find some cpufetch executables compiled for Windows. Just download and run it from Windows CMD.
 
-#### Android
-You need to build `cpufetch` from source (see below).
+#### Building from source
+Just clone the repo and use `make` to compile it
 
-### Building from source
-#### Linux and Windows
 ```
 git clone https://github.com/Dr-Noob/cpufetch
 cd cpufetch
@@ -43,25 +39,23 @@ make
 ./cpufetch
 ```
 
-#### Android
-I recommend using `termux` terminal emulator. Once you installed it, run the following commands:
-
-```
-pkg install -y git make clang
-git clone https://github.com/Dr-Noob/cpufetch
-cd cpufetch
-make
-./cpufetch
-```
+The Makefile is designed to work on both Linux and Windows.
 
 ### Examples
-
 Here are more examples of how `cpufetch` looks on different CPUs.
 
+##### x86_64 CPUs
+
 ![cpu2](pictures/epyc.png)
 
 ![cpu3](pictures/cascade_lake.png)
 
+##### ARM CPUs
+
+![cpu4](pictures/exynos.png)
+
+![cpu5](pictures/snapdragon.png)
+
 ### Colors and style
 By default, `cpufetch` will print the CPU art with the system colorscheme. However, you can always set a custom color scheme, either
 specifying Intel or AMD, or specifying the colors in RGB format:
@@ -76,10 +70,10 @@ In the case of setting the colors using RGB, 4 colors must be given in with the
 
 ### Implementation
 
-`cpufetch` fetches all of the information using the `CPUID` x86 instruction. There are, however, some cases where the CPU does not support fetching some needed information. In this case, `cpufetch` will use `/sys/devices/system/cpu` in Linux as a fallback. If `cpufetch` is running on Windows and `CPUID` does not give all the data, `cpufetch` won't be able to show it. [I hope this can be fixed in the future](https://github.com/Dr-Noob/cpufetch/issues/30)
+See [cpufetch programming documentation](https://github.com/Dr-Noob/cpufetch/blob/master/doc/README.md).
 
 ### Bugs or improvements
-There are many open issues in github (see [issues](https://github.com/Dr-Noob/cpufetch/issues)). Feel free to open a new one report a issue or propose any improvement in `cpufetch`
+There are many open issues in github (see [issues](https://github.com/Dr-Noob/cpufetch/issues)). Feel free to open a new one report an issue or propose any improvement in `cpufetch`
 
-### Testers
-I would like to thank [Gonzalocl](https://github.com/Gonzalocl) and [OdnetninI](https://github.com/OdnetninI) for their help, running `cpufeth` in many different CPUs they have access to, which makes it easier to debug and check the correctness of `cpufetch`.
+### Testing
+I would like to thank [Gonzalocl](https://github.com/Gonzalocl) and [OdnetninI](https://github.com/OdnetninI) for their help, running `cpufetch` in many different CPUs they have access to, which makes it easier to debug and check the correctness of `cpufetch`.

doc/DOCUMENTATION_ARM.md

@@ -1,2 +1,60 @@
 ### 2. Why ARM cpufetch works on Linux based systems?
-TODO
+CPUID instructions (present in x86 architectures) [[1](#references)] allow user level applications to obtain information about the CPU. In ARM architectures, there are many registers (MIDR [[2](#references)], CCSIDR [[3](#references)]) that provide information about the CPU too. However, those registers can only be read from privilege mode (PL1 or higher). Therefore, any user level tool which can actually read information about the running CPU must use the operating system to do so. cpufetch uses some Linux kernel features (see the remaining sections). Therefore, cpufetch in ARM processors is limited to Linux kernel based systems, such as __GNU/Linux__ and __Android__
+
+### 3. How to get CPU microarchitecture?
+__Involved code: [get_midr_from_cpuinfo (udev.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/arm/udev.c), [midr.c](https://github.com/Dr-Noob/cpufetch/blob/master/src/arm/midr.c)__
+
+Microarchitecture information is acquired from the Main ID Register (MIDR) [[2](#references)]. Currently, cpufetch rebuilds this register using `/proc/cpuinfo` file. While this file does not contain the value of the register per se, it contains the following fields:
+- `CPU implementer`,
+- `CPU architecture`
+- `CPU variant`
+- `CPU part`
+- `CPU revision`
+
+The MIDR register can be built with this information. Another posible approach is to read MIDR directly from `/sys/devices/system/cpu/cpu*/regs/identification/midr_el1`
+
+With the MIDR available, the approach is the same as the one used in x86_64 architectures. cpufetch has a file that acts like a database that tries to match the MIDR register with the specific CPU microarchitecture.
+
+### 4. How to get CPU topology?
+__Involved code: [get_ncores_from_cpuinfo (udev.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/arm/udev.c), [midr.c](https://github.com/Dr-Noob/cpufetch/blob/master/src/arm/midr.c)__
+
+ARM provides a new interesting architecture feature: big.LITTLE architectures [[4](#references)]. An ARM CPU can be organized like a typical x86_64 CPU, where all cores share the same microarchitecture. However, ARM big.LITTLE architecture breaks this schema. In a big.LITTLE CPU, two or more CPUs microarchitecture live in the same chip.
+
+This means that cpufetch can't just read which microarchitecture is the first core and assume that the rest of them shares the same microarchitecture. To get the CPU topology, cpufetch first reads the number of CPU cores. This can be obtained from `/sys/devices/system/cpu/present`
+
+Then, for each core, cpufetch reads the MIDR and also the frequency (see section 5). Then, cpufetch assumes that two cores are different when their MIDR are different. This idea allows cpufetch to detect big.LITTLE architectures, and to know how many cores of each architecture the running CPU has.
+
+### 5. How to get the frequency?
+Frequency is read directly from `/sys/devices/system/cpu/cpu*/cpufreq/cpuinfo_max_freq`
+
+### 6. How to get system on chip model?
+__Involved code: [soc.c](https://github.com/Dr-Noob/cpufetch/blob/master/src/arm/soc.c)__
+
+System on chip (SoC) model is obtained using the same idea as the microarchitecture. First, SoC string is read. Then, the string has to be matched against a database-like function (__parse_soc_from_string__). The SoC string of the running CPU can be obtained using two different approaches:
+
+- Using `/proc/cpuinfo`. This is the first thing to try. Linux kernel usually provides the string under the `Hardware` keyword. However, the Linux kernel may be unable to provide this information, or this string may not be found in the database-like function.
+- Using Android properties: This only works on Android systems. Android properties can be read using `__system_property_get` function. cpufetch tries to read two properties:
+  - `ro.mediatek.platform`
+  - `ro.product.board`
+
+  If any string is returned, cpufetch tries to find a match in the database (using the same database as in the case of `/proc/cpuinfo`).
+
+The expected strings have to be hardcoded. I found two ways of knowing which string should correspond to which SoC:
+
+  - Searching on the internet. Manufacturers __usually__ provide this information. For example, Qualcomm usually publishes the chip name along with other characteristics (under the `Part` or `Part number` keyword [[6](#references)]).
+  - "Hunting" for the strings. For example, finding smartphones with a given SoC and manually reading the `/proc/cpuinfo` or the `build.prop` file. A very good resource to do this is the SpecDevice webpage [[7](#references)]).
+
+### 7. How to get cache size and topology?
+ARM architecture supports reading the cache information via some registers (for example, the CCSIDR register  [[3](#references)]). As mentioned earlier, user level applications are not able to read these registers directly. The remaining option is to ask the operating system for this information. However, at the moment, the __Linux kernel does not provide cache information__. Therefore, cpufetch does not print any cache information on ARM CPUs at the moment. There are, however, other approaches to be explored:
+
+- Read the registers in kernel mode. This can be accomplished by running a kernel module [[4](#references)]. Unfortunately, running a custom kernel module is tricky, and sometimes impossible to do reasonably (for example, in Android devices). In any case, my decision is to run cpufetch on user level only.
+- Hardcode the cache information for each SoC: Sometimes, manufacturers publish technical information about the chips, where cache topology and size are shown. This method is impractical, since this kind of information is very hard (or impossible) to find online, and the number of SoC is huge.
+
+#### References
+- [1] [cpufetch x86_64 documentation](https://github.com/Dr-Noob/cpufetch/blob/master/doc/DOCUMENTATION_X86.md)
+- [2] [Main ID Register](https://developer.arm.com/documentation/ddi0433/c/system-control/register-descriptions/main-id-register)
+- [3] [Cache size ID Register](https://developer.arm.com/documentation/100403/0200/register-descriptions/aarch32-system-registers/ccsidr--cache-size-id-register)
+- [4] [How to get the size of the CPU cache in Linux](https://stackoverflow.com/a/63474811/9975463)
+- [5] [ARM big.LITTLE](https://en.wikipedia.org/wiki/ARM_big.LITTLE)
+- [6] [Snapdragon 855+ Mobile Platform](https://www.qualcomm.com/products/snapdragon-855-plus-mobile-platform)
+- [7] [SpecDevice](http://specdevice.com/unmoderated.php)

doc/DOCUMENTATION_X86.md

@@ -1,40 +1,38 @@
 ### 2. Why differences between Intel and AMD?
-There are many different CPUID leaves (see [Useful documentation](#useful-documentation)). However, there are cases where a given leaf does the same thing in Intel and AMD, but the majority of them, they don't. For example, leaf 0x4 gives you the caches information, but in
-AMD is a reserved (invalid) leaf! In the case of AMD, is more common to fetch information using extended levels than using the standard levels (the other way around with Intel).
+There are many different CPUID leaves [[1](#references)]. In some cases, a given leaf does the same thing in Intel and AMD processors, but in the majority of them, they don't. For example, leaf 0x4 gives you the caches information, but in AMD is a reserved (invalid) leaf! In the case of AMD, is more common to fetch information using extended levels than using the standard levels (the other way around with Intel).
 
 ### 3. How to get the frequency?
-__Involved code: get_frequency_info (cpuid.c)__
+__Involved code: [get_frequency_info (cpuid.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/cpuid.c)__
 
-We use CPUID leaf 0x16.
+CPUID leaf 0x16 is used.
 
-If the CPU supports it, we are done. If not:
-- Linux: cpufetch will try to obtain this information using `/sys` filesystem in Linux. I think that, in this case, Linux knows the frequency using MSRs, so at the user level you can't know it, but I will look at the kernel source code to check it.
-- Windows: We are dead. cpufetch can't fetch CPU frequency. This means that peak performance can't be computed because the frequency is needed to compute it.
+If the CPU does not support supports such level:
+- Linux: cpufetch will try to obtain this information using `/sys` filesystem in Linux. I think that Linux knows the frequency using model specific registers (MSRs), which you can't read at the user level.
+- Windows: cpufetch can't obtain CPU frequency. This means that peak performance can't be computed because the frequency is needed to compute it.
 
 ### 4. How to get cache sizes?
-__Involved code: get_cache_info (cpuid.c)__
+__Involved code: [get_cache_info (cpuid.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/cpuid.c)__
 
-- Intel: We use CPUID leaf 0x4
-- AMD: We use extended CPUID leaf 0x1D
+- Intel: CPUID leaf 0x4 is used (using __get_cache_info_general__). If the CPU does not support it, cpufetch can't get this information.
+- AMD: Extended CPUID leaf 0x1D is used (using __get_cache_info_general__). If the CPU does not support this level, cpufetch uses a fallback method, which uses extended leaves 0x5 and 0x6. This fallback method uses __get_cache_info_amd_fallback__.
 
-If CPU does not support it, we are dead: cpufetch can't get this information. If CPU does, we can fetch it, and 0x4 in Intel behaves the same way as 0x1D in AMD.
 
 ### 5. How to get CPU microarchitecture?
-__Involved code: get_cpu_uarch (cpuid.c), get_uarch_from_cpuid (uarch.c)__
+__Involved code: [get_cpu_uarch (cpuid.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/cpuid.c), [get_uarch_from_cpuid (uarch.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/uarch.c)__
 
-We use CPUID leaf 0x1. From there, we get:
+CPUID leaf 0x1 is used. From there, we get:
 - Model
 - Extended Model
 - Family
 - Extended Family
 - Stepping
 
-Knowing this information, we can distinguish any CPU microarchitecture. Inside __uarch.c__ there is a function that behaves as it had a database. It will search, for this information, what kind of microarchitecture the current CPU is. I got the data using and adapting the code form Todd Allen's cpuid program (Link 5 in [Useful documentation](#useful-documentation)). From the microarchitecture, we can obtain the manufacturing process (or technology, the size in nm of the transistors).
+Knowing this information, we can distinguish any CPU microarchitecture. Inside __uarch.c__ there is a function that behaves like a database or a lookup table. The function of this database is to find a match between the information obtained from 0x1 and what kind of microarchitecture the current CPU is. I got the data using and adapting the code from Todd Allen's cpuid program [[5](#references)]. Knowing the microarchitecture, we can obtain the manufacturing process (or technology, the size in nm of the transistors).
 
 ### 6. How to get CPU topology?
-__Involved code: cpuid.h, get_topology_info (cpuid.c), apic.c__
+__Involved code: [cpuid.h](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/cpuid.h), [get_topology_info (cpuid.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/cpuid.c), [apic.c](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/apic.c)__
 
-cpufetch tries to support the most complex systems, so it supports multi socket CPUs and a detailed SMT (Intel HyperThreading) information. The CPU topology is stored like this:
+cpufetch aims to support the most complex systems, so it supports multi-socket CPUs and detailed SMT (Intel HyperThreading) information. The CPU topology is stored in the following struct:
 
 ```
 struct topology {
@@ -52,7 +50,7 @@ This structure needs a bit of explanation, to know what are we looking for:
 - `logical_cores`: Number of logical cores. In a multi socket system, this field stores the number of logical cores for just one socket.
 - `total_cores`: Total number of logical cores. In a multi socket system, this field stores the number of logical cores for the entire system.
 - `sockets`: How many sockets the system has.
-- `smt_supported`: Stores if SMT (or Intel HT) is supported in the CPU, storing the number of threads per core. So, if `smt_supported == 1`, it means that there is 1 thread per core, and SMT is not supported. If SMT is supported, then `smt_supported >= 1`. Note this field tells if CPU if supports it, but not if SMT is activated or not.
+- `smt_supported`: Stores if SMT (or Intel HT) is supported in the CPU, storing the number of threads per core. So, if `smt_supported == 1`, it means that there is 1 thread per core, and SMT is not supported. If SMT is supported, then `smt_supported >= 1`. Note this field tells if the CPU if supports it, but not if SMT is activated or not.
 - `smt_available`: The same idea as `smt_supported`, but it stores if SMT is available. If SMT is not supported, then `smt_available` is always `1`. The differentiation between supported and available lets cpufetch distinguish when a CPU has SMT capabilities, but are disabled (probably in the BIOS).
 
 Let's give two CPU examples and the values that `struct topology` would have in these CPUs.
@@ -80,8 +78,8 @@ sockets = 1
 
 Now that we know what data are we looking for, let's see how we get it:
 
-- __Intel__: We use the methodology explained in the Intel webpage (Link 2 in [Useful documentation](#useful-documentation)). Here, Intel explains how to do it and also gives an example source code. I used it and modified it to fit cpufetch style. The core of this methodology is the usage of the APIC id, so the code is inside __apic.c__.
-- __AMD__: Intel's algorithm using APIC does not work for AMD. To get the same information in AMD, I used the reference from OSdev(Link 3 in [Useful documentation](#useful-documentation)) and also ideas from lscpu(Link 4 in [Useful documentation](#useful-documentation)). This uses:
+- __Intel__: The methodology used is explained in the Intel webpage [[2](#references)]. Intel explains how to do it and also gives an example source code. I used it and modified it to fit cpufetch style. The core of this methodology is the usage of the APIC id, so the code is inside __apic.c__.
+- __AMD__: Intel's algorithm using APIC does not work for AMD. To get the same information in AMD, I used the reference from OSdev [[3](#references)] and also ideas from lscpu [[4](#references)]. This uses:
   - CPUID extended leaf 0x8: Fill `logical_cores`
   - CPUID extended leaf 0x1E: Fill `smt_supported`
   - CPUID standard leaf 0x1 (APIC): Fill `smt_available`
@@ -97,25 +95,26 @@ Now that we know what data are we looking for, let's see how we get it:
   ```
 
 ### 7. How to get cache topology?
-__Involved code: get_cache_topology_amd (cpuid.c), apic.c__
+__Involved code: [get_cache_topology_amd (cpuid.c)](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/cpuid.c), [apic.c](https://github.com/Dr-Noob/cpufetch/blob/master/src/x86/apic.c)__
 
-The topology is reduced to the idea of how many caches we have at a given level. It usually follows the rule of:
+The topology of a cache gives us information about how many caches we have at a given level. It usually follows the rule of:
 - L1: The same as the number of cores (one L1i and one L1d per core).
 - L2: If L2 is the last level cache, one L2. If not, the same as the number of cores (one L2 per core).
 - L3: One L3 cache per socket (shared among all cores).
 
-These assumptions are generally (but not always) true. For example, for the AMD Zen generation, or the Intel Xeon Phi KNL. Thus, cpufetch does not assume the topology and tries to fetch it instead.
+These assumptions are generally (but not always) true. For example, for the AMD Zen generation, or the Intel Xeon Phi KNL. Thus, cpufetch does not assume the topology but obtains it instead.
 
-- __Intel__: We can use the methodology explained in the Intel webpage (Link 2 in [Useful documentation](#useful-documentation)) again (it also covers how to get cache topology using APIC id).
+- __Intel__: The idea is similar to the mentioned in CPU topology [[2](#references)](it also covers how to get cache topology using APIC id).
 
-- __AMD__: Again, we have to look another path for AMD. This time, the way to do it is easier and (I think) more solid and future proof. We just use extended CPUID leaf 0x1D. If the CPU does not support it, we can still guess the topology of the caches (as mentioned earlier). If it does, CPUID can give us how many cores shares a given level of cache. So, if we have the number of cores, we can guess how many caches are there for any given level (see __get_cache_topology_amd__).
+- __AMD__: Again, we have to look for another path for AMD. This time, the way to do it is easier and (I think) more solid and future proof. The idea is to use extended CPUID leaf 0x1D. If the CPU does not support it, we can still guess the topology of the caches (as mentioned earlier). If it does, CPUID can give us how many cores shares a given level of cache. So, if we have the number of cores, we can guess how many caches are there for any given level (see __get_cache_topology_amd__).
 
-#### Useful documentation
-- Link 1: [sandpile CPUID webpage](https://www.sandpile.org/x86/cpuid.htm)
-- Link 2: [CPU topology and cache topology: Intel](https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html)
-- Link 3: [CPU topology: AMD](https://wiki.osdev.org/Detecting_CPU_Topology_(80x86))
-- Link 4: [lscpu](https://github.com/karelzak/util-linux/blob/master/sys-utils/lscpu.c)
-- Link 5: [Todd Allen's cpuid](http://www.etallen.com/cpuid.html)
-- Link 6: [AMD specific CPUID specification](https://www.amd.com/system/files/TechDocs/25481.pdf)
+#### References
+- [1] [sandpile CPUID webpage](https://www.sandpile.org/x86/cpuid.htm)
+- [2] [CPU topology and cache topology: Intel](https://software.intel.com/content/www/us/en/develop/articles/intel-64-architecture-processor-topology-enumeration.html)
+- [3] [CPU topology: AMD](https://wiki.osdev.org/Detecting_CPU_Topology_(80x86))
+- [4] [lscpu](https://github.com/karelzak/util-linux/blob/master/sys-utils/lscpu.c)
+- [5] [Todd Allen's cpuid](http://www.etallen.com/cpuid.html)
+- [6] [AMD specific CPUID specification](https://www.amd.com/system/files/TechDocs/25481.pdf)
+- [7] [Intel vs AMD CPU Architectural Differences: Chips and Chiplets](https://c.mi.com/thread-2585048-1-0.html)
 
-In addition to all these resources, I found very interesting to search in the Linux kernel source code (for example, the directory `arch/x86/kernel/cpu/`), because sometetimes you can find ideas that cannot be found anywhere else!
+In addition to all these resources, I found it very interesting to search in the Linux kernel source code (for example, the directory [`arch/x86/kernel/cpu/`](https://elixir.bootlin.com/linux/latest/source/arch/x86/kernel/cpu)), because sometimes you can find ideas that cannot be found anywhere else!

doc/README.md

@@ -1,12 +1,15 @@
-# cpufetch programming documentation (v0.88)
-This documentation explains how cpufetch works internally and all the design decisions I made. The intention of this documentation is to be useful for me in the future, for everyone interested in the project, and for anyone who is trying to obtain any specific information from the CPU. In this way, this can be used as a manual or a page which collects interesting material in this area.
+# cpufetch programming documentation (v0.94)
+This documentation explains how cpufetch works internally and all the design decisions I made. This document intends to be useful for me in the future, for everyone interested in the project, and for anyone who is trying to obtain any specific information from the CPU. In this way, this can be used as a manual or a page that collects interesting material in this area.
 
 ### 1. Basics
-cpufetch works for __x86_64__ CPUs (Intel and AMD) and experimental support for __ARM__. Other kinds of x86_64 CPU are not supported (I don't think supporting other CPUs may pay off). Depending on the architecture, cpufetch choose certain files to be compiled. A summarized tree of the source code of cpufetch is shown below.
+cpufetch works for __x86_64__ (Intel and AMD) and  __ARM__ CPUs. However, cpufetch is expected to work better on x86_64, because the codebase is older and has been tested much more than the ARM version. Other kinds of x86_64 CPU are not supported (I don't think supporting other CPUs may pay off). Depending on the architecture, cpufetch choose certain files to be compiled. A summarized tree of the source code of cpufetch is shown below.
 
 ```
 cpufetch/
-├── DOCUMENTATION.md
+├── doc
+│   ├── DOCUMENTATION_ARM.md
+│   ├── DOCUMENTATION_X86.md
+│   └── README.md
 ├── Makefile
 ├── README.md
 └── src/
@@ -22,17 +25,17 @@ cpufetch/
         └── other files ...
 ```
 
-Source code is divided in three directories:
+Source code is divided into three directories:
 
-- `common/`: Source code shared beteen x86 and ARM
+- `common/`: Source code shared between x86 and ARM
 - `arm/`: ARM dependant source code
 - `x86/`: x86_64 dependant source code
 
 ##### 1.1 Basics (x86_64)
 
-In x86, __cpufetch works using the CPUID instruction__. It is called directly using assembly (see `src/x86/cpuid_asm.c`). To understand how CPUID works you may have a look at the [Useful documentation](https://github.com/Dr-Noob/cpufetch/blob/master/DOCUMENTATION_x86.md#useful-documentation) section (more precisely, Link 1).
+In x86, __cpufetch works using the CPUID instruction__. It is called directly using assembly (see `src/x86/cpuid_asm.c`). To understand how CPUID works, see [DOCUMENTATION_X86.md](https://github.com/Dr-Noob/cpufetch/blob/master/doc/DOCUMENTATION_X86.md).
 
-At the beginning of execution, cpufetch needs to know the max standard CPUID level and max CPUID extended level supported in the running CPU. We also need to know if the x86 CPU is Intel or AMD because some fetching depends on it. This information will be stored in:
+At the beginning of execution, cpufetch needs to know the max standard CPUID level and max CPUID extended level supported in the running CPU. We also need to know if the x86 CPU is Intel or AMD because sometimes, the way to obtain the information depends on the manufacturer. This information will be stored in:
 
 ```
 struct cpuInfo {
@@ -44,13 +47,13 @@ struct cpuInfo {
 };
 ```
 
-To use any CPUID leaf, we always need to check that it is supported in the current CPU. cpufetch will always check if the leaf is supported in the current CPU, and will use a different workaround if the CPU is Intel or AMD, which leads us to the following section.
+To use any CPUID leaf, cpufetch always needs to check that it is supported in the current CPU.
 
 ##### 1.2 Basics (ARM)
-In ARM, __cpufetch works using the MIDR register and Linux filesystem__. MIDR (Main ID Register) is fetched from `/proc/cpuinfo`. It allows the detection of the microarchitecture of the cores. Furthermore, Linux filesystem `/sys/devices/system/cpu/` is used to fetch the number of cores, and other information. This is the main reason to explain __why `cpufetch` only works on Linux kernel based systems.__
+In ARM, __cpufetch works using the MIDR register and Linux filesystem__. MIDR (Main ID Register) is read from `/proc/cpuinfo`. It allows the detection of the microarchitecture of the cores. Furthermore, Linux filesystem `/sys/devices/system/cpu/` is used to fetch the number of cores and other information. This is the main reason to explain __why `cpufetch` only works on Linux kernel based systems.__
 
 ##### 1.3 Documentation organization
-The rest of the documentation is divided into x86 and ARM architectures, since each one need different implementations:
+The rest of the documentation is divided into x86 and ARM architectures since each one needs different implementations:
 
 - [DOCUMENTATION_X86.md](https://github.com/Dr-Noob/cpufetch/blob/master/doc/DOCUMENTATION_X86.md)
 - [DOCUMENTATION_ARM.md](https://github.com/Dr-Noob/cpufetch/blob/master/doc/DOCUMENTATION_ARM.md)

src/arm/midr.c

@@ -52,7 +52,7 @@ struct frequency* get_frequency_info(uint32_t core) {
   struct frequency* freq = malloc(sizeof(struct frequency));
 
   freq->base = UNKNOWN_FREQ;
-  freq->max = get_max_freq_from_file(core);
+  freq->max = get_max_freq_from_file(core, false);
 
   return freq;
 }
@@ -186,7 +186,7 @@ struct cpuInfo* get_cpu_info() {
       midr_array[i] = midr_array[0];
     }
     
-    freq_array[i] = get_max_freq_from_file(i);
+    freq_array[i] = get_max_freq_from_file(i, false);
     if(freq_array[i] == UNKNOWN_FREQ) {
       printWarn("Unable to fetch max frequency for core %d. This is probably because the core is offline", i);
       freq_array[i] = freq_array[0];
@@ -306,7 +306,7 @@ void print_debug(struct cpuInfo* cpu) {
   
   for(int i=0; i < ncores; i++) {
     printf("[Core %d] ", i);
-    long freq = get_max_freq_from_file(i);
+    long freq = get_max_freq_from_file(i, false);
     uint32_t midr = get_midr_from_cpuinfo(i, &success);
     if(!success) {
       printWarn("Unable to fetch MIDR for core %d. This is probably because the core is offline", i);
@@ -317,7 +317,7 @@ void print_debug(struct cpuInfo* cpu) {
     }
     if(freq == UNKNOWN_FREQ) {
       printWarn("Unable to fetch max frequency for core %d. This is probably because the core is offline", i);
-      printf("%ld MHz\n", get_max_freq_from_file(0));
+      printf("%ld MHz\n", get_max_freq_from_file(0, false));
     }
     else {
       printf("%ld MHz\n", freq);    

src/common/main.c

@@ -13,7 +13,7 @@
   #include "../arm/midr.h"
 #endif
 
-static const char* VERSION = "0.94";
+static const char* VERSION = "0.95";
 
 void print_help(char *argv[]) {
   printf("Usage: %s [--version] [--help] [--debug] [--style \"fancy\"|\"retro\"|\"legacy\"] [--color \"intel\"|\"amd\"|'R,G,B:R,G,B:R,G,B:R,G,B']\n\n", argv[0]);
@@ -51,7 +51,7 @@ NOTES: \n\
 }
 
 void print_version() {
-  printf("cpufetch v%s (%s)\n",VERSION, ARCH_STR);
+  printf("cpufetch v%s (%s) [outfile branch]\n",VERSION, ARCH_STR);
 }
 
 int main(int argc, char* argv[]) {

src/common/printer.c

@@ -22,6 +22,7 @@
 #include <Windows.h>
 #endif
 
+#define OUTPUT_FILE "cpufetch.txt"
 #define max(a,b) (((a)>(b))?(a):(b))
 #define MAX_ATTRIBUTES      100
 
@@ -346,43 +347,43 @@ uint32_t longest_attribute_length(struct ascii* art) {
 }
 
 #ifdef ARCH_X86
-void print_algorithm_intel(struct ascii* art, int n, bool* flag) {
+void print_algorithm_intel(FILE *file, struct ascii* art, int n, bool* flag) {
   for(int i=0; i < LINE_SIZE; i++) {
     if(*flag) {
       if(art->art[n][i] == ' ') {
         *flag = false;
-        printf("%s%c%s", art->color2_ascii, art->ascii_chars[1], art->reset);
+        fprintf(file, "%s%c%s", art->color2_ascii, art->ascii_chars[1], art->reset);
       }
       else {
-        printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
+        fprintf(file, "%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
       }
     }
     else {
       if(art->art[n][i] != ' ' && art->art[n][i] != '\0') {
         *flag = true;
-        printf("%c",' ');
+        fprintf(file, "%c",' ');
       }
       else {
-        printf("%c",' ');
+        fprintf(file, "%c",' ');
       }
     }
   }
 }
 
-void print_algorithm_amd(struct ascii* art, int n, bool* flag) {
+void print_algorithm_amd(FILE *file, struct ascii* art, int n, bool* flag) {
   *flag = false; // dummy, just silence compiler error
   
   for(int i=0; i < LINE_SIZE; i++) {
     if(art->art[n][i] == '@')
-      printf("%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
+      fprintf(file, "%s%c%s", art->color1_ascii, art->ascii_chars[0], art->reset);
     else if(art->art[n][i] == '#')
-      printf("%s%c%s", art->color2_ascii, art->ascii_chars[1], art->reset);
+      fprintf(file, "%s%c%s", art->color2_ascii, art->ascii_chars[1], art->reset);
     else
-      printf("%c",art->art[n][i]);
+      fprintf(file, "%c",art->art[n][i]);
   }
 }
 
-void print_ascii_x86(struct ascii* art, uint32_t la, void (*callback_print_algorithm)(struct ascii* art, int i, bool* flag)) {  
+void print_ascii_x86(FILE *file, struct ascii* art, uint32_t la, void (*callback_print_algorithm)(FILE *file, struct ascii* art, int i, bool* flag)) {  
   int attr_to_print = 0;
   int attr_type;
   char* attr_value;
@@ -391,9 +392,9 @@ void print_ascii_x86(struct ascii* art, uint32_t la, void (*callback_print_algor
   uint32_t space_down = NUMBER_OF_LINES - art->n_attributes_set - space_up;
   bool flag = false;
 
-  printf("\n");
+  fprintf(file, "\n");
   for(uint32_t n=0;n<NUMBER_OF_LINES;n++) {
-    callback_print_algorithm(art, n, &flag);
+    callback_print_algorithm(file, art, n, &flag);
 
     if(n > space_up-1 && n < NUMBER_OF_LINES-space_down) {
       attr_type = art->attributes[attr_to_print]->type;
@@ -401,20 +402,20 @@ void print_ascii_x86(struct ascii* art, uint32_t la, void (*callback_print_algor
       attr_to_print++;
       
       space_right = 1 + (la - strlen(ATTRIBUTE_FIELDS[attr_type]));
-      printf("%s%s%s%*s%s%s%s\n", art->color1_text, ATTRIBUTE_FIELDS[attr_type], art->reset, space_right, "", art->color2_text, attr_value, art->reset);
+      fprintf(file, "%s%s%s%*s%s%s%s\n", art->color1_text, ATTRIBUTE_FIELDS[attr_type], art->reset, space_right, "", art->color2_text, attr_value, art->reset);
     }
-    else printf("\n");
+    else fprintf(file, "\n");
   }
-  printf("\n");
+  fprintf(file, "\n");
 }
 
-void print_ascii(struct ascii* art) {
+void print_ascii(FILE *file, struct ascii* art) {
   uint32_t longest_attribute = longest_attribute_length(art);
   
   if(art->vendor == CPU_VENDOR_INTEL)
-    print_ascii_x86(art, longest_attribute, &print_algorithm_intel);
+    print_ascii_x86(file, art, longest_attribute, &print_algorithm_intel);
   else if(art->vendor == CPU_VENDOR_AMD)
-    print_ascii_x86(art, longest_attribute, &print_algorithm_amd);
+    print_ascii_x86(file, art, longest_attribute, &print_algorithm_amd);
   else {
     printBug("Invalid CPU vendor: %d\n", art->vendor);
   }
@@ -426,6 +427,8 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct colors* cs) {
   if(art == NULL)
     return false;  
   
+  FILE *output_file;
+  
   char* uarch = get_str_uarch(cpu);
   char* manufacturing_process = get_str_process(cpu);
   char* sockets = get_str_sockets(cpu->topo);
@@ -436,7 +439,6 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct colors* cs) {
   char* avx = get_str_avx(cpu);
   char* fma = get_str_fma(cpu);
 
-
   char* l1i = get_str_l1i(cpu->cach);
   char* l1d = get_str_l1d(cpu->cach);
   char* l2 = get_str_l2(cpu->cach);
@@ -472,9 +474,14 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct colors* cs) {
   if(art->n_attributes_set > NUMBER_OF_LINES) {
     printBug("The number of attributes set is bigger than the max that can be displayed");
     return false;
+  }  
+  
+  if((output_file = fopen(OUTPUT_FILE, "w+")) == NULL) {
+    perror("fopen");
+    return false;    
   }
-
-  print_ascii(art);
+  
+  print_ascii(output_file, art);
 
   free(manufacturing_process);
   free(max_frequency);

src/common/udev.c

@@ -28,16 +28,21 @@ char* read_file(char* path, int* len) {
   return buf;
 }
 
-long get_freq_from_file(char* path) {
+long get_freq_from_file(char* path, bool hv_present) {
   int filelen;
   char* buf;
   if((buf = read_file(path, &filelen)) == NULL) {
-  #ifdef ARCH_X86
-    perror("open");
-    printBug("Could not open '%s'", path); 
-  #elif ARCH_ARM
-    printWarn("Could not open '%s'", path); 
-  #endif
+    #ifdef ARCH_X86
+      if(hv_present) {
+        printWarn("Could not open '%s'", path);
+      }
+      else {
+        perror("open");
+        printBug("Could not open '%s'", path);            
+      }
+    #elif ARCH_ARM
+      printWarn("Could not open '%s'", path); 
+    #endif
     return UNKNOWN_FREQ;
   }
 
@@ -64,14 +69,14 @@ long get_freq_from_file(char* path) {
   return ret/1000;
 }
 
-long get_max_freq_from_file(uint32_t core) {
+long get_max_freq_from_file(uint32_t core, bool hv_present) {
   char path[_PATH_FREQUENCY_MAX_LEN];
   sprintf(path, "%s%s/cpu%d%s%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_FREQUENCY, _PATH_FREQUENCY_MAX);
-  return get_freq_from_file(path);
+  return get_freq_from_file(path, hv_present);
 }
 
-long get_min_freq_from_file(uint32_t core) {
+long get_min_freq_from_file(uint32_t core, bool hv_present) {
   char path[_PATH_FREQUENCY_MAX_LEN];
   sprintf(path, "%s%s/cpu%d%s%s", _PATH_SYS_SYSTEM, _PATH_SYS_CPU, core, _PATH_FREQUENCY, _PATH_FREQUENCY_MIN);
-  return get_freq_from_file(path);
+  return get_freq_from_file(path, hv_present);
 }

src/common/udev.h

@@ -10,6 +10,8 @@
 #include <fcntl.h>
 #include <errno.h>
 
+#include "cpu.h"
+
 #define _PATH_SYS_SYSTEM        "/sys/devices/system"
 #define _PATH_SYS_CPU           "/cpu"
 #define _PATH_FREQUENCY         "/cpufreq"
@@ -20,7 +22,7 @@
 #define DEFAULT_FILE_SIZE       4096
 
 char* read_file(char* path, int* len);
-long get_max_freq_from_file(uint32_t core);
-long get_min_freq_from_file(uint32_t core);
+long get_max_freq_from_file(uint32_t core, bool hv_present);
+long get_min_freq_from_file(uint32_t core, bool hv_present);
 
 #endif

src/x86/apic.c

@@ -1,14 +1,17 @@
 #ifdef _WIN32
 #include <windows.h>
-#else
+#elif defined __linux__
 #define _GNU_SOURCE
 #include <sched.h>
+#elif defined __APPLE__
+#define UNUSED(x) (void)(x)
 #endif
 
 #include <stdlib.h>
 #include <stdint.h>
 #include <string.h>
 #include <stdio.h>
+#include <unistd.h>
 
 #include "apic.h"
 #include "cpuid_asm.h"
@@ -66,6 +69,7 @@ uint32_t get_apic_id(bool x2apic_id) {
   }
 }
 
+#ifndef __APPLE__
 bool bind_to_cpu(int cpu_id) {
   #ifdef _WIN32
     HANDLE process = GetCurrentProcess();
@@ -82,6 +86,7 @@ bool bind_to_cpu(int cpu_id) {
     return true;
   #endif  
 }
+#endif
 
 bool fill_topo_masks_apic(struct topology* topo) {
   uint32_t eax = 0x00000001;
@@ -254,8 +259,60 @@ void get_cache_topology_from_apic(struct topology* topo) {
   }
 }
 
+bool apic_array_full(uint32_t* apic_ids, int n) {
+  for(int i=0; i < n; i++) {
+    if(apic_ids[i] == (uint32_t) -1) return false;
+  }
+  return true;
+}
+
+void add_apic_to_array(uint32_t apic, uint32_t* apic_ids, int n) {
+  int i=0;
+  int last=0;
+  bool found = false;
+
+  while(!found && i < n) {
+    if(apic_ids[i] == apic) found = true;
+    if(apic_ids[i] != (uint32_t) -1) last = i+1;
+    i++;
+  }
+  
+  if(!found) { 
+    apic_ids[last] = apic;
+    //printf("Added %d\n", apic);
+  }
+}
+
+bool fill_apic_ids(uint32_t* apic_ids, int n, bool x2apic_id) {
+#ifdef __APPLE__    
+  // macOS extremely dirty approach...
+  printf("cpufetch is computing APIC IDs, please wait...\n");
+  bool end = false;
+  uint32_t apic;
+  for(int i=0; i < n; i++) apic_ids[i] = (uint32_t) -1;
+
+  while(!end) {
+    apic = get_apic_id(x2apic_id);
+    
+    add_apic_to_array(apic, apic_ids, n);
+    end = apic_array_full(apic_ids, n);    
+    usleep(1000);
+  }        
+#else
+  for(int i=0; i < n; i++) {
+    if(!bind_to_cpu(i)) {
+      printErr("Failed binding to CPU %d", i);
+      return false;
+    }
+    apic_ids[i] = get_apic_id(x2apic_id);
+  }
+#endif
+  return true;
+}
+
 bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) { 
-  uint32_t apic_id;
+  uint32_t apic_id;  
+  uint32_t* apic_ids = malloc(sizeof(uint32_t) * topo->total_cores);
   uint32_t* apic_pkg = malloc(sizeof(uint32_t) * topo->total_cores);
   uint32_t* apic_core = malloc(sizeof(uint32_t) * topo->total_cores);
   uint32_t* apic_smt = malloc(sizeof(uint32_t) * topo->total_cores);
@@ -281,12 +338,11 @@ bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
   
   get_cache_topology_from_apic(topo);  
   
-  for(int i=0; i < topo->total_cores; i++) {
-    if(!bind_to_cpu(i)) {
-      printErr("Failed binding to CPU %d", i);
-      return false;
-    }
-    apic_id = get_apic_id(x2apic_id);
+  if(!fill_apic_ids(apic_ids, topo->total_cores, x2apic_id))
+    return false;
+  
+  for(int i=0; i < topo->total_cores; i++) {    
+    apic_id = apic_ids[i];
     
     apic_pkg[i] = (apic_id & topo->apic->pkg_mask) >> topo->apic->pkg_mask_shift;
     apic_core[i] = (apic_id & topo->apic->core_mask) >> topo->apic->smt_mask_width;
@@ -337,6 +393,10 @@ bool get_topology_from_apic(struct cpuInfo* cpu, struct topology* topo) {
 } 
 
 uint32_t is_smt_enabled_amd(struct topology* topo) {
+#ifdef __APPLE__
+  UNUSED(topo);
+  return 1;
+#else  
   uint32_t id;
   
   for(int i = 0; i < topo->total_cores; i++) {
@@ -349,4 +409,5 @@ uint32_t is_smt_enabled_amd(struct topology* topo) {
   }
   
   return 1;  
+#endif  
 }

src/x86/cpuid.c

@@ -27,7 +27,6 @@ static const char *hv_vendors_string[] = {
   [HV_VENDOR_VMWARE]    = "VMwareVMware",
   [HV_VENDOR_XEN]       = "XenVMMXenVMM",
   [HV_VENDOR_PARALLELS] = "lrpepyh vr",
-  [HV_VENDOR_INVALID]   = NULL
 };
 
 static char *hv_vendors_name[] = {
@@ -594,7 +593,7 @@ struct cache* get_cache_info(struct cpuInfo* cpu) {
 
   uint32_t level;
 
-  // We use standart 0x00000004 for Intel
+  // We use standard 0x00000004 for Intel
   // We use extended 0x8000001D for AMD
   // or 0x80000005/6 for old AMD
   if(cpu->cpu_vendor == CPU_VENDOR_INTEL) {
@@ -661,13 +660,32 @@ struct frequency* get_frequency_info(struct cpuInfo* cpu) {
   
   if(cpu->maxLevels < 0x00000016) {
     #ifdef _WIN32
+      if(cpu->hv->present) {
+        printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000016, cpu->maxLevels);
+      }
+      else {
+        printErr("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000016, cpu->maxLevels);    
+      }
+      freq->base = UNKNOWN_FREQ;
+      freq->max = UNKNOWN_FREQ;
+    #elif defined __APPLE__
       printErr("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X)", 0x00000016, cpu->maxLevels);
       freq->base = UNKNOWN_FREQ;
       freq->max = UNKNOWN_FREQ;
     #else
       printWarn("Can't read frequency information from cpuid (needed level is 0x%.8X, max is 0x%.8X). Using udev", 0x00000016, cpu->maxLevels);
       freq->base = UNKNOWN_FREQ;
-      freq->max = get_max_freq_from_file(0);
+      freq->max = get_max_freq_from_file(0, cpu->hv->present);
+      
+      if(freq->max == 0) {
+        if(cpu->hv->present) {
+          printWarn("Read max CPU frequency and got 0 MHz");
+        }
+        else {
+          printBug("Read max CPU frequency and got 0 MHz");    
+        }
+        freq->max = UNKNOWN_FREQ;
+      }
     #endif
   }
   else {
@@ -682,11 +700,21 @@ struct frequency* get_frequency_info(struct cpuInfo* cpu) {
     freq->max = ebx;    
     
     if(freq->base == 0) {
-      printWarn("Read base CPU frequency and got 0 MHz");
+      if(cpu->hv->present) {
+        printWarn("Read base CPU frequency and got 0 MHz");
+      }
+      else {
+        printBug("Read base CPU frequency and got 0 MHz");    
+      }
       freq->base = UNKNOWN_FREQ;
     }
     if(freq->max == 0) {
-      printWarn("Read max CPU frequency and got 0 MHz");
+      if(cpu->hv->present) {
+        printWarn("Read max CPU frequency and got 0 MHz");
+      }
+      else {
+        printBug("Read max CPU frequency and got 0 MHz");    
+      }
       freq->max = UNKNOWN_FREQ;
     }
   }
@@ -866,12 +894,19 @@ char* get_str_fma(struct cpuInfo* cpu) {
   return string;
 }
 
-/*** DEBUG ***/
-
 void print_debug(struct cpuInfo* cpu) {
+  uint32_t eax = 0x00000001;
+  uint32_t ebx = 0;
+  uint32_t ecx = 0;
+  uint32_t edx = 0;
+  
+  cpuid(&eax, &ebx, &ecx, &edx);
+  
   printf("%s\n", cpu->cpu_name);
-  printf("- Max standart level: 0x%.8X\n", cpu->maxLevels);
+  if(cpu->hv->present) printf("- Hypervisor: %s\n", cpu->hv->hv_name);
+  printf("- Max standard level: 0x%.8X\n", cpu->maxLevels);
   printf("- Max extended level: 0x%.8X\n", cpu->maxExtendedLevels);
+  printf("- CPUID dump: 0x%.8X\n", eax);
 
   free_cpuinfo_struct(cpu);
 }

src/x86/uarch.c

@@ -11,6 +11,7 @@
  *   http://www.etallen.com/cpuid.html
  * - This should be updated from time to time, to support newer CPUs. A good reference to look at:
  *   https://en.wikichip.org/
+ *   http://instlatx64.atw.hu/
  */
 
 // From Todd Allen:
@@ -63,6 +64,9 @@ enum {
   UARCH_BROADWELL,
   UARCH_AIRMONT,
   UARCH_KABY_LAKE,
+  UARCH_COMET_LAKE,
+  UARCH_AMBER_LAKE,
+  UARCH_WHISKEY_LAKE,
   UARCH_SKYLAKE,
   UARCH_CASCADE_LAKE,
   UARCH_COOPER_LAKE,
@@ -123,7 +127,7 @@ void fill_uarch(struct uarch* arch, char* str, MICROARCH u, uint32_t process) {
   arch->process= process;
 }
 
-// iNApired in Todd Allen's decode_uarch_intel
+// Inspired in Todd Allen's decode_uarch_intel
 struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, uint32_t m, int s) {
   struct uarch* arch = malloc(sizeof(struct uarch));
   
@@ -134,7 +138,7 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   // S: Stepping                                                                   //
   // ----------------------------------------------------------------------------- //
   //                EF  F  EM   M   S                                              //
-  UARCH_START  
+  UARCH_START
   CHECK_UARCH(arch, 0,  5,  0,  0, NA, "P5",              UARCH_P5,              800)
   CHECK_UARCH(arch, 0,  5,  0,  1, NA, "P5",              UARCH_P5,              800)
   CHECK_UARCH(arch, 0,  5,  0,  2, NA, "P5",              UARCH_P5,              UNK)
@@ -215,7 +219,10 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 0,  6,  8, 10, NA, "Tremont",         UARCH_TREMONT,          10) // no spec update; only geekbench.com example
   CHECK_UARCH(arch, 0,  6,  8, 12, NA, "Willow Cove",     UARCH_WILLOW_COVE,      10) // found only on en.wikichip.org
   CHECK_UARCH(arch, 0,  6,  8, 13, NA, "Willow Cove",     UARCH_WILLOW_COVE,      10) // LX*
-  CHECK_UARCH(arch, 0,  6,  8, 14, NA, "Kaby Lake",       UARCH_KABY_LAKE,        14)
+  CHECK_UARCH(arch, 0,  6,  8, 14,  9, "Amber Lake",      UARCH_AMBER_LAKE,       14) // wikichip
+  CHECK_UARCH(arch, 0,  6,  8, 14, 10, "Kaby Lake",       UARCH_KABY_LAKE,        14) // wikichip
+  CHECK_UARCH(arch, 0,  6,  8, 14, 11, "Whiskey Lake",    UARCH_WHISKEY_LAKE,     14) // wikichip
+  CHECK_UARCH(arch, 0,  6,  8, 14, 12, "Comet Lake",      UARCH_COMET_LAKE,       14) // wikichip
   CHECK_UARCH(arch, 0,  6,  9,  6, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
   CHECK_UARCH(arch, 0,  6,  9, 12, NA, "Tremont",         UARCH_TREMONT,          10) // LX*
   CHECK_UARCH(arch, 0,  6,  9, 13, NA, "Sunny Cove",      UARCH_SUNNY_COVE,       10) // LX*
@@ -224,8 +231,8 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 0,  6,  9, 14, 11, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
   CHECK_UARCH(arch, 0,  6,  9, 14, 12, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
   CHECK_UARCH(arch, 0,  6,  9, 14, 13, "Coffee Lake",     UARCH_COFFE_LAKE,       14)
-  CHECK_UARCH(arch, 0,  6, 10,  5, NA, "Kaby Lake",       UARCH_KABY_LAKE,        14) // LX*
-  CHECK_UARCH(arch, 0,  6, 10,  6, NA, "Kaby Lake",       UARCH_KABY_LAKE,        14) // no spec update; only iNAtlatx64 example
+  CHECK_UARCH(arch, 0,  6, 10,  5, NA, "Comet Lake",      UARCH_COMET_LAKE,       14) // wikichip
+  CHECK_UARCH(arch, 0,  6, 10,  6, NA, "Comet Lake",      UARCH_COMET_LAKE,       14) // instlatx64.atw.hu (i7-10710U)
   CHECK_UARCH(arch, 0, 11,  0,  0, NA, "Knights Ferry",   UARCH_KNIGHTS_FERRY,    45) // found only on en.wikichip.org
   CHECK_UARCH(arch, 0, 11,  0,  1, NA, "Knights Corner",  UARCH_KNIGHTS_CORNER,   22)
   CHECK_UARCH(arch, 0, 15,  0,  0, NA, "Willamette",      UARCH_WILLAMETTE,      180)
@@ -238,7 +245,7 @@ struct uarch* get_uarch_from_cpuid_intel(uint32_t ef, uint32_t f, uint32_t em, u
   CHECK_UARCH(arch, 1, 15,  0,  1, NA, "Itanium2",        UARCH_ITANIUM2,        130)
   CHECK_UARCH(arch, 1, 15,  0,  2, NA, "Itanium2",        UARCH_ITANIUM2,        130)
   UARCH_END
-    
+ 
   return arch;
 }
 
@@ -351,7 +358,6 @@ struct uarch* get_uarch_from_cpuid(struct cpuInfo* cpu, uint32_t ef, uint32_t f,
 }
 
 bool vpus_are_AVX512(struct cpuInfo* cpu) {
-  return cpu->arch->uarch != UARCH_ICE_LAKE;    
   return cpu->arch->uarch != UARCH_ICE_LAKE;
 }
 
@@ -359,10 +365,7 @@ bool is_knights_landing(struct cpuInfo* cpu) {
   return cpu->arch->uarch == UARCH_KNIGHTS_LANDING;  
 }
 
-int get_number_of_vpus(struct cpuInfo* cpu) {
-  if(cpu->cpu_vendor == CPU_VENDOR_AMD)
-    return 1;
-  
+int get_number_of_vpus(struct cpuInfo* cpu) {  
   switch(cpu->arch->uarch) {
       case UARCH_HASWELL:
       case UARCH_BROADWELL:
@@ -370,13 +373,20 @@ int get_number_of_vpus(struct cpuInfo* cpu) {
       case UARCH_SKYLAKE:
       case UARCH_CASCADE_LAKE:                    
       case UARCH_KABY_LAKE:
+      case UARCH_COMET_LAKE:
+      case UARCH_AMBER_LAKE:
+      case UARCH_WHISKEY_LAKE:
       case UARCH_COFFE_LAKE:
       case UARCH_PALM_COVE:    
       
       case UARCH_KNIGHTS_LANDING:
       case UARCH_KNIGHTS_MILL:
           
-      case UARCH_ICE_LAKE:      
+      case UARCH_ICE_LAKE:   
+          
+      // Right now is just a guess!
+      case UARCH_ZEN2:
+      case UARCH_ZEN3:    
         return 2;
       default:
         return 1;