Quick test

README.md

@@ -45,7 +45,6 @@ cpufetch is a command-line tool written in C that displays the CPU information i
   - [3.1 x86_64](#31-x86_64)
   - [3.2 ARM](#32-arm)
   - [3.3 PowerPC](#33-powerpc)
-  - [3.4 RISC-V](#34-risc-v)
 - [4. Colors](#4-colors)
   - [4.1 Specifying a name](#41-specifying-a-name)
   - [4.2 Specifying the colors in RGB format](#42-specifying-the-colors-in-rgb-format)
@@ -121,11 +120,6 @@ make
 <p align="center"><img width=90% src="pictures/ibm.png"></p>
 <p align="center">Talos II</p>
 
-## 3.4 RISC-V
-
-<p align="center"><img width=80% src="pictures/starfive.png"></p>
-<p align="center">StarFive VisionFive 2</p>
-
 ## 4. Colors
 By default, `cpufetch` will print the CPU logo with the system colorscheme. However, you can set a custom color scheme in two different ways:
 

src/arm/midr.c

@@ -431,6 +431,8 @@ struct cpuInfo* get_cpu_info(void) {
   struct cpuInfo* cpu = malloc(sizeof(struct cpuInfo));
   init_cpu_info(cpu);
 
+  test_thread_siblings_list();
+
   #ifdef __linux__
     return get_cpu_info_linux(cpu);
   #elif defined __APPLE__ || __MACH__
@@ -513,10 +515,6 @@ void print_debug(struct cpuInfo* cpu) {
     }
   }
 
-  if (cpu->feat->SVE || cpu->feat->SVE2) {
-    printf("- cntb: %d\n", (int) cpu->feat->cntb);
-  }
-
   #if defined(__APPLE__) || defined(__MACH__)
     printf("hw.cpufamily: 0x%.8X\n", get_sys_info_by_name("hw.cpufamily"));
     printf("hw.cpusubfamily: 0x%.8X\n", get_sys_info_by_name("hw.cpusubfamily"));

src/arm/soc.c

@@ -424,9 +424,6 @@ bool match_mediatek(char* soc_name, struct system_on_chip* soc) {
 }
 
 /*
- * Good sources:
- * https://www.geektopia.es/es/products/company/qualcomm/socs/
- *
  * APQ: Application Processor Qualcomm
  * MSM: Mobile Station Modem
  * In a APQXXXX or MSMXXXX, the second digit represents:
@@ -584,25 +581,14 @@ bool match_qualcomm(char* soc_name, struct system_on_chip* soc) {
   SOC_EQ(tmp, "SM8250-AB",      "865+",      SOC_SNAPD_SM8250_AB,      soc,  7)
   SOC_EQ(tmp, "SM8350",         "888",       SOC_SNAPD_SM8350,         soc,  5)
   SOC_EQ(tmp, "SM8350-AC",      "888+",      SOC_SNAPD_SM8350,         soc,  5)
-  // Snapdragon Gen 4 //
+  // Snapdragon Gen //
-  SOC_EQ(tmp, "SM4375",         "4 Gen 1",   SOC_SNAPD_SM4375,         soc,  6)
   SOC_EQ(tmp, "SM4450",         "4 Gen 2",   SOC_SNAPD_SM4450,         soc,  4)
-  SOC_EQ(tmp, "SM4635",         "4s Gen 2",  SOC_SNAPD_SM4635,         soc,  4)
-  // Snapdragon Gen 6 //
-  SOC_EQ(tmp, "SM6375-AC",      "6s Gen 3",  SOC_SNAPD_SM6375_AC,      soc,  6)
   SOC_EQ(tmp, "SM6450",         "6 Gen 1",   SOC_SNAPD_SM6450,         soc,  4)
-  // Snapdragon Gen 7 //
   SOC_EQ(tmp, "SM7435-AB",      "7s Gen 2",  SOC_SNAPD_SM7435_AB,      soc,  4)
   SOC_EQ(tmp, "SM7450",         "7 Gen 1",   SOC_SNAPD_SM7450,         soc,  4)
   SOC_EQ(tmp, "SM7475",         "7+ Gen 2",  SOC_SNAPD_SM7475,         soc,  4)
-  SOC_EQ(tmp, "SM7550-AB",      "7 Gen 3",   SOC_SNAPD_SM7550_AB,      soc,  4)
-  SOC_EQ(tmp, "SM7675-AB",      "7+ Gen 3",  SOC_SNAPD_SM7675_AB,      soc,  4)
-  // Snapdragon Gen 8 //
   SOC_EQ(tmp, "SM8450",         "8 Gen 1",   SOC_SNAPD_SM8450,         soc,  4)
   SOC_EQ(tmp, "SM8475",         "8+ Gen 1",  SOC_SNAPD_SM8475,         soc,  4)
-  SOC_EQ(tmp, "SM8550-AB",      "8 Gen 2",   SOC_SNAPD_SM8550_AB,      soc,  4)
-  SOC_EQ(tmp, "SM8635",         "8s Gen 3",  SOC_SNAPD_SM8635,         soc,  4)
-  SOC_EQ(tmp, "SM8650-AB",      "8 Gen 3",   SOC_SNAPD_SM8650_AB,      soc,  4)
   SOC_END
 }
 

src/arm/socs.h

@@ -271,16 +271,13 @@ enum {
   SOC_SNAPD_SDM660,
   SOC_SNAPD_SM6115,
   SOC_SNAPD_SM6125,
-  SOC_SNAPD_SM6375_AC,
   SOC_SNAPD_SM6450,
   SOC_SNAPD_SDM670,
   SOC_SNAPD_SM6150,
   SOC_SNAPD_SM6350,
   SOC_SNAPD_SDM710,
   SOC_SNAPD_SDM712,
-  SOC_SNAPD_SM4375,
   SOC_SNAPD_SM4450,
-  SOC_SNAPD_SM4635,
   SOC_SNAPD_SM7125,
   SOC_SNAPD_SM7150_AA,
   SOC_SNAPD_SM7150_AB,
@@ -292,8 +289,6 @@ enum {
   SOC_SNAPD_SM7435_AB,
   SOC_SNAPD_SM7450,
   SOC_SNAPD_SM7475,
-  SOC_SNAPD_SM7550_AB,
-  SOC_SNAPD_SM7675_AB,
   SOC_SNAPD_MSM8974AA,
   SOC_SNAPD_MSM8974AB,
   SOC_SNAPD_MSM8974AC,
@@ -315,9 +310,6 @@ enum {
   SOC_SNAPD_SM8350,
   SOC_SNAPD_SM8450,
   SOC_SNAPD_SM8475,
-  SOC_SNAPD_SM8550_AB,
-  SOC_SNAPD_SM8635,
-  SOC_SNAPD_SM8650_AB,
   // APPLE
   SOC_APPLE_M1,
   SOC_APPLE_M1_PRO,
@@ -390,7 +382,7 @@ inline static VENDOR get_soc_vendor_from_soc(SOC soc) {
   else if(soc >= SOC_KUNPENG_920 && soc <= SOC_KUNPENG_930) return SOC_VENDOR_KUNPENG;
   else if(soc >= SOC_EXYNOS_3475 && soc <= SOC_EXYNOS_880) return SOC_VENDOR_EXYNOS;
   else if(soc >= SOC_MTK_MT6893 && soc <= SOC_MTK_MT8783) return SOC_VENDOR_MEDIATEK;
-  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8650_AB) return SOC_VENDOR_SNAPDRAGON;
+  else if(soc >= SOC_SNAPD_QSD8650 && soc <= SOC_SNAPD_SM8475) return SOC_VENDOR_SNAPDRAGON;
   else if(soc >= SOC_APPLE_M1 && soc <= SOC_APPLE_M3_MAX) return SOC_VENDOR_APPLE;
   else if(soc >= SOC_ALLWINNER_A10 && soc <= SOC_ALLWINNER_R328) return SOC_VENDOR_ALLWINNER;
   else if(soc >= SOC_ROCKCHIP_3288 && soc <= SOC_ROCKCHIP_3588) return SOC_VENDOR_ROCKCHIP;

src/arm/sve.c

@@ -7,9 +7,10 @@ uint64_t sve_cntb(void) {
     uint64_t x0 = 0;
     __asm volatile("cntb %0"
          : "=r"(x0));
+    printf("cntb=%ld\n", x0);
     return x0;
   #else
-    printWarn("sve_cntb: Hardware supports SVE, but it was not enabled by the compiler");
+    printWarn("sve_cntb: SVE not enabled by the compiler");
     return 0;
   #endif
 }

src/common/cpu.h

@@ -126,7 +126,7 @@ struct features {
   bool CRC32;
   bool SVE;
   bool SVE2;
-  uint64_t cntb;
+  uint32_t cntb;
 #endif  
 };
 

src/common/global.c

@@ -62,7 +62,7 @@
 #endif
 
 #ifndef GIT_FULL_VERSION
-  static const char* VERSION = "1.06";
+  static const char* VERSION = "1.05";
 #endif
 
 enum {

src/common/printer.c

@@ -634,10 +634,9 @@ bool print_cpufetch_x86(struct cpuInfo* cpu, STYLE s, struct color** cs, struct
     }
 
     // Show the most modern vector instructions.
+    // If AVX is supported show it, otherwise show SSE
     if (strcmp(avx, "No") == 0) {
-      if (strcmp(sse, "No") != 0) {
+      setAttribute(art, ATTRIBUTE_SSE, sse);
-        setAttribute(art, ATTRIBUTE_SSE, sse);
-      }
     }
     else {
       setAttribute(art, ATTRIBUTE_AVX, avx);

src/common/udev.c

@@ -315,6 +315,24 @@ int get_num_caches_by_level(struct cpuInfo* cpu, uint32_t level) {
   return ret;
 }
 
+// Just to check what is going on with missing thread_siblings_list
+void test_thread_siblings_list(void) {
+  int num_cores = 12;
+  int filelen;
+  char* buf = NULL;
+
+  for(int i=0; i < num_cores; i++) {
+    char* path = ecalloc(500, sizeof(char));
+    sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", i);
+
+    if((buf = read_file(path, &filelen)) == NULL) {
+      printf("Could not open '%s'", path);      
+    }
+
+    printf("%s: %s\n", path, buf);
+  }
+}
+
 int get_num_sockets_package_cpus(struct topology* topo) {
   // Get number of sockets using
   // /sys/devices/system/cpu/cpu*/topology/package_cpus

src/common/udev.h

@@ -43,5 +43,6 @@ int get_num_sockets_package_cpus(struct topology* topo);
 int get_ncores_from_cpuinfo(void);
 char* get_field_from_cpuinfo(char* CPUINFO_FIELD);
 bool is_devtree_compatible(char* str);
+void test_thread_siblings_list(void);
 
 #endif

src/x86/cpuid.c

@@ -709,9 +709,9 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
     topo->total_cores_module = topo->total_cores;
   }
 
-  bool toporet = false;
   switch(cpu->cpu_vendor) {
     case CPU_VENDOR_INTEL:
+      bool toporet = false;
       if (cpu->maxLevels >= 0x00000004) {
         toporet = get_topology_from_apic(cpu, topo);
       }
@@ -750,15 +750,10 @@ struct topology* get_topology_info(struct cpuInfo* cpu, struct cache* cach, int
         }
       }
       else {
-        #ifdef __linux__
+        printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000008, cpu->maxExtendedLevels);
-          printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X), using udev...", 0x80000008, cpu->maxExtendedLevels);
+        topo->physical_cores = 1;
-          get_topology_from_udev(topo);
+        topo->logical_cores = 1;
-        #else
+        topo->smt_supported = 1;
-          printWarn("Can't read topology information from cpuid (needed extended level is 0x%.8X, max is 0x%.8X)", 0x80000008, cpu->maxExtendedLevels);
-          topo->physical_cores = 1;
-          topo->logical_cores = 1;
-          topo->smt_supported = 1;
-        #endif
       }
 
       if (cpu->maxLevels >= 0x00000001) {
@@ -1101,14 +1096,8 @@ char* get_str_sse(struct cpuInfo* cpu) {
       last+=SSE4_2_sl;
   }
 
-  if (last == 0) {
+  //Purge last comma
-    snprintf(string, 2+1, "No");
+  string[last-1] = '\0';
-  }
-  else {
-    //Purge last comma
-    string[last-1] = '\0';
-  }
-
   return string;
 }